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Added resiliancy against vertical path elements.

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This commit is contained in:
Markus Lampert 2016-12-12 22:41:18 -08:00
parent c1fc88c6a3
commit d6c588e57b
1 changed files with 17 additions and 8 deletions
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25
src/Mod/Path/PathScripts/PathDressupHoldingTags.py
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@ -279,17 +279,20 @@ class MapWireToTag:
else: else:
plinths.append(p1) plinths.append(p1)
# remove all edges that are connected to the plinths of the (former) internal struts # remove all edges that are connected to the plinths of the (former) internal struts
# including the edge that connects the entry and exit point directly
for e in copy.copy(inputEdges): for e in copy.copy(inputEdges):
if PathGeom.edgeConnectsTo(e, self.entry) and PathGeom.edgeConnectsTo(e, self.exit):
debugEdge(e, '......... X1')
inputEdges.remove(e)
continue
for p in plinths: for p in plinths:
if PathGeom.edgeConnectsTo(e, p): if PathGeom.edgeConnectsTo(e, p):
debugEdge(e, '......... X2') debugEdge(e, '......... X1')
inputEdges.remove(e) inputEdges.remove(e)
break break
# if there are any edges beside a direct edge remaining, the direct edge between
# entry and exit is redundant
if len(inputEdges) > 1:
for e in copy.copy(inputEdges):
if PathGeom.edgeConnectsTo(e, self.entry) and PathGeom.edgeConnectsTo(e, self.exit):
debugEdge(e, '......... X2')
inputEdges.remove(e)
# the remaining edges form a walk around the tag # the remaining edges form a walk around the tag
# they need to be ordered and potentially flipped though # they need to be ordered and potentially flipped though
outputEdges = [] outputEdges = []
@ -321,6 +324,13 @@ class MapWireToTag:
# print("xxxxxx (%.2f, %.2f, %.2f)" % (p.x, p.y, p.z)) # print("xxxxxx (%.2f, %.2f, %.2f)" % (p.x, p.y, p.z))
return outputEdges return outputEdges
def shell(self):
shell = self.wire.extrude(FreeCAD.Vector(0, 0, 10))
redundant = filter(lambda f: f.Area == 0, shell.childShapes())
if redundant:
return shell.removeShape(redundant)
return shell
def add(self, edge): def add(self, edge):
self.tail = None self.tail = None
if self.tag.solid.isInside(edge.valueAt(edge.LastParameter), 0.000001, True): if self.tag.solid.isInside(edge.valueAt(edge.LastParameter), 0.000001, True):
@ -335,8 +345,7 @@ class MapWireToTag:
self.tail = tail self.tail = tail
self.exit = i self.exit = i
if self.wire: if self.wire:
shell = self.wire.extrude(FreeCAD.Vector(0, 0, 10)) face = self.shell().common(self.tag.solid)
face = shell.common(self.tag.solid)
for e,flip in self.cleanupEdges(face.Edges): for e,flip in self.cleanupEdges(face.Edges):
debugEdge(e, '++++++++ %s' % ('.' if not flip else '@')) debugEdge(e, '++++++++ %s' % ('.' if not flip else '@'))