diff --git a/README b/README index 8514117..b3ef2dd 100644 --- a/README +++ b/README @@ -63,7 +63,6 @@ Design Principles TODO (as of February, 2013) short-term (1 month): -* finish lut_encoding test * finish dist_mem test * support block memory * example: counter (including clock, jtag) diff --git a/libs/control.c b/libs/control.c index 78a46cf..0dc6879 100644 --- a/libs/control.c +++ b/libs/control.c @@ -838,8 +838,7 @@ int fdev_set_required_pins(struct fpga_model* model, int y, int x, int type, int type_idx) { struct fpga_device* dev; - int req_inpins[6]; - int i, j, k, rc; + int req_inpins, i, j, rc; RC_CHECK(model); dev = fdev_p(model, y, x, type, type_idx); @@ -897,32 +896,18 @@ int fdev_set_required_pins(struct fpga_model* model, int y, int x, int type, add_req_inpin(dev, LI_AX+i); } - for (j = 0; j < 6; j++) - req_inpins[j] = 0; + req_inpins = 0; if (dev->u.logic.a2d[i].flags & LUT5VAL_SET) { // A6 must be high/vcc if lut5 is used - req_inpins[5] = 1; - for (j = 0; j < 32; j++) { - if (!(dev->u.logic.a2d[i].lut5_val & (1ULL << j))) - continue; - for (k = 0; k < 5; k++) { - if (j & (1<u.logic.a2d[i].lut5_val, 32); } if (dev->u.logic.a2d[i].flags & LUT6VAL_SET) { - for (j = 0; j < 64; j++) { - if (!(dev->u.logic.a2d[i].lut6_val & (1ULL << j))) - continue; - for (k = 0; k < 6; k++) { - if (j & (1<u.logic.a2d[i].lut6_val, + (dev->u.logic.a2d[i].flags & LUT5VAL_SET) ? 32 : 64); } for (j = 0; j < 6; j++) { - if (req_inpins[j]) + if (req_inpins & (1<u.logic.a2d[i].ff_mux == MUX_XOR diff --git a/libs/helper.c b/libs/helper.c index 1602d8c..265fea4 100644 --- a/libs/helper.c +++ b/libs/helper.c @@ -122,6 +122,8 @@ static int bool_nextlen(const char *expr, int len) if (expr[i] < '1' || expr[i] > '6') return -1; return i+1; } + if (expr[i] == '0' || expr[i] == '1') + return i+1; return -1; } @@ -236,7 +238,11 @@ int bool_str2bits(const char *str, int str_len, uint64_t *u64, int num_bits) for (j = 0; j < sizeof(vars)/sizeof(*vars); j++) vars[j] = (i & (1<> (1<