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merged bit2txt into bit2fp

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This commit is contained in:
Wolfgang Spraul 2012-08-18 13:40:17 +02:00
parent 277ffc4f6d
commit 0a5183cefd
13 changed files with 1581 additions and 1764 deletions
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2
.gitignore vendored
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@ -1,5 +1,3 @@
bit2txt
bit2txt.o
draw_svg_tiles
draw_svg_tiles.o
helper.o

13
Makefile
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@ -18,7 +18,7 @@ LDLIBS += `pkg-config libxml-2.0 --libs`
MODEL_OBJ = model_main.o model_tiles.o model_devices.o model_ports.o model_conns.o model_switches.o model_helper.o
all: new_fp fp2bit bit2fp draw_svg_tiles \
autotest bit2txt hstrrep sort_seq merge_seq pair2net
autotest hstrrep sort_seq merge_seq pair2net
autotest: autotest.o $(MODEL_OBJ) floorplan.o control.o helper.o model.h
@ -46,10 +46,6 @@ draw_svg_tiles: draw_svg_tiles.o $(MODEL_OBJ) helper.o control.o
draw_svg_tiles.o: draw_svg_tiles.c model.h helper.h
bit2txt: bit2txt.o helper.o
bit2txt.o: bit2txt.c helper.h
pair2net: pair2net.o helper.o
pair2net.o: pair2net.c helper.h
@ -123,8 +119,7 @@ compare.%: xc6slx9_empty.%
@cat $<|awk '{if ($$1=="sw") printf "%s %s %s %s %s\n",$$2,$$3,$$4,$$5,$$6}'|sort >$@
clean:
rm -f bit2txt bit2txt.o \
draw_svg_tiles draw_svg_tiles.o \
rm -f draw_svg_tiles draw_svg_tiles.o \
new_fp new_fp.o \
helper.o $(MODEL_OBJ) hstrrep hstrrep.o \
sort_seq sort_seq.o \
@ -148,6 +143,6 @@ clean:
install: all
mkdir -p $(DESTDIR)/$(PREFIX)/bin/
install -m 755 new_fp $(DESTDIR)/$(PREFIX)/bin/
install -m 755 bit2txt $(DESTDIR)/$(PREFIX)/bin/
install -m 755 bit2fp $(DESTDIR)/$(PREFIX)/bin/
uninstall:
rm -f $(DESTDIR)/$(PREFIX)/bin/{new_fp,bit2txt}
rm -f $(DESTDIR)/$(PREFIX)/bin/{new_fp,bit2fp}

1
README
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@ -27,7 +27,6 @@ Design Utilities
fpgatools Development Utilities
- autotest executes test suite
- bit2txt dumps .bit bitstream as text
- hstrrep high-speed hashed array based search and replace util
- sort_seq sorts line-based text file by sequence numbers in strings
- merge_seq merges a pre-sorted text file into wire sequences

26
autotest.c
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@ -75,12 +75,12 @@ static int diff_printf(struct test_state* tstate)
strcpy(&path[path_base], ".fp");
dest_f = fopen(path, "w");
if (!dest_f) { rc = -1; FAIL(); }
if (!dest_f) FAIL(errno);
rc = printf_devices(dest_f, tstate->model, /*config_only*/ 1);
if (rc) FAIL();
if (rc) FAIL(rc);
rc = printf_switches(dest_f, tstate->model, /*enabled_only*/ 1);
if (rc) FAIL();
if (rc) FAIL(rc);
fclose(dest_f);
dest_f = 0;
@ -88,11 +88,11 @@ static int diff_printf(struct test_state* tstate)
snprintf(tmp, sizeof(tmp), "./autotest_diff.sh %s %s.fp >%s.log 2>&1",
prior_fp, path, path);
rc = system(tmp);
if (rc) FAIL();
if (rc) FAIL(rc);
strcpy(&path[path_base], ".diff");
rc = dump_file(path);
if (rc) FAIL();
if (rc) FAIL(rc);
tstate->next_diff_counter++;
return 0;
@ -132,13 +132,13 @@ int main(int argc, char** argv)
strcpy(tstate.tmp_dir, AUTOTEST_TMP_DIR);
mkdir(tstate.tmp_dir, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH);
rc = diff_start(&tstate, "and");
if (rc) FAIL();
if (rc) FAIL(rc);
// configure P46
rc = fpga_find_iob(&model, "P46", &P46_y, &P46_x, &P46_idx);
if (rc) FAIL();
if (rc) FAIL(rc);
P46_dev = fpga_dev(&model, P46_y, P46_x, DEV_IOB, P46_idx);
if (!P46_dev) { rc = -1; FAIL(); }
if (!P46_dev) FAIL(EINVAL);
P46_dev->instantiated = 1;
strcpy(P46_dev->iob.istandard, IO_LVCMOS33);
P46_dev->iob.bypass_mux = BYPASS_MUX_I;
@ -146,9 +146,9 @@ int main(int argc, char** argv)
// configure P48
rc = fpga_find_iob(&model, "P48", &P48_y, &P48_x, &P48_idx);
if (rc) FAIL();
if (rc) FAIL(rc);
P48_dev = fpga_dev(&model, P48_y, P48_x, DEV_IOB, P48_idx);
if (!P48_dev) { rc = -1; FAIL(); }
if (!P48_dev) FAIL(EINVAL);
P48_dev->instantiated = 1;
strcpy(P48_dev->iob.ostandard, IO_LVCMOS33);
P48_dev->iob.drive_strength = 12;
@ -158,13 +158,13 @@ int main(int argc, char** argv)
// configure logic
logic_dev = fpga_dev(&model, /*y*/ 68, /*x*/ 13, DEV_LOGIC, /*LOGIC_X*/ 1);
if (!logic_dev) { rc = -1; FAIL(); }
if (!logic_dev) FAIL(EINVAL);
logic_dev->instantiated = 1;
logic_dev->logic.D_used = 1;
rc = fpga_set_lut(&model, logic_dev, D6_LUT, "A3", ZTERM);
if (rc) FAIL();
if (rc) FAIL(rc);
#if 0
#if 1
rc = diff_printf(&tstate);
if (rc) goto fail;
#endif

32
bit2fp.c
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@ -12,9 +12,10 @@
int main(int argc, char** argv)
{
struct fpga_model model;
FILE* fbits = 0;
int bits_only, file_arg, rc = -1;
struct fpga_config config;
// parameters
if (argc < 2) {
fprintf(stderr,
"\n"
@ -23,7 +24,6 @@ int main(int argc, char** argv)
"\n", argv[0], argv[0]);
goto fail;
}
bits_only = 0;
file_arg = 1;
if (!strcmp(argv[1], "--bits-only")) {
@ -31,22 +31,30 @@ int main(int argc, char** argv)
file_arg = 2;
}
fbits = fopen(argv[file_arg], "r");
if (!fbits) {
fprintf(stderr, "Error opening %s.\n", argv[file_arg]);
goto fail;
// read bitstream file
{
FILE* fbits = fopen(argv[file_arg], "r");
if (!fbits) {
fprintf(stderr, "Error opening %s.\n", argv[file_arg]);
goto fail;
}
rc = read_bitfile(&config, fbits);
fclose(fbits);
if (rc) FAIL(rc);
}
// build model and fill from bitstream
if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING)))
goto fail;
XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING))) FAIL(rc);
if ((rc = extract_model(&config, &model))) FAIL(rc);
if ((rc = read_bits(&model, fbits))) goto fail;
// dump model
if ((rc = write_floorplan(stdout, &model,
bits_only ? FP_BITS_ONLY : FP_BITS_DEFAULT))) goto fail;
fclose(fbits);
bits_only ? FP_BITS_ONLY : FP_BITS_DEFAULT))) FAIL(rc);
// dump what doesn't fit into the model
if ((rc = dump_config(&config, DUMP_BITS))) FAIL(rc);
return EXIT_SUCCESS;
fail:
if (fbits) fclose(fbits);
return rc;
}

1634
bit2txt.c
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File diff suppressed because it is too large Load Diff

1450
bits.c
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File diff suppressed because it is too large Load Diff

85
bits.h
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@ -5,15 +5,84 @@
// For details see the UNLICENSE file at the root of the source tree.
//
struct fpga_config
{
int param1, param2;
uint8_t* bits;
uint8_t* bram_data;
// The highest 4 bits are the binary revision and not
// used when performing IDCODE verification.
// ug380, Configuration Sequence, page 78
#define IDCODE_MASK 0x0FFFFFFF
#define XC6SLX4 0x04000093
#define XC6SLX9 0x04001093
#define XC6SLX16 0x04002093
#define XC6SLX25 0x04004093
#define XC6SLX25T 0x04024093
#define XC6SLX45 0x04008093
#define XC6SLX45T 0x04028093
#define XC6SLX75 0x0400E093
#define XC6SLX75T 0x0402E093
#define XC6SLX100 0x04011093
#define XC6SLX100T 0x04031093
#define XC6SLX150 0x0401D093
// xc6 configuration registers, documentation in ug380, page90
enum fpga_config_reg {
CRC = 0, FAR_MAJ, FAR_MIN, FDRI, FDRO, CMD, CTL, MASK, STAT, LOUT, COR1,
COR2, PWRDN_REG, FLR, IDCODE, CWDT, HC_OPT_REG, CSBO = 18,
GENERAL1, GENERAL2, GENERAL3, GENERAL4, GENERAL5, MODE_REG, PU_GWE,
PU_GTS, MFWR, CCLK_FREQ, SEU_OPT, EXP_SIGN, RDBK_SIGN, BOOTSTS,
EYE_MASK, CBC_REG
};
// read_bitfile() write_bitfile()
// get_bit() set_bit()
#define REG_NOOP -1 // pseudo register for noops
#define FAR_MAJ_O 0
#define FAR_MIN_O 1
struct fpga_config_reg_rw
{
enum fpga_config_reg reg;
union {
int int_v;
int far[2]; // 0 (FAR_MAJ_O) = major, 1 (FAR_MIN_O) = minor
};
};
enum {
CMD_NULL = 0, CMD_WCFG, CMD_MFW, CMD_LFRM, CMD_RCFG, CMD_START,
CMD_RCRC = 7, CMD_AGHIGH, CMD_GRESTORE = 10, CMD_SHUTDOWN,
CMD_DESYNC = 13, CMD_IPROG
};
#define MAX_HEADER_STR_LEN 128
#define MAX_REG_ACTIONS 256
#define BRAM_DATA_START (4*505*130)
#define BRAM_DATA_LEN (4*144*130)
struct fpga_config
{
char header_str[4][MAX_HEADER_STR_LEN];
int num_regs;
struct fpga_config_reg_rw reg[MAX_REG_ACTIONS];
// indices into reg (initialized to -1)
int num_regs_before_bits;
int idcode_reg;
int FLR_reg;
int bits_len;
uint8_t* bits;
int bram_off;
int IOB_off;
};
int read_bitfile(struct fpga_config* cfg, FILE* f);
int extract_model(struct fpga_config* cfg, struct fpga_model* model);
#define DUMP_HEADER_STR 0x0001
#define DUMP_REGS 0x0002
#define DUMP_BITS 0x0004
int dump_config(struct fpga_config* cfg, int flags);
void free_config(struct fpga_config* cfg);
int read_bits(struct fpga_model* model, FILE* f);
int write_bits(FILE* f, struct fpga_model* model);

10
control.c
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@ -269,14 +269,14 @@ int fpga_conn_dest(struct fpga_model* model, int y, int x,
int i, rc, connpt_i, num_dests, conn_point_dests_o;
rc = strarray_find(&model->str, name, &connpt_i);
if (rc) FAIL();
if (rc) FAIL(rc);
tile = YX_TILE(model, y, x);
for (i = 0; i < tile->num_conn_point_names; i++) {
if (tile->conn_point_names[i*2+1] == connpt_i)
break;
}
if (i >= tile->num_conn_point_names)
FAIL();
if (i >= tile->num_conn_point_names)
FAIL(EINVAL);
conn_point_dests_o = tile->conn_point_names[i*2];
if (i < tile->num_conn_point_names-1)
@ -330,7 +330,7 @@ int fpga_switch_dest(struct fpga_model* model, int y, int x,
int rc, i, connpt_o, from_name_i, dest_idx_counter;
rc = strarray_find(&model->str, name, &from_name_i);
if (rc) FAIL();
if (rc) FAIL(rc);
// counts how many switches from the same source (name)
// we have already encountered - to find the dest_idx'th
@ -347,7 +347,7 @@ int fpga_switch_dest(struct fpga_model* model, int y, int x,
}
if (i >= tile->num_switches)
return NO_SWITCH;
if (dest_idx_counter > dest_idx) FAIL();
if (dest_idx_counter > dest_idx) FAIL(EINVAL);
return i;
fail:
return NO_SWITCH;

61
helper.c
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@ -7,21 +7,6 @@
#include "helper.h"
void printf_help(void)
{
printf("\n"
"bit2txt %s - convert FPGA bitstream to text\n"
"Public domain work by Wolfgang Spraul\n"
"\n"
"bit2txt [options] <path to .bit file>\n"
" --help print help message\n"
" --version print version number\n"
" --info add extra info to output (marked #I)\n"
" <path to .bit file> bitstream to print on stdout\n"
" (proposing extension .b2t)\n"
"\n", PROGRAM_REVISION);
}
const char* bitstr(uint32_t value, int digits)
{
static char str[2 /* "0b" */ + 32 + 1 /* '\0' */];
@ -103,52 +88,6 @@ void atom_remove(char* bits, const cfg_atom_t* atom)
}
}
int printf_header(uint8_t* d, int len, int inpos, int* outdelta, int dry_run)
{
int i, str_len;
*outdelta = 0;
if (inpos + 13 > len) {
fprintf(stderr, "#E File size %i below minimum of 13 bytes.\n",
len);
return -1;
}
if (!dry_run) {
printf("hex");
for (i = 0; i < 13; i++)
printf(" %.02x", d[inpos+*outdelta+i]);
printf("\n");
}
*outdelta += 13;
// 4 strings 'a' - 'd', 16-bit length
for (i = 'a'; i <= 'd'; i++) {
if (inpos + *outdelta + 3 > len) {
fprintf(stderr, "#E Unexpected EOF at %i.\n", len);
return -1;
}
if (d[inpos + *outdelta] != i) {
fprintf(stderr, "#E Expected string code '%c', got "
"'%c'.\n", i, d[inpos + *outdelta]);
return -1;
}
str_len = __be16_to_cpu(*(uint16_t*)&d[inpos + *outdelta + 1]);
if (inpos + *outdelta + 3 + str_len > len) {
fprintf(stderr, "#E Unexpected EOF at %i.\n", len);
return -1;
}
if (d[inpos + *outdelta + 3 + str_len - 1]) {
fprintf(stderr, "#E z-terminated string ends with %0xh"
".\n", d[inpos + *outdelta + 3 + str_len - 1]);
return -1;
}
if (!dry_run)
printf("header_str_%c %s\n", i, &d[inpos + *outdelta + 3]);
*outdelta += 3 + str_len;
}
return 0;
}
// for an equivalent schematic, see lut.svg
const int lut_base_vars[6] = {0 /* A1 */, 1, 0 /* A3 - not used */,
0, 0, 1 /* A6 */};

6
helper.h
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@ -22,11 +22,9 @@
"Internal error in %s:%i\n", __FILE__, __LINE__); exit(1); }
#define HERE() fprintf(stderr, "%s:%i\n", __FILE__, __LINE__)
#define FAIL() do { HERE(); goto fail; } while (0)
#define FAIL(code) do { HERE(); rc = (code); goto fail; } while (0)
#define XOUT() do { HERE(); goto xout; } while (0)
void printf_help(void);
const char* bitstr(uint32_t value, int digits);
void hexdump(int indent, const uint8_t* data, int len);
@ -56,8 +54,6 @@ typedef struct _cfg_atom
int atom_found(char* bits, const cfg_atom_t* atom);
void atom_remove(char* bits, const cfg_atom_t* atom);
int printf_header(uint8_t* d, int len, int inpos, int* outdelta, int dry_run);
void printf_lut6(const char* cfg);
// bits is tested only for 32 and 64
const char* lut2bool(const uint64_t lut, int bits,

1
model.h
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@ -10,6 +10,7 @@
#include <stdlib.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <sys/stat.h>
#include "helper.h"

24
model_devices.c
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@ -52,45 +52,43 @@ static int init_iob(struct fpga_model* model, int y, int x,
prefix = "LIOB";
else if (x == model->x_width - RIGHT_OUTER_O)
prefix = "RIOB";
else {
rc = -1;
FAIL();
}
else
FAIL(EINVAL);
snprintf(tile->devs[idx].iob.pinw_in_O,
sizeof(tile->devs[idx].iob.pinw_in_O),
"%s_O%i_PINW", prefix, type_idx);
rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_in_O);
if (rc) FAIL();
if (rc) FAIL(rc);
snprintf(tile->devs[idx].iob.pinw_in_T,
sizeof(tile->devs[idx].iob.pinw_in_T),
"%s_T%i_PINW", prefix, type_idx);
rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_in_T);
if (rc) FAIL();
if (rc) FAIL(rc);
snprintf(tile->devs[idx].iob.pinw_out_I,
sizeof(tile->devs[idx].iob.pinw_out_I),
"%s_IBUF%i_PINW", prefix, type_idx);
rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_out_I);
if (rc) FAIL();
if (rc) FAIL(rc);
snprintf(tile->devs[idx].iob.pinw_out_PADOUT,
sizeof(tile->devs[idx].iob.pinw_out_PADOUT),
"%s_PADOUT%i", prefix, type_idx);
rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_out_PADOUT);
if (rc) FAIL();
if (rc) FAIL(rc);
snprintf(tile->devs[idx].iob.pinw_in_DIFFI_IN,
sizeof(tile->devs[idx].iob.pinw_in_DIFFI_IN),
"%s_DIFFI_IN%i", prefix, type_idx);
rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_in_DIFFI_IN);
if (rc) FAIL();
if (rc) FAIL(rc);
snprintf(tile->devs[idx].iob.pinw_in_DIFFO_IN,
sizeof(tile->devs[idx].iob.pinw_in_DIFFO_IN),
"%s_DIFFO_IN%i", prefix, type_idx);
rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_in_DIFFO_IN);
if (rc) FAIL();
if (rc) FAIL(rc);
snprintf(tile->devs[idx].iob.pinw_out_DIFFO_OUT,
sizeof(tile->devs[idx].iob.pinw_out_DIFFO_OUT),
"%s_DIFFO_OUT%i", prefix, type_idx);
rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_out_DIFFO_OUT);
if (rc) FAIL();
if (rc) FAIL(rc);
if (!x && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 1)
strcpy(tile->devs[idx].iob.pinw_out_PCI_RDY, "LIOB_TOP_PCI_RDY0");
@ -106,7 +104,7 @@ static int init_iob(struct fpga_model* model, int y, int x,
"%s_PCI_RDY%i", prefix, type_idx);
}
rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_out_PCI_RDY);
if (rc) FAIL();
if (rc) FAIL(rc);
return 0;
fail:
return rc;
@ -137,7 +135,7 @@ static int add_dev(struct fpga_model* model,
tile->devs[new_dev_i].type = type;
if (type == DEV_IOB) {
rc = init_iob(model, y, x, new_dev_i, subtype);
if (rc) FAIL();
if (rc) FAIL(rc);
} else if (type == DEV_LOGIC)
tile->devs[new_dev_i].logic.subtype = subtype;
return 0;