minor pieces here and there, a little lost right now...
This commit is contained in:
Wolfgang Spraul
parent
b25f9daa4a
commit
0c08f07fee
75
autotest.c
75
autotest.c
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@ -1681,6 +1681,57 @@ fail:
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return rc;
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}
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static int test_bufg_config(struct test_state* tstate)
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{
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int dev_y, dev_x, dev_tidx, i, rc;
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tstate->diff_to_null = 1;
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// todo: not implemented
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return 0;
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i = 0;
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while (1) {
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rc = fdev_enum(tstate->model, DEV_BUFGMUX, i++,
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&dev_y, &dev_x, &dev_tidx);
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if (rc) FAIL(EINVAL);
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if (dev_y == -1) break;
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rc = fdev_bufgmux(tstate->model, dev_y, dev_x, dev_tidx,
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BUFG_CLK_ASYNC, BUFG_DISATTR_LOW, BUFG_SINV_Y);
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if (rc) FAIL(rc);
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// stub nets for required pins? s-pin?
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if ((rc = diff_printf(tstate))) FAIL(rc);
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fdev_delete(tstate->model, dev_y, dev_x, DEV_BUFGMUX, dev_tidx);
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}
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return 0;
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fail:
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return rc;
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}
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static int test_bufio_config(struct test_state* tstate)
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{
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// todo: not implemented
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return 0;
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}
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static int test_pll_config(struct test_state* tstate)
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{
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// todo: not implemented
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return 0;
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}
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static int test_dcm_config(struct test_state* tstate)
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{
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// todo: not implemented
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return 0;
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}
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static int test_bscan_config(struct test_state* tstate)
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{
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// todo: not implemented
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return 0;
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}
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#define DEFAULT_DIFF_EXEC "./autotest_diff.sh"
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static void printf_help(const char* argv_0, const char** available_tests)
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@ -1711,7 +1762,9 @@ int main(int argc, char** argv)
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char param[1024], cmdline_test[1024];
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int i, param_skip, rc;
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const char* available_tests[] =
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{ "logic_cfg", "routing_sw", "io_sw", "iob_cfg", "lut_encoding", 0 };
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{ "logic_cfg", "routing_sw", "io_sw", "iob_cfg",
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"lut_encoding", "bufg_cfg", "bufio_cfg", "pll_cfg",
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"dcm_cfg", "bscan_cfg", 0 };
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// flush after every line is better for the autotest
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// output, tee, etc.
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@ -1840,6 +1893,26 @@ int main(int argc, char** argv)
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rc = test_lut_encoding(&tstate);
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if (rc) FAIL(rc);
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}
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if (!strcmp(cmdline_test, "bufg_cfg")) {
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rc = test_bufg_config(&tstate);
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if (rc) FAIL(rc);
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}
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if (!strcmp(cmdline_test, "bufio_cfg")) {
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rc = test_bufio_config(&tstate);
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if (rc) FAIL(rc);
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}
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if (!strcmp(cmdline_test, "pll_cfg")) {
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rc = test_pll_config(&tstate);
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if (rc) FAIL(rc);
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}
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if (!strcmp(cmdline_test, "dcm_cfg")) {
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rc = test_dcm_config(&tstate);
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if (rc) FAIL(rc);
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}
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if (!strcmp(cmdline_test, "bscan_cfg")) {
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rc = test_bscan_config(&tstate);
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if (rc) FAIL(rc);
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}
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printf("\n");
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printf("O Test completed.\n");
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111
libs/control.c
111
libs/control.c
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@ -200,6 +200,97 @@ const char* fpga_iob_sitename(struct fpga_model* model, int y, int x,
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return 0;
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}
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static void enum_x(struct fpga_model *model, enum fpgadev_type type,
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int enum_i, int *y, int x, int *type_idx)
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{
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int type_count, i, _y;
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struct fpga_tile* tile;
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type_count = 0;
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for (_y = 0; _y < model->y_height; _y++) {
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tile = YX_TILE(model, _y, x);
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for (i = 0; i < tile->num_devs; i++) {
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if (tile->devs[i].type != type)
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continue;
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if (type_count == enum_i) {
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*y = _y;
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*type_idx = type_count;
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return;
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}
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type_count++;
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}
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}
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*y = -1;
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}
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int fdev_enum(struct fpga_model* model, enum fpgadev_type type, int enum_i,
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int *y, int *x, int *type_idx)
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{
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struct fpga_tile* tile;
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int i, j, type_count, rc;
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CHECK_RC(model);
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switch (type) {
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case DEV_BUFGMUX:
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tile = YX_TILE(model, model->center_y, model->center_x);
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if (!tile) FAIL(EINVAL);
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type_count = 0;
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for (i = 0; i < tile->num_devs; i++) {
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if (tile->devs[i].type != DEV_BUFGMUX)
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continue;
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if (type_count == enum_i) {
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*y = model->center_y;
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*x = model->center_x;
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*type_idx = type_count;
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return 0;
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}
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type_count++;
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}
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*y = -1;
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return 0;
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case DEV_BUFIO: {
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int yx_pairs[] = {
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TOP_OUTER_ROW, model->center_x-CENTER_CMTPLL_O,
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model->center_y, LEFT_OUTER_COL,
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model->center_y, model->x_width-RIGHT_OUTER_O,
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model->y_height-BOT_OUTER_ROW, model->center_x-CENTER_CMTPLL_O };
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type_count = 0;
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for (i = 0; i < sizeof(yx_pairs)/sizeof(*yx_pairs)/2; i++) {
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tile = YX_TILE(model, yx_pairs[i*2], yx_pairs[i*2+1]);
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for (j = 0; j < tile->num_devs; j++) {
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if (tile->devs[j].type != DEV_BUFIO)
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continue;
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if (type_count == enum_i) {
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*y = yx_pairs[i*2];
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*x = yx_pairs[i*2+1];
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*type_idx = type_count;
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return 0;
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}
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type_count++;
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}
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}
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*y = -1;
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return 0;
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}
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case DEV_PLL:
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case DEV_DCM:
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enum_x(model, type, enum_i, y, model->center_x
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- CENTER_CMTPLL_O, type_idx);
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return 0;
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case DEV_BSCAN:
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enum_x(model, type, enum_i, y, model->x_width
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- RIGHT_IO_DEVS_O, type_idx);
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return 0;
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default: break;
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}
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HERE();
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*y = -1;
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return 0;
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fail:
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return rc;
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}
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static const char* dev_str[] = FPGA_DEV_STR;
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const char* fdev_type2str(enum fpgadev_type type)
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@ -852,6 +943,26 @@ fail:
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return rc;
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}
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int fdev_bufgmux(struct fpga_model* model, int y, int x,
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int type_idx, int clk, int disable_attr, int s_inv)
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{
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struct fpga_device* dev;
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int rc;
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dev = fdev_p(model, y, x, DEV_BUFGMUX, type_idx);
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if (!dev) FAIL(EINVAL);
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rc = reset_required_pins(dev);
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if (rc) FAIL(rc);
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dev->u.bufgmux.clk = clk;
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dev->u.bufgmux.disable_attr = disable_attr;
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dev->u.bufgmux.s_inv = s_inv;
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dev->instantiated = 1;
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return 0;
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fail:
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return rc;
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}
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static void scan_lut_digits(const char* s, int* digits)
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{
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int i;
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@ -18,13 +18,17 @@ const char* fpga_iob_sitename(struct fpga_model* model, int y, int x,
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// 2. The index of the device within devices of the same type in the tile.
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//
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// If index is past the last device of that type,
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// y is returned as -1.
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int fdev_enum(struct fpga_model* model, enum fpgadev_type type, int enum_i,
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int *y, int *x, int *type_idx);
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const char* fdev_type2str(enum fpgadev_type type);
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enum fpgadev_type fdev_str2type(const char* str, int len);
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// returns 0 if device not found
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struct fpga_device* fdev_p(struct fpga_model* model,
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int y, int x, enum fpgadev_type type, dev_type_idx_t type_idx);
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// Looks up a device index based on the type index.
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// returns NO_DEV (-1) if not found
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dev_idx_t fpga_dev_idx(struct fpga_model* model,
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@ -94,6 +98,9 @@ int fdev_iob_slew(struct fpga_model* model, int y, int x,
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int fdev_iob_drive(struct fpga_model* model, int y, int x,
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int type_idx, int drive_strength);
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int fdev_bufgmux(struct fpga_model* model, int y, int x,
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int type_idx, int clk, int disable_attr, int s_inv);
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int fdev_set_required_pins(struct fpga_model* model, int y, int x, int type,
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int type_idx);
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void fdev_print_required_pins(struct fpga_model* model, int y, int x,
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294
libs/floorplan.c
294
libs/floorplan.c
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@ -184,8 +184,8 @@ static int printf_IOB(FILE* f, struct fpga_model* model,
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return 0;
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}
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static int read_IOB_attr(struct fpga_model* model, struct fpga_device* dev,
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const char* w1, int w1_len, const char* w2, int w2_len)
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static int read_IOB_attr(struct fpga_model *model, struct fpga_device *dev,
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const char *w1, int w1_len, const char *w2, int w2_len)
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{
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// First the one-word attributes.
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if (!str_cmp(w1, w1_len, "O_used", ZTERM)) {
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@ -283,7 +283,7 @@ inst_1:
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dev->instantiated = 1;
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return 1;
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inst_2:
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dev->instantiated = 2;
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dev->instantiated = 1;
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return 2;
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}
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@ -655,6 +655,237 @@ inst_2:
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return 2;
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}
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static int printf_BUFGMUX(FILE* f, struct fpga_model* model,
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int y, int x, int config_only)
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{
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struct fpga_tile *tile;
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struct fpgadev_bufgmux *cfg;
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char pref[256];
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int type_count, i, rc;
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tile = YX_TILE(model, y, x);
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type_count = 0;
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for (i = 0; i < tile->num_devs; i++) {
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if (tile->devs[i].type != DEV_BUFGMUX)
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continue;
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if (config_only && !(tile->devs[i].instantiated)) {
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type_count++;
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continue;
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}
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snprintf(pref, sizeof(pref), "dev y%02i x%02i BUFGMUX %i",
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y, x, type_count++);
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if (!config_only)
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fprintf(f, "%s\n", pref);
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cfg = &tile->devs[i].u.bufgmux;
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switch (cfg->clk) {
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case BUFG_CLK_ASYNC:
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fprintf(f, "%s clk ASYNC\n", pref);
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break;
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case BUFG_CLK_SYNC:
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fprintf(f, "%s clk SYNC\n", pref);
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break;
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case 0: break; default: FAIL(EINVAL);
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}
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switch (cfg->disable_attr) {
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case BUFG_DISATTR_LOW:
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fprintf(f, "%s disable_attr LOW\n", pref);
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break;
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case BUFG_DISATTR_HIGH:
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fprintf(f, "%s disable_attr HIGH\n", pref);
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break;
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case 0: break; default: FAIL(EINVAL);
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}
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switch (cfg->s_inv) {
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case BUFG_SINV_N:
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fprintf(f, "%s s_inv NO\n", pref);
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break;
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case BUFG_SINV_Y:
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fprintf(f, "%s s_inv YES\n", pref);
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break;
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case 0: break; default: FAIL(EINVAL);
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}
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}
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return 0;
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fail:
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return rc;
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}
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static int read_BUFGMUX_attr(struct fpga_model *model, struct fpga_device *dev,
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const char *w1, int w1_len, const char *w2, int w2_len)
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{
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// BUFGMUX only has 2-word attributes
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if (w2_len < 1) return 0;
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if (!str_cmp(w1, w1_len, "clk", ZTERM)) {
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if (!str_cmp(w2, w2_len, "ASYNC", ZTERM))
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dev->u.bufgmux.clk = BUFG_CLK_ASYNC;
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else if (!str_cmp(w2, w2_len, "SYNC", ZTERM))
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dev->u.bufgmux.clk = BUFG_CLK_SYNC;
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else return 0;
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goto inst;
|
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}
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if (!str_cmp(w1, w1_len, "disable_attr", ZTERM)) {
|
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if (!str_cmp(w2, w2_len, "LOW", ZTERM))
|
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dev->u.bufgmux.disable_attr = BUFG_DISATTR_LOW;
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else if (!str_cmp(w2, w2_len, "HIGH", ZTERM))
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dev->u.bufgmux.disable_attr = BUFG_DISATTR_HIGH;
|
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else return 0;
|
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goto inst;
|
||||
}
|
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if (!str_cmp(w1, w1_len, "s_inv", ZTERM)) {
|
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if (!str_cmp(w2, w2_len, "NO", ZTERM))
|
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dev->u.bufgmux.s_inv = BUFG_SINV_N;
|
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else if (!str_cmp(w2, w2_len, "YES", ZTERM))
|
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dev->u.bufgmux.s_inv = BUFG_SINV_Y;
|
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else return 0;
|
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goto inst;
|
||||
}
|
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return 0;
|
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inst:
|
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dev->instantiated = 1;
|
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return 2;
|
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}
|
||||
|
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static int printf_BUFIO(FILE* f, struct fpga_model* model,
|
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int y, int x, int config_only)
|
||||
{
|
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struct fpga_tile *tile;
|
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struct fpgadev_bufio *cfg;
|
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char pref[256];
|
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int type_count, i, rc;
|
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|
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tile = YX_TILE(model, y, x);
|
||||
type_count = 0;
|
||||
for (i = 0; i < tile->num_devs; i++) {
|
||||
if (tile->devs[i].type != DEV_BUFIO)
|
||||
continue;
|
||||
if (config_only && !(tile->devs[i].instantiated)) {
|
||||
type_count++;
|
||||
continue;
|
||||
}
|
||||
snprintf(pref, sizeof(pref), "dev y%02i x%02i BUFGMUX %i",
|
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y, x, type_count++);
|
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if (!config_only)
|
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fprintf(f, "%s\n", pref);
|
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cfg = &tile->devs[i].u.bufio;
|
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if (cfg->divide)
|
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fprintf(f, "%s divide %i\n", pref, cfg->divide);
|
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switch (cfg->divide_bypass) {
|
||||
case BUFIO_DIVIDEBP_N:
|
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fprintf(f, "%s divide_bypass NO\n", pref);
|
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break;
|
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case BUFIO_DIVIDEBP_Y:
|
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fprintf(f, "%s divide_bypass YES\n", pref);
|
||||
break;
|
||||
case 0: break; default: FAIL(EINVAL);
|
||||
}
|
||||
switch (cfg->i_inv) {
|
||||
case BUFIO_IINV_N:
|
||||
fprintf(f, "%s i_inv NO\n", pref);
|
||||
break;
|
||||
case BUFIO_IINV_Y:
|
||||
fprintf(f, "%s i_inv YES\n", pref);
|
||||
break;
|
||||
case 0: break; default: FAIL(EINVAL);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
fail:
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int read_BUFIO_attr(struct fpga_model *model, struct fpga_device *dev,
|
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const char *w1, int w1_len, const char *w2, int w2_len)
|
||||
{
|
||||
// BUFIO only has 2-word attributes
|
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if (w2_len < 1) return 0;
|
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if (!str_cmp(w1, w1_len, "divide", ZTERM)) {
|
||||
dev->u.bufio.divide = to_i(w2, w2_len);
|
||||
goto inst;
|
||||
}
|
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if (!str_cmp(w1, w1_len, "divide_bypass", ZTERM)) {
|
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if (!str_cmp(w2, w2_len, "NO", ZTERM))
|
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dev->u.bufio.divide_bypass = BUFIO_DIVIDEBP_N;
|
||||
else if (!str_cmp(w2, w2_len, "YES", ZTERM))
|
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dev->u.bufio.divide_bypass = BUFIO_DIVIDEBP_Y;
|
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else return 0;
|
||||
goto inst;
|
||||
}
|
||||
if (!str_cmp(w1, w1_len, "i_inv", ZTERM)) {
|
||||
if (!str_cmp(w2, w2_len, "NO", ZTERM))
|
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dev->u.bufio.i_inv = BUFIO_IINV_N;
|
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else if (!str_cmp(w2, w2_len, "YES", ZTERM))
|
||||
dev->u.bufio.i_inv = BUFIO_IINV_Y;
|
||||
else return 0;
|
||||
goto inst;
|
||||
}
|
||||
return 0;
|
||||
inst:
|
||||
dev->instantiated = 1;
|
||||
return 2;
|
||||
}
|
||||
|
||||
static int printf_BSCAN(FILE* f, struct fpga_model* model,
|
||||
int y, int x, int config_only)
|
||||
{
|
||||
struct fpga_tile *tile;
|
||||
struct fpgadev_bscan *cfg;
|
||||
char pref[256];
|
||||
int type_count, i, rc;
|
||||
|
||||
tile = YX_TILE(model, y, x);
|
||||
type_count = 0;
|
||||
for (i = 0; i < tile->num_devs; i++) {
|
||||
if (tile->devs[i].type != DEV_BSCAN)
|
||||
continue;
|
||||
if (config_only && !(tile->devs[i].instantiated)) {
|
||||
type_count++;
|
||||
continue;
|
||||
}
|
||||
snprintf(pref, sizeof(pref), "dev y%02i x%02i BUFGMUX %i",
|
||||
y, x, type_count++);
|
||||
if (!config_only)
|
||||
fprintf(f, "%s\n", pref);
|
||||
cfg = &tile->devs[i].u.bscan;
|
||||
if (cfg->jtag_chain)
|
||||
fprintf(f, "%s jtag_chain %i\n", pref, cfg->jtag_chain);
|
||||
switch (cfg->jtag_test) {
|
||||
case BSCAN_JTAG_TEST_N:
|
||||
fprintf(f, "%s jtag_test NO\n", pref);
|
||||
break;
|
||||
case BSCAN_JTAG_TEST_Y:
|
||||
fprintf(f, "%s jtag_test YES\n", pref);
|
||||
break;
|
||||
case 0: break; default: FAIL(EINVAL);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
fail:
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int read_BSCAN_attr(struct fpga_model *model, struct fpga_device *dev,
|
||||
const char *w1, int w1_len, const char *w2, int w2_len)
|
||||
{
|
||||
// BSCAN only has 2-word attributes
|
||||
if (w2_len < 1) return 0;
|
||||
if (!str_cmp(w1, w1_len, "jtag_chain", ZTERM)) {
|
||||
dev->u.bscan.jtag_chain = to_i(w2, w2_len);
|
||||
goto inst;
|
||||
}
|
||||
if (!str_cmp(w1, w1_len, "jtag_test", ZTERM)) {
|
||||
if (!str_cmp(w2, w2_len, "NO", ZTERM))
|
||||
dev->u.bscan.jtag_test = BSCAN_JTAG_TEST_N;
|
||||
else if (!str_cmp(w2, w2_len, "YES", ZTERM))
|
||||
dev->u.bscan.jtag_test = BSCAN_JTAG_TEST_Y;
|
||||
else return 0;
|
||||
goto inst;
|
||||
}
|
||||
return 0;
|
||||
inst:
|
||||
dev->instantiated = 1;
|
||||
return 2;
|
||||
}
|
||||
|
||||
int printf_devices(FILE* f, struct fpga_model* model, int config_only)
|
||||
{
|
||||
int x, y, i, rc;
|
||||
|
|
@ -672,6 +903,24 @@ int printf_devices(FILE* f, struct fpga_model* model, int config_only)
|
|||
if (rc) goto fail;
|
||||
}
|
||||
}
|
||||
for (x = 0; x < model->x_width; x++) {
|
||||
for (y = 0; y < model->y_height; y++) {
|
||||
rc = printf_BUFGMUX(f, model, y, x, config_only);
|
||||
if (rc) goto fail;
|
||||
}
|
||||
}
|
||||
for (x = 0; x < model->x_width; x++) {
|
||||
for (y = 0; y < model->y_height; y++) {
|
||||
rc = printf_BUFIO(f, model, y, x, config_only);
|
||||
if (rc) goto fail;
|
||||
}
|
||||
}
|
||||
for (x = 0; x < model->x_width; x++) {
|
||||
for (y = 0; y < model->y_height; y++) {
|
||||
rc = printf_BSCAN(f, model, y, x, config_only);
|
||||
if (rc) goto fail;
|
||||
}
|
||||
}
|
||||
for (x = 0; x < model->x_width; x++) {
|
||||
for (y = 0; y < model->y_height; y++) {
|
||||
tile = YX_TILE(model, y, x);
|
||||
|
|
@ -679,7 +928,10 @@ int printf_devices(FILE* f, struct fpga_model* model, int config_only)
|
|||
if (config_only && !(tile->devs[i].instantiated))
|
||||
continue;
|
||||
if (tile->devs[i].type == DEV_LOGIC
|
||||
|| tile->devs[i].type == DEV_IOB)
|
||||
|| tile->devs[i].type == DEV_IOB
|
||||
|| tile->devs[i].type == DEV_BUFGMUX
|
||||
|| tile->devs[i].type == DEV_BUFIO
|
||||
|| tile->devs[i].type == DEV_BSCAN)
|
||||
continue; // handled earlier
|
||||
fprintf(f, "dev y%02i x%02i %s\n", y, x,
|
||||
fdev_type2str(tile->devs[i].type));
|
||||
|
|
@ -825,13 +1077,6 @@ fail:
|
|||
return rc;
|
||||
}
|
||||
|
||||
static enum fpgadev_type to_type(const char* s, int len)
|
||||
{
|
||||
if (!str_cmp(s, len, "IOB", 3)) return DEV_IOB;
|
||||
if (!str_cmp(s, len, "LOGIC", 5)) return DEV_LOGIC;
|
||||
return DEV_NONE;
|
||||
}
|
||||
|
||||
static int coord(const char* s, int start, int* end, int* y, int* x)
|
||||
{
|
||||
int y_beg, y_end, x_beg, x_end, rc;
|
||||
|
|
@ -986,14 +1231,17 @@ static void read_dev_line(struct fpga_model* model, const char* line, int start)
|
|||
|
||||
if (type_end == type_beg || idx_end == idx_beg
|
||||
|| !all_digits(&line[idx_beg], idx_end-idx_beg)) {
|
||||
fprintf(stderr, "error %i: %s", __LINE__, line);
|
||||
HERE();
|
||||
return;
|
||||
}
|
||||
dev_type = to_type(&line[type_beg], type_end-type_beg);
|
||||
dev_type = fdev_str2type(&line[type_beg], type_end-type_beg);
|
||||
dev_type_idx = to_i(&line[idx_beg], idx_end-idx_beg);
|
||||
dev_idx = fpga_dev_idx(model, y_coord, x_coord, dev_type, dev_type_idx);
|
||||
if (dev_idx == NO_DEV) {
|
||||
fprintf(stderr, "error %i: %s", __LINE__, line);
|
||||
fprintf(stderr, "%s:%i y%02i x%02i dev_type %i "
|
||||
"dev_type_idx %i dev_idx %i\n",
|
||||
__FILE__, __LINE__, y_coord, x_coord, dev_type,
|
||||
dev_type_idx, dev_idx);
|
||||
return;
|
||||
}
|
||||
dev_ptr = FPGA_DEV(model, y_coord, x_coord, dev_idx);
|
||||
|
|
@ -1016,6 +1264,24 @@ static void read_dev_line(struct fpga_model* model, const char* line, int start)
|
|||
&line[second_beg],
|
||||
second_end-second_beg);
|
||||
break;
|
||||
case DEV_BUFGMUX:
|
||||
words_consumed = read_BUFGMUX_attr(model, dev_ptr,
|
||||
&line[next_beg], next_end-next_beg,
|
||||
&line[second_beg],
|
||||
second_end-second_beg);
|
||||
break;
|
||||
case DEV_BUFIO:
|
||||
words_consumed = read_BUFIO_attr(model, dev_ptr,
|
||||
&line[next_beg], next_end-next_beg,
|
||||
&line[second_beg],
|
||||
second_end-second_beg);
|
||||
break;
|
||||
case DEV_BSCAN:
|
||||
words_consumed = read_BSCAN_attr(model, dev_ptr,
|
||||
&line[next_beg], next_end-next_beg,
|
||||
&line[second_beg],
|
||||
second_end-second_beg);
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "error %i: %s", __LINE__, line);
|
||||
return;
|
||||
|
|
|
|||
48
libs/model.h
48
libs/model.h
|
|
@ -343,7 +343,7 @@ typedef int dev_type_idx_t;
|
|||
#define FPGA_DEV(model, y, x, dev_idx) (&YX_TILE(model, y, x)->devs[dev_idx])
|
||||
|
||||
//
|
||||
// logic device
|
||||
// DEV_LOGIC
|
||||
//
|
||||
|
||||
// M and L device is always at type index 0, X device
|
||||
|
|
@ -444,7 +444,7 @@ struct fpgadev_logic
|
|||
};
|
||||
|
||||
//
|
||||
// iob device
|
||||
// DEV_IOB
|
||||
//
|
||||
|
||||
enum { IOBM = 1, IOBS };
|
||||
|
|
@ -493,6 +493,47 @@ struct fpgadev_iob
|
|||
int out_term;
|
||||
};
|
||||
|
||||
//
|
||||
// DEV_BUFGMUX
|
||||
//
|
||||
|
||||
enum { BUFG_CLK_ASYNC = 1, BUFG_CLK_SYNC };
|
||||
enum { BUFG_DISATTR_LOW = 1, BUFG_DISATTR_HIGH };
|
||||
enum { BUFG_SINV_N = 1, BUFG_SINV_Y };
|
||||
|
||||
struct fpgadev_bufgmux
|
||||
{
|
||||
int clk;
|
||||
int disable_attr;
|
||||
int s_inv;
|
||||
};
|
||||
|
||||
//
|
||||
// DEV_BUFIO
|
||||
//
|
||||
|
||||
enum { BUFIO_DIVIDEBP_N = 1, BUFIO_DIVIDEBP_Y };
|
||||
enum { BUFIO_IINV_N = 1, BUFIO_IINV_Y };
|
||||
|
||||
struct fpgadev_bufio
|
||||
{
|
||||
int divide;
|
||||
int divide_bypass;
|
||||
int i_inv;
|
||||
};
|
||||
|
||||
//
|
||||
// DEV_BSCAN
|
||||
//
|
||||
|
||||
enum { BSCAN_JTAG_TEST_N = 1, BSCAN_JTAG_TEST_Y };
|
||||
|
||||
struct fpgadev_bscan
|
||||
{
|
||||
int jtag_chain; // 1-4
|
||||
int jtag_test;
|
||||
};
|
||||
|
||||
//
|
||||
// fpga_device
|
||||
//
|
||||
|
|
@ -526,6 +567,9 @@ struct fpga_device
|
|||
union {
|
||||
struct fpgadev_logic logic;
|
||||
struct fpgadev_iob iob;
|
||||
struct fpgadev_bufgmux bufgmux;
|
||||
struct fpgadev_bufio bufio;
|
||||
struct fpgadev_bscan bscan;
|
||||
} u;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user