finished gclk
This commit is contained in:
Wolfgang Spraul
parent
17857de4d2
commit
0ebac7068f
4
Makefile
4
Makefile
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@ -65,8 +65,8 @@ compare.%: xc6slx9_empty.%
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%.ports: %.fp
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cat $<|awk '{if ($$1=="port") printf "%s %s %s\n",$$2,$$3,$$4}'|sort >$@
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%.sw: %.fp
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cat $<|awk '{if ($$1=="switch") printf "%s %s %s %s %s\n",$$2,$$3,$$4,$$5,$$6}'|sort >$@
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%.sw: %.fp sort_seq merge_seq
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cat $<|awk '{if ($$1=="switch") printf "%s %s %s %s %s\n",$$2,$$3,$$4,$$5,$$6}'|sort|./sort_seq -|./merge_seq -|sort >$@
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clean:
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rm -f bit2txt bit2txt.o \
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208
model.c
208
model.c
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@ -73,8 +73,10 @@ int fpga_build_model(struct fpga_model* model, int fpga_rows, const char* column
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memset(model, 0, sizeof(*model));
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model->cfg_rows = fpga_rows;
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strncpy(model->cfg_columns, columns, sizeof(model->cfg_columns)-1);
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strncpy(model->cfg_left_wiring, left_wiring, sizeof(model->cfg_left_wiring)-1);
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strncpy(model->cfg_right_wiring, right_wiring, sizeof(model->cfg_right_wiring)-1);
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strncpy(model->cfg_left_wiring, left_wiring,
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sizeof(model->cfg_left_wiring)-1);
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strncpy(model->cfg_right_wiring, right_wiring,
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sizeof(model->cfg_right_wiring)-1);
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strarray_init(&model->str, STRIDX_64K);
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rc = init_tiles(model);
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@ -173,9 +175,14 @@ static int run_gclk(struct fpga_model* model)
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fprintf(stderr, "Internal error in line %i\n", __LINE__);
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goto xout;
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}
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gclk_net.pts[next_net_o].start_count = 0;
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gclk_net.pts[next_net_o].x = x;
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if (is_atx(X_ROUTING_COL, model, x)) {
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gclk_net.pts[next_net_o].y = row_top_y+8;
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if (is_atx(X_LEFT_IO_ROUTING_COL|X_FABRIC_ROUTING_COL|X_CENTER_ROUTING_COL, model, x)) {
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gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_INT";
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} else if (is_atx(X_LEFT_MCB, model, x)) {
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gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_MCB";
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} else if (is_atx(X_LOGIC_COL|X_LEFT_IO_DEVS_COL, model, x)) {
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gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_CLB";
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} else if (is_atx(X_FABRIC_BRAM_MACC_ROUTING_COL, model, x)) {
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@ -184,8 +191,29 @@ static int run_gclk(struct fpga_model* model)
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gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_BRAM";
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} else if (is_atx(X_FABRIC_MACC_COL, model, x)) {
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gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_DSP";
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} else if (is_atx(X_CENTER_CMTPLL_COL, model, x)) {
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gclk_net.pts[next_net_o].y = row_top_y+7;
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gclk_net.pts[next_net_o++].name = "HCLK_CMT_GCLK%i_CLB";
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} else if (is_atx(X_CENTER_REGS_COL, model, x)) {
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gclk_net.pts[next_net_o++].name = "CLKV_BUFH_LEFT_L%i";
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// connect left half
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gclk_net.pts[next_net_o].name = "";
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if ((rc = add_conn_net(model, NOPREF_BI_F, &gclk_net))) goto xout;
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// start right half
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gclk_net.pts[0].start_count = 0;
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gclk_net.pts[0].x = x;
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gclk_net.pts[0].y = row_top_y+8;
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gclk_net.pts[0].name = "CLKV_BUFH_RIGHT_R%i";
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next_net_o = 1;
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} else if (is_atx(X_RIGHT_IO_ROUTING_COL, model, x)) {
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gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_INT";
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// connect right half
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gclk_net.pts[next_net_o].name = "";
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if ((rc = add_conn_net(model, NOPREF_BI_F, &gclk_net))) goto xout;
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break;
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}
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if (x >= model->tile_x_range) {
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@ -193,12 +221,6 @@ static int run_gclk(struct fpga_model* model)
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goto xout;
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}
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}
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for (i = 0; i < next_net_o; i++) {
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gclk_net.pts[i].start_count = 0;
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gclk_net.pts[i].y = row_top_y+8;
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}
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gclk_net.pts[next_net_o].name = "";
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if ((rc = add_conn_net(model, NOPREF_BI_F, &gclk_net))) goto xout;
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}
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for (x = 0; x < model->tile_x_range; x++) {
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if (is_atx(X_ROUTING_COL, model, x)) {
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@ -235,7 +257,8 @@ static int run_gclk(struct fpga_model* model)
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gclk_net.pts[7].name = "GCLK%i_BRK";
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if ((rc = add_conn_net(model, NOPREF_BI_F, &gclk_net))) goto xout;
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// connects gclk of each row tile to hclk tile at the middle of the row
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// vertically connects gclk of each row tile to
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// hclk tile at the middle of the row
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for (i = 0; i < 8; i++) {
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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row_top_y+i, x, "GCLK%i", 0, 15,
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@ -244,13 +267,6 @@ static int run_gclk(struct fpga_model* model)
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row_top_y+9+i, x, (i == 7 && is_break) ? "GCLK%i_BRK" : "GCLK%i", 0, 15,
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row_top_y+8, x, "HCLK_GCLK%i", 0))) goto xout;
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}
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if (x < model->center_x) {
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// long connection to CMT at center of chip
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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row_top_y+8, x, "HCLK_GCLK%i_INT", 0, 15,
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row_top_y+7, model->center_x-1, "HCLK_CMT_GCLK%i_CLB", 0))) goto xout;
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}
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}
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}
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}
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@ -535,6 +551,125 @@ static int run_gclk_horiz_regs(struct fpga_model* model)
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}
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}
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}
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// some local nets around the center on the left side
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{ struct w_net net = {
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3,
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{{ "REGL_GCLK%i", 0, model->center_y, LEFT_OUTER_COL },
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{ "REGH_LTERM_GCLK%i", 0, model->center_y, LEFT_INNER_COL },
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{ "REGH_IOI_INT_GCLK%i", 0, model->center_y, LEFT_IO_ROUTING },
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{ "" }}};
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if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
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{
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const char* str[3] = {"REGL_GCLK%i", "REGH_LTERM_GCLK%i", "REGH_IOI_INT_GCLK%i"};
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y-2, LEFT_IO_ROUTING, "INT_BUFPLL_GCLK%i", 2, 3,
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model->center_y-1, LEFT_IO_ROUTING, "INT_BUFPLL_GCLK%i_EXT", 2))) goto xout;
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for (x = LEFT_OUTER_COL; x <= LEFT_IO_ROUTING; x++) {
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y-1, LEFT_IO_ROUTING, "INT_BUFPLL_GCLK%i", 0, 1,
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model->center_y, x, str[x], 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y-1, LEFT_IO_ROUTING, "INT_BUFPLL_GCLK%i_EXT", 2, 3,
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model->center_y, x, str[x], 2))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y-2, LEFT_IO_ROUTING, "INT_BUFPLL_GCLK%i", 2, 3,
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model->center_y, x, str[x], 2))) goto xout;
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}
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}
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// and right side
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{ struct w_net net = {
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3,
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{{ "REGH_RIOI_GCLK%i", 0, model->center_y, model->tile_x_range-RIGHT_IO_DEVS_O },
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{ "MCB_REGH_GCLK%i", 0, model->center_y, model->tile_x_range-RIGHT_MCB_O },
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{ "REGR_GCLK%i", 0, model->center_y, model->tile_x_range-RIGHT_OUTER_O },
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{ "" }}};
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if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
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{
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const char* str[5] = {"REGH_IOI_INT_GCLK%i", "REGH_RIOI_GCLK%i", "MCB_REGH_GCLK%i", "REGR_RTERM_GCLK%i", "REGR_GCLK%i"};
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y-2, model->tile_x_range-RIGHT_IO_ROUTING_O, "INT_BUFPLL_GCLK%i", 2, 3,
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model->center_y-1, model->tile_x_range-RIGHT_IO_ROUTING_O, "INT_BUFPLL_GCLK%i_EXT", 2))) goto xout;
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for (x = model->tile_x_range-RIGHT_IO_ROUTING_O; x <= model->tile_x_range-RIGHT_OUTER_O; x++) {
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y-1, model->tile_x_range-RIGHT_IO_ROUTING_O, "INT_BUFPLL_GCLK%i_EXT", 2, 3,
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model->center_y, x, str[x-(model->tile_x_range-RIGHT_IO_ROUTING_O)], 2))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y-2, model->tile_x_range-RIGHT_IO_ROUTING_O, "INT_BUFPLL_GCLK%i", 2, 3,
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model->center_y, x, str[x-(model->tile_x_range-RIGHT_IO_ROUTING_O)], 2))) goto xout;
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}
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}
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{ struct w_net net = {
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1,
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{{ "INT_BUFPLL_GCLK%i", 0, model->center_y-1, model->tile_x_range-RIGHT_IO_ROUTING_O },
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{ "REGH_RIOI_INT_GCLK%i", 0, model->center_y, model->tile_x_range-RIGHT_IO_ROUTING_O },
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{ "REGH_RIOI_GCLK%i", 0, model->center_y, model->tile_x_range-RIGHT_IO_DEVS_O },
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{ "REGH_RTERM_GCLK%i", 0, model->center_y, model->tile_x_range-RIGHT_INNER_O },
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{ "" }}};
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if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
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{ struct w_net net = {
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1,
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{{ "REGH_IOI_INT_GCLK%i", 2, model->center_y, model->tile_x_range-RIGHT_IO_ROUTING_O },
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{ "REGH_RIOI_GCLK%i", 2, model->center_y, model->tile_x_range-RIGHT_IO_DEVS_O },
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{ "REGR_RTERM_GCLK%i", 2, model->center_y, model->tile_x_range-RIGHT_INNER_O },
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{ "" }}};
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if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
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// the naming is a little messed up here, and the networks are
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// actually simpler than represented here (with full 0:3 connections).
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// But until we have better representation of wire networks, this has
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// to suffice.
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_OUTER_O,
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"REGR_GCLK%i", 0, 1,
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model->center_y-1, model->tile_x_range-RIGHT_IO_ROUTING_O,
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"INT_BUFPLL_GCLK%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_OUTER_O,
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"REGR_GCLK%i", 0, 1,
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model->center_y, model->tile_x_range-RIGHT_IO_ROUTING_O,
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"REGH_RIOI_INT_GCLK%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_OUTER_O,
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"REGR_GCLK%i", 2, 3,
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model->center_y, model->tile_x_range-RIGHT_IO_ROUTING_O,
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"REGH_IOI_INT_GCLK%i", 2))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_OUTER_O,
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"REGR_GCLK%i", 0, 1,
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model->center_y, model->tile_x_range-RIGHT_INNER_O,
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"REGH_RTERM_GCLK%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_OUTER_O,
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"REGR_GCLK%i", 2, 3,
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model->center_y, model->tile_x_range-RIGHT_INNER_O,
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"REGR_RTERM_GCLK%i", 2))) goto xout;
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// same from MCB_REGH_GCLK...
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_MCB_O,
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"MCB_REGH_GCLK%i", 0, 1,
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model->center_y-1, model->tile_x_range-RIGHT_IO_ROUTING_O,
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"INT_BUFPLL_GCLK%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_MCB_O,
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"MCB_REGH_GCLK%i", 0, 1,
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model->center_y, model->tile_x_range-RIGHT_IO_ROUTING_O,
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"REGH_RIOI_INT_GCLK%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_MCB_O,
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"MCB_REGH_GCLK%i", 2, 3,
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model->center_y, model->tile_x_range-RIGHT_IO_ROUTING_O,
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"REGH_IOI_INT_GCLK%i", 2))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_MCB_O,
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"MCB_REGH_GCLK%i", 0, 1,
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model->center_y, model->tile_x_range-RIGHT_INNER_O,
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"REGH_RTERM_GCLK%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->center_y, model->tile_x_range-RIGHT_MCB_O,
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"MCB_REGH_GCLK%i", 2, 3,
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model->center_y, model->tile_x_range-RIGHT_INNER_O,
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"REGR_RTERM_GCLK%i", 2))) goto xout;
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return 0;
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xout:
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return rc;
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@ -594,6 +729,43 @@ static int run_gclk_vert_regs(struct fpga_model* model)
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}
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net.pts[i].name = "";
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if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout;
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// a few local gclk networks at the center top and bottom
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{ struct w_net net = {
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1,
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{{ "REGT_GCLK%i", 0, TOP_OUTER_ROW, model->center_x-1 },
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{ "REGT_TTERM_GCLK%i", 0, TOP_INNER_ROW, model->center_x-1 },
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{ "REGV_TTERM_GCLK%i", 0, TOP_INNER_ROW, model->center_x },
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{ "BUFPLL_TOP_GCLK%i", 0, TOP_INNER_ROW, model->center_x+1 },
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{ "" }}};
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if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
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{ struct w_net net = {
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1,
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{{ "REGB_GCLK%i", 0, model->tile_y_range-1, model->center_x-1 },
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{ "REGB_BTERM_GCLK%i", 0, model->tile_y_range-2, model->center_x-1 },
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{ "REGV_BTERM_GCLK%i", 0, model->tile_y_range-2, model->center_x },
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{ "BUFPLL_BOT_GCLK%i", 0, model->tile_y_range-2, model->center_x+1 },
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{ "" }}};
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if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
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// wire up gclk from tterm down to top 8 rows at center_x+1
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for (i = TOP_IO_TILES; i <= TOP_IO_TILES+HALF_ROW; i++) {
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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TOP_INNER_ROW, model->center_x+1,
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"IOI_TTERM_GCLK%i", 0, 15,
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i, model->center_x+1,
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(i == TOP_IO_TILES+HALF_ROW) ?
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"HCLK_GCLK_UP%i" : "GCLK%i", 0))) goto xout;
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}
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// same at the bottom upwards
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for (i = model->tile_y_range-2-1; i >= model->tile_y_range-2-HALF_ROW-1; i--) {
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if ((rc = add_conn_range(model, NOPREF_BI_F,
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model->tile_y_range-2, model->center_x+1,
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"IOI_BTERM_GCLK%i", 0, 15,
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i, model->center_x+1,
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(i == model->tile_y_range-2-HALF_ROW-1) ?
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"HCLK_GCLK%i" : "GCLK%i", 0))) goto xout;
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}
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return 0;
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xout:
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return rc;
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@ -1800,6 +1972,8 @@ int is_atx(int check, struct fpga_model* model, int x)
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if (check & X_RIGHT_IO_ROUTING_COL && x == model->tile_x_range-5) return 1;
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if (check & X_RIGHT_IO_DEVS_COL && x == model->tile_x_range-4) return 1;
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if (check & X_LEFT_SIDE && x < model->center_x) return 1;
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if (check & X_LEFT_MCB && x == LEFT_MCB_COL) return 1;
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if (check & X_RIGHT_MCB && x == model->tile_x_range-3) return 1;
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return 0;
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}
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26
model.h
26
model.h
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@ -128,11 +128,25 @@ enum fpga_tile_type
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HCLK_IO_BOT_DN_L, HCLK_IO_BOT_DN_R,
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};
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// Some constant to make the core more readable
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#define LEFT_IO_ROUTING 2
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#define LEFT_IO_DEVS 3
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#define TOP_IO_TILES 2
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#define BOTTOM_IO_TILES 2
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// Some constants to make the code more readable
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#define LEFT_OUTER_COL 0
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#define LEFT_INNER_COL 1
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#define LEFT_IO_ROUTING 2
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#define LEFT_IO_DEVS 3
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||||
#define LEFT_MCB_COL 4
|
||||
|
||||
#define TOP_IO_TILES 2
|
||||
#define TOP_OUTER_ROW 0
|
||||
#define TOP_INNER_ROW 1
|
||||
#define BOTTOM_IO_TILES 2
|
||||
#define HALF_ROW 8
|
||||
|
||||
// Offsets on right side are deducted from width
|
||||
#define RIGHT_OUTER_O 1
|
||||
#define RIGHT_INNER_O 2
|
||||
#define RIGHT_MCB_O 3
|
||||
#define RIGHT_IO_DEVS_O 4
|
||||
#define RIGHT_IO_ROUTING_O 5
|
||||
|
||||
// tile flags
|
||||
|
||||
|
|
@ -180,6 +194,8 @@ int is_aty(int check, struct fpga_model* model, int y);
|
|||
#define X_RIGHT_IO_ROUTING_COL 0x00080000
|
||||
#define X_RIGHT_IO_DEVS_COL 0x00100000
|
||||
#define X_LEFT_SIDE 0x00200000 // true for anything left of the center (not including center)
|
||||
#define X_LEFT_MCB 0x00400000
|
||||
#define X_RIGHT_MCB 0x00800000
|
||||
|
||||
// multiple checks are combined with OR logic
|
||||
int is_atx(int check, struct fpga_model* model, int x);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user