more switches
This commit is contained in:
Wolfgang Spraul
parent
d54a0ff81d
commit
1f5d790f09
4
README
4
README
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@ -65,6 +65,10 @@ TODO (as of 2012-08, expected time to delivery: months to years
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* many more cases in model of switches and inter-tile connections
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* write standard design elements for libfpga-stdlib library
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* support lm32 or openrisc core, either via libfpga or iverilog backend
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* several places might benefit from a bison parser:
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- switchbox description into bit parser/generator (bit_frames.c)
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- inter-tile wire connections (model_conns.c)
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- configure devices and route wires
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* ipv6 or vnc in hardware?
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* iverilog fpga backend
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264
bit_frames.c
264
bit_frames.c
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@ -487,6 +487,8 @@ static int mod4_calc(int a, int b)
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struct sw_mip_src
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{
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int minor;
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int m0_sw_to;
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int m0_two_bits_o;
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int m0_two_bits_val;
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@ -510,28 +512,15 @@ struct sw_mi20_src
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int src_wire[6];
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};
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static int construct_extract_state(struct extract_state* es, struct fpga_model* model)
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static int src_to_bitpos(struct extract_state* es, const struct sw_mip_src* src, int src_len)
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{
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char from_str[MAX_WIRENAME_LEN], to_str[MAX_WIRENAME_LEN];
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int i, j, k, l, cur_pair_start, cur_two_bits_o, cur_two_bits_val, rc;
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int logicin_i;
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int i, j, rc;
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memset(es, 0, sizeof(*es));
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es->model = model;
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if (model->first_routing_y == -1)
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FAIL(EINVAL);
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// mip 10
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{ const struct sw_mip_src src[] = {
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{DW + ((W_EL1*4+2) | DIR_BEG), 0, 2, 3, DW + ((W_NR1*4+3) | DIR_BEG), 14, 1, 2,
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{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
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LW + LO_BMUX, LW + LO_DQ, LW + LO_D}}};
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for (i = 0; i < sizeof(src)/sizeof(*src); i++) {
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for (j = 0; j < sizeof(src[0].src_wire)/sizeof(src[0].src_wire[0]); j++) {
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for (i = 0; i < src_len; i++) {
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for (j = 0; j < sizeof(src->src_wire)/sizeof(src->src_wire[0]); j++) {
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if (src[i].src_wire[j] == UNDEF) continue;
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es->bit_pos[es->num_bit_pos].minor = 20;
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es->bit_pos[es->num_bit_pos].minor = src[i].minor;
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es->bit_pos[es->num_bit_pos].two_bits_o = src[i].m0_two_bits_o;
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es->bit_pos[es->num_bit_pos].two_bits_val = src[i].m0_two_bits_val;
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es->bit_pos[es->num_bit_pos].one_bit_o = src[i].m0_one_bit_start + j*2;
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@ -547,8 +536,245 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
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}
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es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
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es->num_bit_pos++;
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es->bit_pos[es->num_bit_pos].minor = src[i].minor;
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es->bit_pos[es->num_bit_pos].two_bits_o = src[i].m1_two_bits_o;
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es->bit_pos[es->num_bit_pos].two_bits_val = src[i].m1_two_bits_val;
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es->bit_pos[es->num_bit_pos].one_bit_o = src[i].m1_one_bit_start + j*2;
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es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
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es->model->first_routing_y, es->model->first_routing_x,
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fpga_wirestr_i(es->model, src[i].src_wire[j]),
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fpga_wirestr_i(es->model, src[i].m1_sw_to));
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if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
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fprintf(stderr, "#E routing switch %s -> %s not in model\n",
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fpga_wirestr(es->model, src[i].src_wire[j]),
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fpga_wirestr(es->model, src[i].m1_sw_to));
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FAIL(EINVAL);
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}
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es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
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es->num_bit_pos++;
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}
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}}
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}
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return 0;
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fail:
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return rc;
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}
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static int wire_decrement(int wire)
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{
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int _wire, flags;
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if (wire >= DW && wire <= DW_LAST) {
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_wire = wire - DW;
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flags = _wire & DIR_FLAGS;
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_wire &= ~DIR_FLAGS;
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if (_wire%4 == 0)
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return DW + ((_wire + 3) | flags);
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return DW + ((_wire - 1) | flags);
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}
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if (wire >= LW && wire <= LW_LAST) {
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_wire = wire - LW;
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flags = _wire & LD1;
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_wire &= ~LD1;
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if (_wire == LO_A)
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return LW + (LO_D|flags);
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if (_wire == LO_AMUX)
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return LW + (LO_DMUX|flags);
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if (_wire == LO_AQ)
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return LW + (LO_DQ|flags);
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if ((_wire >= LO_B && _wire <= LO_D)
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|| (_wire >= LO_BMUX && _wire <= LO_DMUX)
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|| (_wire >= LO_BQ && _wire <= LO_DQ))
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return LW + ((_wire-1)|flags);
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}
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HERE();
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return wire;
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}
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static int construct_extract_state(struct extract_state* es, struct fpga_model* model)
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{
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char from_str[MAX_WIRENAME_LEN], to_str[MAX_WIRENAME_LEN];
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int i, j, k, l, cur_pair_start, cur_two_bits_o, cur_two_bits_val, rc;
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int logicin_i;
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memset(es, 0, sizeof(*es));
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es->model = model;
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if (model->first_routing_y == -1)
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FAIL(EINVAL);
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#if 0
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// mip 0-10 (6*288=1728 switches)
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{ struct sw_mip_src src[] = {
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{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 2, 3,
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DW + ((W_NW4*4+3) | DIR_BEG), 14, 1, 2,
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{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
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LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
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{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 1, 3,
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DW + ((W_NW4*4+3) | DIR_BEG), 14, 2, 2,
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{DW + ((W_SW2*4+2)|DIR_N3), DW + ((W_SS2*4+2)|DIR_N3), DW + ((W_WW2*4+2)|DIR_N3),
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DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_NW2*4+3}},
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{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 0, 3,
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DW + ((W_NW4*4+3) | DIR_BEG), 14, 0, 2,
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{DW + ((W_SW4*4+2)|DIR_N3), DW + ((W_SS4*4+2)|DIR_N3), DW + W_NE4*4+3,
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DW + W_NN4*4+3, DW + W_NW4*4+3, DW + W_WW4*4+3}},
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{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 2, 18,
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DW + ((W_SW4*4+3) | DIR_BEG), 30, 1, 19,
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{DW + W_SW2*4+3, DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0),
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DW + W_SS2*4+3, DW + W_SE2*4+3, DW + W_EE2*4+3}},
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{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 1, 18,
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DW + ((W_SW4*4+3) | DIR_BEG), 30, 2, 19,
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{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
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LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
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{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 0, 18,
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DW + ((W_SW4*4+3) | DIR_BEG), 30, 0, 19,
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{DW + W_SW4*4+3, DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0),
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DW + ((W_NW4*4+0)|DIR_S0), DW + W_SE4*4+3, DW + W_EE4*4+3}},
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{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 2, 3,
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DW + ((W_NE4*4+3) | DIR_BEG), 14, 1, 2,
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{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
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LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
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{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 1, 3,
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DW + ((W_NE4*4+3) | DIR_BEG), 14, 2, 2,
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{DW + W_EE2*4+3, DW + W_SE2*4+3, DW + ((W_WW2*4+2)|DIR_N3),
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DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_NW2*4+3}},
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{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 0, 3,
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DW + ((W_NE4*4+3) | DIR_BEG), 14, 0, 2,
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{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
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DW + W_NN4*4+3, DW + W_NW4*4+3, DW + W_WW4*4+3}},
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{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 2, 18,
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DW + ((W_SE4*4+3) | DIR_BEG), 30, 1, 19,
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{DW + W_SW2*4+3, DW + W_NN2*4+3, DW + W_NE2*4+3,
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DW + W_SS2*4+3, DW + W_SE2*4+3, DW + W_EE2*4+3}},
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{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 1, 18,
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DW + ((W_SE4*4+3) | DIR_BEG), 30, 2, 19,
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{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
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LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
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{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 0, 18,
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DW + ((W_SE4*4+3) | DIR_BEG), 30, 0, 19,
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{DW + W_SW4*4+3, DW + W_SS4*4+3, DW + W_NN4*4+3,
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DW + W_NE4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}},
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{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 2, 3,
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DW + ((W_NN2*4+3) | DIR_BEG), 14, 1, 2,
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{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
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LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
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{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 1, 3,
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DW + ((W_NN2*4+3) | DIR_BEG), 14, 2, 2,
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{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + ((W_WL1*4+2)|DIR_N3),
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DW + W_WR1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
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{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 0, 3,
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DW + ((W_NN2*4+3) | DIR_BEG), 14, 0, 2,
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{DW + W_NW4*4+3, DW + W_WW4*4+3, DW + W_NE4*4+3,
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DW + W_NN4*4+3, DW + ((W_WW2*4+2)|DIR_N3), DW + W_NW2*4+3}},
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{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 2, 18,
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DW + ((W_SW2*4+3) | DIR_BEG), 30, 1, 19,
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{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + ((W_WR1*4+0)|DIR_S0),
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DW + W_WL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
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{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 1, 18,
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DW + ((W_SW2*4+3) | DIR_BEG), 30, 2, 19,
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{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
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LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
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{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 0, 18,
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DW + ((W_SW2*4+3) | DIR_BEG), 30, 0, 19,
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{DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0), DW + W_SW4*4+3,
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DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0), DW + ((W_NW4*4+0)|DIR_S0)}},
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{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 2, 3,
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DW + ((W_EE2*4+3) | DIR_BEG), 14, 1, 2,
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{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
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LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
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{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 1, 3,
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DW + ((W_EE2*4+3) | DIR_BEG), 14, 2, 2,
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{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_EL1*4+3,
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DW + W_ER1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
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{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 0, 3,
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DW + ((W_EE2*4+3) | DIR_BEG), 14, 0, 2,
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{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
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DW + W_NN4*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
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{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 2, 18,
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DW + ((W_SE2*4+3) | DIR_BEG), 30, 1, 19,
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{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + W_ER1*4+3,
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DW + W_EL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
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{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 1, 18,
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DW + ((W_SE2*4+3) | DIR_BEG), 30, 2, 19,
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{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
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LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
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{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 0, 18,
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DW + ((W_SE2*4+3) | DIR_BEG), 30, 0, 19,
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{DW + W_SE2*4+3, DW + W_EE2*4+3, DW + W_SW4*4+3,
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DW + W_SS4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}},
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{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 2, 3,
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DW + ((W_NL1*4+2) | DIR_BEG), 14, 1, 2,
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{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
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LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
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{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 1, 3,
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DW + ((W_NL1*4+2) | DIR_BEG), 14, 2, 2,
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{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + ((W_WL1*4+2)|DIR_N3),
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DW + W_WR1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
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{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 0, 3,
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DW + ((W_NL1*4+2) | DIR_BEG), 14, 0, 2,
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{DW + W_NW4*4+3, DW + W_WW4*4+3, DW + W_NE4*4+3,
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DW + W_NN4*4+3, DW + ((W_WW2*4+2)|DIR_N3), DW + W_NW2*4+3}},
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{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 2, 18,
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DW + ((W_WL1*4+2) | DIR_BEG), 30, 1, 19,
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{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + ((W_WR1*4+0)|DIR_S0),
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DW + W_WL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
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{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 1, 18,
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DW + ((W_WL1*4+2) | DIR_BEG), 30, 2, 19,
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{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
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LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
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{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 0, 18,
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DW + ((W_WL1*4+2) | DIR_BEG), 30, 0, 19,
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{DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0), DW + W_SW4*4+3,
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DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0), DW + ((W_NW4*4+0)|DIR_S0)}},
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{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 2, 3,
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DW + ((W_NR1*4+3) | DIR_BEG), 14, 1, 2,
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{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
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LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
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{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 1, 3,
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DW + ((W_NR1*4+3) | DIR_BEG), 14, 2, 2,
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{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_EL1*4+3,
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DW + W_ER1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
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{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 0, 3,
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DW + ((W_NR1*4+3) | DIR_BEG), 14, 0, 2,
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{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
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DW + W_NN4*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
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{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 2, 18,
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DW + ((W_ER1*4+0) | DIR_BEG), 30, 1, 19,
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{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + W_ER1*4+3,
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DW + W_EL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
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{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 1, 18,
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DW + ((W_ER1*4+0) | DIR_BEG), 30, 2, 19,
|
||||
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
||||
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
||||
{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 0, 18,
|
||||
DW + ((W_ER1*4+0) | DIR_BEG), 30, 0, 19,
|
||||
{DW + W_SE2*4+3, DW + W_EE2*4+3, DW + W_SW4*4+3,
|
||||
DW + W_SS4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}}};
|
||||
|
||||
for (i = 0;; i++) {
|
||||
rc = src_to_bitpos(es, src, sizeof(src)/sizeof(*src));
|
||||
if (rc) FAIL(rc);
|
||||
if (i >= 3) break;
|
||||
for (j = 0; j < sizeof(src)/sizeof(*src); j++) {
|
||||
src[j].m0_sw_to = wire_decrement(src[j].m0_sw_to);
|
||||
src[j].m0_two_bits_o += 32;
|
||||
src[j].m0_one_bit_start += 32;
|
||||
src[j].m1_sw_to = wire_decrement(src[j].m1_sw_to);
|
||||
src[j].m1_two_bits_o += 32;
|
||||
src[j].m1_one_bit_start += 32;
|
||||
for (k = 0; k < sizeof(src[0].src_wire)/sizeof(src[0].src_wire[0]); k++)
|
||||
src[j].src_wire[k] = wire_decrement(src[j].src_wire[k]);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
// todo: 12
|
||||
#if 0
|
||||
// switches from logicout to dirwires (6*2*2*4*6=576 switches)
|
||||
for (i = 0; i < DIRBEG_ROW; i++) {
|
||||
|
|
|
|||
24
control.c
24
control.c
|
|
@ -1865,21 +1865,19 @@ const char* fpga_wirestr(struct fpga_model* model, enum extra_wires wire)
|
|||
snprintf(buf[last_buf], sizeof(buf[0]), "GCLK%i", wire-GCLK0);
|
||||
else if (wire >= DW && wire <= DW_LAST) {
|
||||
char beg_end;
|
||||
int s0n3_flag;
|
||||
int flags;
|
||||
|
||||
wire -= DW;
|
||||
beg_end = (wire & DIR_BEG) ? 'B' : 'E';
|
||||
s0n3_flag = wire & DIR_S0N3;
|
||||
wire &= ~(DIR_BEG|DIR_S0N3);
|
||||
if (s0n3_flag) {
|
||||
if (wire%4 == 0) {
|
||||
snprintf(buf[last_buf], sizeof(buf[0]),
|
||||
"%s%c_S0", wire_base(wire/4), beg_end);
|
||||
} else if (wire%4 == 3) {
|
||||
snprintf(buf[last_buf], sizeof(buf[0]),
|
||||
"%s%c_N3", wire_base(wire/4), beg_end);
|
||||
} else HERE();
|
||||
} else
|
||||
flags = wire & DIR_FLAGS;
|
||||
wire &= ~DIR_FLAGS;
|
||||
beg_end = (flags & DIR_BEG) ? 'B' : 'E';
|
||||
if (flags & DIR_S0 && wire%4 == 0)
|
||||
snprintf(buf[last_buf], sizeof(buf[0]),
|
||||
"%s%c_S0", wire_base(wire/4), beg_end);
|
||||
else if (flags & DIR_N3 && wire%4 == 3)
|
||||
snprintf(buf[last_buf], sizeof(buf[0]),
|
||||
"%s%c_N3", wire_base(wire/4), beg_end);
|
||||
else
|
||||
snprintf(buf[last_buf], sizeof(buf[0]),
|
||||
"%s%c%i", wire_base(wire/4), beg_end, wire%4);
|
||||
|
||||
|
|
|
|||
12
model.h
12
model.h
|
|
@ -766,11 +766,15 @@ const char* wire_base(enum wire_type w);
|
|||
enum wire_type rotate_wire(enum wire_type cur, int off);
|
||||
enum wire_type wire_to_len(enum wire_type w, int first_len);
|
||||
|
||||
// Those two flags can be OR'ed into the DW..DW_LAST range.
|
||||
// These three flags can be OR'ed into the DW..DW_LAST range.
|
||||
// DIR_BEG signals a 'B' line - the default is 'E' endpoint.
|
||||
// DIR_S0N3 turns 0 into _S0 and 3 into _N3.
|
||||
#define DIR_BEG 0x100
|
||||
#define DIR_S0N3 0x200
|
||||
// DIR_S0 turns 0 into _S0
|
||||
// DIR_N3 turns 3 into _N3.
|
||||
// First flag must be higher than LAST_LEN4 (25) * 4 + 3 = 103
|
||||
#define DIR_BEG 0x80
|
||||
#define DIR_S0 0x100
|
||||
#define DIR_N3 0x200
|
||||
#define DIR_FLAGS (DIR_BEG|DIR_S0|DIR_N3)
|
||||
|
||||
// The extra wires must not overlap with logicin_wire or logicout_wire
|
||||
// namespaces so that they can be combined with either of them.
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user