switch cleanup
This commit is contained in:
Wolfgang Spraul
parent
0fa0e7f3c3
commit
279cd02600
1
.gitignore
vendored
1
.gitignore
vendored
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@ -31,3 +31,4 @@ bit2fp.o
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parts.o
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autotest.tmp/
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autotest.out/
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compare.gold/
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31
Makefile
31
Makefile
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@ -148,22 +148,25 @@ libfpga-floorplan.a: $(LIBFPGA_FLOORPLAN_OBJS)
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libfpga-control.a: $(LIBFPGA_CONTROL_OBJS)
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$(AR) $@ $^
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xc6slx9_empty.fp: new_fp
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xc6slx9.fp: new_fp
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./new_fp > $@
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xc6slx9.svg: draw_svg_tiles
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./draw_svg_tiles | xmllint --pretty 1 - > $@
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compare_all: compare.tiles compare.devs compare.conns compare.ports compare.sw
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compare_all: compare_tiles compare_devs compare_conns \
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compare_ports compare_sw compare_swbits
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compare.%: xc6slx9_empty.%
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@comm -1 -2 $< compare_other.$* > compare_$*_matching.txt
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compare_gold: compare.gold/xc6slx9.swbits
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compare_%: xc6slx9.%
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@comm -1 -2 $< compare.gold/$< > compare_$*_matching.txt
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@echo Matching lines - compare_$*_matching.txt:
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@cat compare_$*_matching.txt | wc -l
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@diff -u compare_other.$* $< > compare_$*_diff.txt || true
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@diff -u compare.gold/$< $< > compare_$*_diff.txt || true
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@echo Missing lines - compare_$*_diff.txt
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@cat compare_$*_diff.txt | grep ^-y | wc -l
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@cat compare_$*_diff.txt | grep ^+y > compare_$*_extra.txt || true
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@cat compare_$*_diff.txt | grep ^-[^-] | wc -l
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@cat compare_$*_diff.txt | grep ^+[^+] > compare_$*_extra.txt || true
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@if test -s compare_$*_extra.txt; then echo Extra lines - compare_$*_extra.txt: ; cat compare_$*_extra.txt; fi;
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%.tiles: %.fp
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@ -190,6 +193,9 @@ compare.%: xc6slx9_empty.%
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%.sw: %.fp
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@cat $<|awk '{if ($$1=="sw") printf "%s %s %s %s %s\n",$$2,$$3,$$4,$$5,$$6}'|sort >$@
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%.swbits: bit2fp
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./bit2fp --printf-swbits | sort > $@
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clean:
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rm -f $(foreach test,$(TESTS),"autotest.out/autotest_$(test).diff_to_gold")
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rm -f $(foreach test,$(TESTS),"autotest.out/autotest_$(test).log")
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@ -206,17 +212,16 @@ clean:
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bit2fp bit2fp.o \
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pair2net pair2net.o \
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libfpga-bit.a libfpga-control.a libfpga-cores.a libfpga-floorplan.a libfpga-model.a \
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xc6slx9_empty.fp xc6slx9.svg \
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xc6slx9_empty.tiles xc6slx9_empty.devs xc6slx9_empty.conns \
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xc6slx9_empty.ports xc6slx9_empty.sw xc6slx9_empty.cnets \
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compare_other.tiles compare_other.devs compare_other.conns compare_other.ports \
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compare_other.sw compare_other.cnets \
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xc6slx9.fp xc6slx9.svg \
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xc6slx9.tiles xc6slx9.devs xc6slx9.conns \
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xc6slx9.ports xc6slx9.sw xc6slx9.cnets xc6slx9.swbits \
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compare_tiles_matching.txt compare_tiles_diff.txt compare_tiles_extra.txt \
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compare_devs_matching.txt compare_devs_diff.txt compare_devs_extra.txt \
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compare_conns_matching.txt compare_conns_diff.txt compare_conns_extra.txt \
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compare_ports_matching.txt compare_ports_diff.txt compare_ports_extra.txt \
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compare_sw_matching.txt compare_sw_diff.txt compare_sw_extra.txt \
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compare_cnets_matching.txt compare_cnets_diff.txt compare_cnets_extra.txt
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compare_cnets_matching.txt compare_cnets_diff.txt compare_cnets_extra.txt \
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compare_swbits_matching.txt compare_swbits_diff.txt compare_swbits_extra.txt
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install: all
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mkdir -p $(DESTDIR)/$(PREFIX)/bin/
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146
autotest.c
146
autotest.c
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@ -500,7 +500,9 @@ fail:
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return rc;
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}
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static int test_routing_sw_from_south(struct test_state* tstate,
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int test_routing_sw_from_iob(struct test_state* tstate,
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swidx_t* done_list, int* done_list_len);
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int test_routing_sw_from_iob(struct test_state* tstate,
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swidx_t* done_list, int* done_list_len)
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{
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struct switch_to_yx switch_to;
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@ -577,7 +579,7 @@ fail:
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return rc;
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}
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static int test_routing_sw_from_north(struct test_state* tstate,
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static int test_routing_sw_from_logic(struct test_state* tstate,
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swidx_t* done_list, int* done_list_len)
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{
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struct fpga_device* dev;
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@ -585,79 +587,85 @@ static int test_routing_sw_from_north(struct test_state* tstate,
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struct sw_conns conns;
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const char* str;
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net_idx_t net;
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int y, x, i, rc;
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int y, x, rel_y, i, rc;
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y = 67;
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x = 13;
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for (i = '1'; i <= '6'; i++) {
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rc = fdev_logic_set_lut(tstate->model, y, x,
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DEV_LOGM, LUT_A, 6, pf("A%c", i), ZTERM);
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if (rc) FAIL(rc);
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rc = fdev_set_required_pins(tstate->model, y, x,
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DEV_LOGIC, DEV_LOGM);
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if (rc) FAIL(rc);
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if (tstate->dry_run)
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fdev_print_required_pins(tstate->model,
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y, x, DEV_LOGIC, DEV_LOGM);
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dev = fdev_p(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
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if (!dev) FAIL(EINVAL);
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if (!dev->pinw_req_in) FAIL(EINVAL);
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rc = fpga_net_new(tstate->model, &net);
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if (rc) FAIL(rc);
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rc = fpga_net_add_port(tstate->model, net, y, x,
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DEV_LOGIC, DEV_LOGM, dev->pinw_req_for_cfg[0]);
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if (rc) FAIL(rc);
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swto.model = tstate->model;
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swto.start_y = y;
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swto.start_x = x;
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swto.start_switch = fdev_logic_pinstr_i(tstate->model,
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dev->pinw_req_for_cfg[0]|LD1, LOGIC_M);
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swto.from_to = SW_TO;
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swto.rel_y = 0;
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swto.rel_x = -1;
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swto.target_connpt = STRIDX_NO_ENTRY;
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rc = fpga_switch_to_rel(&swto);
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if (rc) FAIL(rc);
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if (!swto.set.len) FAIL(EINVAL);
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if (tstate->dry_run)
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printf_switch_to_rel_result(&swto);
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rc = fpga_net_add_sw(tstate->model, net, swto.start_y,
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swto.start_x, swto.set.sw, swto.set.len);
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if (rc) FAIL(rc);
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rc = construct_sw_conns(&conns, tstate->model, swto.dest_y, swto.dest_x,
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swto.dest_connpt, SW_TO, /*max_depth*/ 1);
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if (rc) FAIL(rc);
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while (fpga_switch_conns(&conns) != NO_CONN) {
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if (conns.dest_x != swto.dest_x
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|| conns.dest_y != swto.dest_y+1)
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continue;
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str = strarray_lookup(&tstate->model->str, conns.dest_str_i);
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if (!str) { HERE(); continue; }
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if (strlen(str) < 5
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|| str[2] != '1' || str[3] != 'B')
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continue;
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rc = fpga_net_add_sw(tstate->model, net, swto.dest_y,
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swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
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// We loop over this twice, once with rel_y==-1 and then with rel_y==+1
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// That way we come into the routing switchbox over the nr1/nl1 wires
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// from below, or sr1/sl1 wires from above.
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for (rel_y = -1; rel_y <= 1; rel_y += 2) {
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for (i = '1'; i <= '6'; i++) {
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rc = fdev_logic_set_lut(tstate->model, y, x,
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DEV_LOGM, LUT_A, 6, pf("A%c", i), ZTERM);
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if (rc) FAIL(rc);
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rc = fdev_set_required_pins(tstate->model, y, x,
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DEV_LOGIC, DEV_LOGM);
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if (rc) FAIL(rc);
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if (tstate->dry_run)
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fprintf_net(stdout, tstate->model, net);
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rc = test_switches(tstate, conns.dest_y, conns.dest_x,
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conns.dest_str_i, net, done_list, done_list_len);
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fdev_print_required_pins(tstate->model,
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y, x, DEV_LOGIC, DEV_LOGM);
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dev = fdev_p(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
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if (!dev) FAIL(EINVAL);
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if (!dev->pinw_req_in) FAIL(EINVAL);
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rc = fpga_net_new(tstate->model, &net);
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if (rc) FAIL(rc);
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rc = fpga_net_remove_sw(tstate->model, net, swto.dest_y,
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swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
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rc = fpga_net_add_port(tstate->model, net, y, x,
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DEV_LOGIC, DEV_LOGM, dev->pinw_req_for_cfg[0]);
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if (rc) FAIL(rc);
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swto.model = tstate->model;
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swto.start_y = y;
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swto.start_x = x;
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swto.start_switch = fdev_logic_pinstr_i(tstate->model,
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dev->pinw_req_for_cfg[0]|LD1, LOGIC_M);
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swto.from_to = SW_TO;
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swto.rel_y = 0;
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swto.rel_x = -1;
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swto.target_connpt = STRIDX_NO_ENTRY;
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rc = fpga_switch_to_rel(&swto);
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if (rc) FAIL(rc);
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if (!swto.set.len) FAIL(EINVAL);
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if (tstate->dry_run)
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printf_switch_to_rel_result(&swto);
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rc = fpga_net_add_sw(tstate->model, net, swto.start_y,
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swto.start_x, swto.set.sw, swto.set.len);
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if (rc) FAIL(rc);
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rc = construct_sw_conns(&conns, tstate->model, swto.dest_y, swto.dest_x,
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swto.dest_connpt, SW_TO, /*max_depth*/ 1);
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if (rc) FAIL(rc);
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while (fpga_switch_conns(&conns) != NO_CONN) {
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if (conns.dest_x != swto.dest_x
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|| conns.dest_y != swto.dest_y+rel_y)
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continue;
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str = strarray_lookup(&tstate->model->str, conns.dest_str_i);
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if (!str) { HERE(); continue; }
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if (strlen(str) < 5
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|| str[2] != '1' || str[3] != 'B')
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continue;
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rc = fpga_net_add_sw(tstate->model, net, swto.dest_y,
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swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
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if (rc) FAIL(rc);
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if (tstate->dry_run)
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fprintf_net(stdout, tstate->model, net);
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rc = test_switches(tstate, conns.dest_y, conns.dest_x,
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conns.dest_str_i, net, done_list, done_list_len);
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if (rc) FAIL(rc);
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rc = fpga_net_remove_sw(tstate->model, net, swto.dest_y,
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swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
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if (rc) FAIL(rc);
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}
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destruct_sw_conns(&conns);
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fdev_delete(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
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fpga_net_delete(tstate->model, net);
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}
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destruct_sw_conns(&conns);
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fdev_delete(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
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fpga_net_delete(tstate->model, net);
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}
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return 0;
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fail:
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@ -744,9 +752,7 @@ static int test_routing_switches(struct test_state* tstate)
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}
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}
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done_sw_len = 0;
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rc = test_routing_sw_from_south(tstate, done_sw_list, &done_sw_len);
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if (rc) FAIL(rc);
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rc = test_routing_sw_from_north(tstate, done_sw_list, &done_sw_len);
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rc = test_routing_sw_from_logic(tstate, done_sw_list, &done_sw_len);
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if (rc) FAIL(rc);
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return 0;
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fail:
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2
bit.h
2
bit.h
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@ -92,5 +92,5 @@ void free_config(struct fpga_config* cfg);
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int write_bitfile(FILE* f, struct fpga_model* model);
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int extract_model(struct fpga_model* model, struct fpga_bits* bits);
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int printf_routing_mips(struct fpga_model* model);
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int printf_swbits(struct fpga_model* model);
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int write_model(struct fpga_bits* bits, struct fpga_model* model);
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14
bit2fp.c
14
bit2fp.c
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@ -13,7 +13,7 @@ int main(int argc, char** argv)
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{
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struct fpga_model model;
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int bit_header, bit_regs, fp_header, pull_model, file_arg, flags;
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int dump_routing_mips, rc = -1;
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int print_swbits, rc = -1;
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struct fpga_config config;
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// parameters
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@ -22,7 +22,7 @@ int main(int argc, char** argv)
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"\n"
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"%s - bitstream to floorplan\n"
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"Usage: %s [--bit-header] [--bit-regs] [--no-model] [--no-fp-header]\n"
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" %*s [--dump-routing-mips] <bitstream_file>\n"
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" %*s [--printf-swbits] <bitstream_file>\n"
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"\n", argv[0], argv[0], (int) strlen(argv[0]), "");
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goto fail;
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}
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@ -31,7 +31,7 @@ int main(int argc, char** argv)
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pull_model = 1;
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fp_header = 1;
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file_arg = 1;
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dump_routing_mips = 0;
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print_swbits = 0;
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while (file_arg < argc
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&& !strncmp(argv[file_arg], "--", 2)) {
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if (!strcmp(argv[file_arg], "--bit-header"))
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@ -42,8 +42,8 @@ int main(int argc, char** argv)
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pull_model = 0;
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else if (!strcmp(argv[file_arg], "--no-fp-header"))
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fp_header = 0;
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else if (!strcmp(argv[file_arg], "--dump-routing-mips"))
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dump_routing_mips = 1;
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else if (!strcmp(argv[file_arg], "--printf-swbits"))
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print_swbits = 1;
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else break;
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file_arg++;
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}
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@ -52,8 +52,8 @@ int main(int argc, char** argv)
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if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
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XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING))) FAIL(rc);
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if (dump_routing_mips) {
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rc = printf_routing_mips(&model);
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if (print_swbits) {
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rc = printf_swbits(&model);
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if (rc) FAIL(rc);
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return 0;
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}
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164
bit_frames.c
164
bit_frames.c
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@ -73,19 +73,26 @@ static struct bit_pos s_default_bits[] = {
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{ 0, 1, 23, 1039 },
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{ 2, 0, 3, 66 }};
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// swpos_mip is relative to a tile, i.e. major (x) and
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// sw_bitpos is relative to a tile, i.e. major (x) and
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// row/v64_i (y) are defined outside.
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struct swpos_mip
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struct sw_bitpos
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{
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int mip; // 0-18, even only
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int two_bits_o; // 0-127, even only
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// minors 0-19 are minor pairs, minor will be set
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// to the even beginning of the pair, two_bits_o and
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// one_bit_o are within 2*64 bits of the two minors.
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// Even bit offsets are from the first minor, odd bit
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// offsets from the second minor.
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// minor 20 is a regular single 64-bit minor.
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int minor; // 0,2,4,..18 for pairs, 20 for single-minor
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int two_bits_o; // 0-126 for pairs (even only), 0-62 for single-minor
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int two_bits_val; // 0-3
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int one_bit_o; // 0-127, 1-6 bits up or down from two-bit val
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int one_bit_o; // 1-6 positions up or down from two-bit pos
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swidx_t uni_dir;
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swidx_t rev_dir; // NO_SWITCH for unidirectional switches
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};
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struct swpos_yx
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struct sw_yxpos
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{
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int y;
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int x;
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@ -98,12 +105,12 @@ struct extract_state
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{
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struct fpga_model* model;
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struct fpga_bits* bits;
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int num_mips;
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struct swpos_mip mip[MAX_SWITCHBOX_SIZE];
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int num_bit_pos;
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struct sw_bitpos bit_pos[MAX_SWITCHBOX_SIZE];
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// yx switches are fully extracted ones pointing into the
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// model, stored here for later processing into nets.
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int num_sw_yx;
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struct swpos_yx sw_yx[MAX_YX_SWITCHES]; // needs to be dynamically alloced...
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int num_yx_pos;
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struct sw_yxpos yx_pos[MAX_YX_SWITCHES]; // needs to be dynamically alloced...
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};
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static int extract_iobs(struct fpga_model* model, struct fpga_bits* bits)
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@ -315,7 +322,7 @@ fail:
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}
|
||||
|
||||
static int mip_is_set(struct extract_state* es, int y, int x,
|
||||
struct swpos_mip* swpos, int* is_set)
|
||||
struct sw_bitpos* swpos, int* is_set)
|
||||
{
|
||||
int row_num, row_pos, start_in_frame, two_bits_val, rc;
|
||||
|
||||
|
|
@ -329,15 +336,15 @@ static int mip_is_set(struct extract_state* es, int y, int x,
|
|||
start_in_frame = row_pos*64;
|
||||
|
||||
two_bits_val =
|
||||
(get_bit(es->bits, row_num, es->model->x_major[x], swpos->mip,
|
||||
(get_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
|
||||
start_in_frame + swpos->two_bits_o/2) << 1)
|
||||
| (get_bit(es->bits, row_num, es->model->x_major[x], swpos->mip+1,
|
||||
| (get_bit(es->bits, row_num, es->model->x_major[x], swpos->minor+1,
|
||||
start_in_frame + swpos->two_bits_o/2) << 2);
|
||||
if (two_bits_val != swpos->two_bits_val)
|
||||
return 0;
|
||||
|
||||
if (!get_bit(es->bits, row_num, es->model->x_major[x],
|
||||
swpos->mip + (swpos->one_bit_o&1),
|
||||
swpos->minor + (swpos->one_bit_o&1),
|
||||
start_in_frame + swpos->one_bit_o/2))
|
||||
return 0;
|
||||
*is_set = 1;
|
||||
|
|
@ -347,7 +354,7 @@ fail:
|
|||
}
|
||||
|
||||
static int mip_clear_bits(struct extract_state* es, int y, int x,
|
||||
struct swpos_mip* swpos)
|
||||
struct sw_bitpos* swpos)
|
||||
{
|
||||
int row_num, row_pos, start_in_frame, rc;
|
||||
|
||||
|
|
@ -359,11 +366,11 @@ static int mip_clear_bits(struct extract_state* es, int y, int x,
|
|||
else
|
||||
start_in_frame = row_pos*64;
|
||||
|
||||
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->mip,
|
||||
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
|
||||
start_in_frame + swpos->two_bits_o/2);
|
||||
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->mip + 1,
|
||||
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor+ 1,
|
||||
start_in_frame + swpos->two_bits_o/2);
|
||||
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->mip + (swpos->one_bit_o&1),
|
||||
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor + (swpos->one_bit_o&1),
|
||||
start_in_frame + swpos->one_bit_o/2);
|
||||
|
||||
return 0;
|
||||
|
|
@ -379,27 +386,22 @@ static int extract_routing_switches(struct extract_state* es, int y, int x)
|
|||
tile = YX_TILE(es->model, y, x);
|
||||
if (y != 68 || x != 12) return 0;
|
||||
|
||||
// build tile-relative model of all routing switches and
|
||||
// store in the extract state
|
||||
if (!es->num_mips) {
|
||||
}
|
||||
|
||||
for (i = 0; i < es->num_mips; i++) {
|
||||
rc = mip_is_set(es, y, x, &es->mip[i], &is_set);
|
||||
for (i = 0; i < es->num_bit_pos; i++) {
|
||||
rc = mip_is_set(es, y, x, &es->bit_pos[i], &is_set);
|
||||
if (rc) FAIL(rc);
|
||||
if (!is_set) continue;
|
||||
|
||||
if (tile->switches[es->mip[i].uni_dir] & SWITCH_BIDIRECTIONAL)
|
||||
if (tile->switches[es->bit_pos[i].uni_dir] & SWITCH_BIDIRECTIONAL)
|
||||
HERE();
|
||||
if (tile->switches[es->mip[i].uni_dir] & SWITCH_USED)
|
||||
if (tile->switches[es->bit_pos[i].uni_dir] & SWITCH_USED)
|
||||
HERE();
|
||||
if (es->num_sw_yx >= MAX_YX_SWITCHES)
|
||||
if (es->num_yx_pos >= MAX_YX_SWITCHES)
|
||||
{ FAIL(ENOTSUP); }
|
||||
es->sw_yx[es->num_sw_yx].y = y;
|
||||
es->sw_yx[es->num_sw_yx].x = x;
|
||||
es->sw_yx[es->num_sw_yx].idx = es->mip[i].uni_dir;
|
||||
es->num_sw_yx++;
|
||||
rc = mip_clear_bits(es, y, x, &es->mip[i]);
|
||||
es->yx_pos[es->num_yx_pos].y = y;
|
||||
es->yx_pos[es->num_yx_pos].x = x;
|
||||
es->yx_pos[es->num_yx_pos].idx = es->bit_pos[i].uni_dir;
|
||||
es->num_yx_pos++;
|
||||
rc = mip_clear_bits(es, y, x, &es->bit_pos[i]);
|
||||
if (rc) FAIL(rc);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -484,7 +486,7 @@ static int mod4_calc(int a, int b)
|
|||
static int construct_extract_state(struct extract_state* es, struct fpga_model* model)
|
||||
{
|
||||
char from_str[MAX_WIRENAME_LEN], to_str[MAX_WIRENAME_LEN];
|
||||
int i, j, k, l, cur_mip, cur_two_bits_o, cur_two_bits_val, rc;
|
||||
int i, j, k, l, cur_pair_start, cur_two_bits_o, cur_two_bits_val, rc;
|
||||
int logicin_i;
|
||||
|
||||
memset(es, 0, sizeof(*es));
|
||||
|
|
@ -494,36 +496,36 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
|
|||
|
||||
// switches from logicout to dirwires (6*2*2*4*6=576 switches)
|
||||
for (i = 0; i < DIRBEG_ROW; i++) {
|
||||
cur_mip = (i/2)*2;
|
||||
cur_pair_start = (i/2)*2;
|
||||
for (j = 0; j <= 3; j++) { // 4 wires for each dirwire
|
||||
for (k = 0; k <= 1; k++) { // two dirbeg rows
|
||||
cur_two_bits_o = j*32 + k*16;
|
||||
if (i%2) cur_two_bits_o += 14;
|
||||
cur_two_bits_val = ((i%2)^k) ? 1 : 2;
|
||||
for (l = 0; l < LOGOUT_ROW; l++) {
|
||||
es->mip[es->num_mips].mip = cur_mip;
|
||||
es->mip[es->num_mips].two_bits_o = cur_two_bits_o;
|
||||
es->mip[es->num_mips].two_bits_val = cur_two_bits_val;
|
||||
es->bit_pos[es->num_bit_pos].minor = cur_pair_start;
|
||||
es->bit_pos[es->num_bit_pos].two_bits_o = cur_two_bits_o;
|
||||
es->bit_pos[es->num_bit_pos].two_bits_val = cur_two_bits_val;
|
||||
|
||||
es->mip[es->num_mips].one_bit_o = j*32+k*16+2+l*2;
|
||||
es->bit_pos[es->num_bit_pos].one_bit_o = j*32+k*16+2+l*2;
|
||||
if (!((i%2)^k)) // right side (second minor)
|
||||
es->mip[es->num_mips].one_bit_o++;
|
||||
es->bit_pos[es->num_bit_pos].one_bit_o++;
|
||||
|
||||
snprintf(from_str, sizeof(from_str), "LOGICOUT%i", logicout_matrix[j*LOGOUT_ROW + (k?5-l:l)]);
|
||||
snprintf(to_str, sizeof(to_str), "%sB%i",
|
||||
wire_base(dirbeg_matrix[k*DIRBEG_ROW+i]), mod4_calc(dirbeg_matrix_topnum[k*DIRBEG_ROW+i], -j));
|
||||
es->mip[es->num_mips].uni_dir = fpga_switch_lookup(es->model,
|
||||
es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
|
||||
es->model->first_routing_y, es->model->first_routing_x,
|
||||
strarray_find(&es->model->str, from_str),
|
||||
strarray_find(&es->model->str, to_str));
|
||||
if (es->mip[es->num_mips].uni_dir == NO_SWITCH) {
|
||||
if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
|
||||
fprintf(stderr, "#E routing switch %s -> %s not in model\n",
|
||||
from_str, to_str);
|
||||
FAIL(EINVAL);
|
||||
}
|
||||
|
||||
es->mip[es->num_mips].rev_dir = NO_SWITCH;
|
||||
es->num_mips++;
|
||||
es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
|
||||
es->num_bit_pos++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -535,42 +537,42 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
|
|||
for (k = 0; k <= 1; k++) { // two switch destinations
|
||||
|
||||
// VCC
|
||||
es->mip[es->num_mips].mip = i;
|
||||
es->mip[es->num_mips].two_bits_o = 32*j + (k?14:0);
|
||||
es->mip[es->num_mips].two_bits_val = 3;
|
||||
es->mip[es->num_mips].one_bit_o = 32*j+2;
|
||||
es->bit_pos[es->num_bit_pos].minor = i;
|
||||
es->bit_pos[es->num_bit_pos].two_bits_o = 32*j + (k?14:0);
|
||||
es->bit_pos[es->num_bit_pos].two_bits_val = 3;
|
||||
es->bit_pos[es->num_bit_pos].one_bit_o = 32*j+2;
|
||||
logicin_i = j*2*LOGIN_ROW + i-12 + k;
|
||||
|
||||
if (i == 14 || i == 18) {
|
||||
es->mip[es->num_mips].two_bits_o += 16;
|
||||
es->mip[es->num_mips].one_bit_o += 16;
|
||||
es->mip[es->num_mips].one_bit_o += !k;
|
||||
es->bit_pos[es->num_bit_pos].two_bits_o += 16;
|
||||
es->bit_pos[es->num_bit_pos].one_bit_o += 16;
|
||||
es->bit_pos[es->num_bit_pos].one_bit_o += !k;
|
||||
logicin_i += LOGIN_ROW;
|
||||
} else
|
||||
es->mip[es->num_mips].one_bit_o += k;
|
||||
es->bit_pos[es->num_bit_pos].one_bit_o += k;
|
||||
|
||||
snprintf(to_str, sizeof(to_str), "LOGICIN_B%i", logicin_matrix[logicin_i]);
|
||||
es->mip[es->num_mips].uni_dir = fpga_switch_lookup(es->model,
|
||||
es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
|
||||
es->model->first_routing_y, es->model->first_routing_x,
|
||||
strarray_find(&es->model->str, "VCC_WIRE"),
|
||||
strarray_find(&es->model->str, to_str));
|
||||
if (es->mip[es->num_mips].uni_dir == NO_SWITCH) {
|
||||
if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
|
||||
fprintf(stderr, "#E routing switch VCC_WIRE -> %s not in model\n",
|
||||
to_str);
|
||||
FAIL(EINVAL);
|
||||
}
|
||||
es->mip[es->num_mips].rev_dir = NO_SWITCH;
|
||||
es->mip[es->num_mips+1] = es->mip[es->num_mips];
|
||||
es->num_mips++;
|
||||
es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
|
||||
es->bit_pos[es->num_bit_pos+1] = es->bit_pos[es->num_bit_pos];
|
||||
es->num_bit_pos++;
|
||||
|
||||
// GFAN
|
||||
if (i == 14 || i == 18) {
|
||||
es->mip[es->num_mips].two_bits_o -= 16;
|
||||
es->mip[es->num_mips].one_bit_o -= 16;
|
||||
es->bit_pos[es->num_bit_pos].two_bits_o -= 16;
|
||||
es->bit_pos[es->num_bit_pos].one_bit_o -= 16;
|
||||
logicin_i -= LOGIN_ROW;
|
||||
} else { // 12 or 16
|
||||
es->mip[es->num_mips].two_bits_o += 16;
|
||||
es->mip[es->num_mips].one_bit_o += 16;
|
||||
es->bit_pos[es->num_bit_pos].two_bits_o += 16;
|
||||
es->bit_pos[es->num_bit_pos].one_bit_o += 16;
|
||||
logicin_i += LOGIN_ROW;
|
||||
}
|
||||
snprintf(from_str, sizeof(from_str), "GFAN%i", j<2?1:0);
|
||||
|
|
@ -578,11 +580,11 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
|
|||
strcpy(to_str, "FAN_B");
|
||||
else
|
||||
snprintf(to_str, sizeof(to_str), "LOGICIN_B%i", logicin_matrix[logicin_i]);
|
||||
es->mip[es->num_mips].uni_dir = fpga_switch_lookup(es->model,
|
||||
es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
|
||||
es->model->first_routing_y, es->model->first_routing_x,
|
||||
strarray_find(&es->model->str, from_str),
|
||||
strarray_find(&es->model->str, to_str));
|
||||
if (es->mip[es->num_mips].uni_dir == NO_SWITCH) {
|
||||
if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
|
||||
fprintf(stderr, "#E routing switch %s -> %s not in model\n",
|
||||
from_str, to_str);
|
||||
FAIL(EINVAL);
|
||||
|
|
@ -593,18 +595,18 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
|
|||
|| logicin_matrix[logicin_i] == 35
|
||||
|| logicin_matrix[logicin_i] == 51
|
||||
|| logicin_matrix[logicin_i] == 53) {
|
||||
es->mip[es->num_mips].rev_dir = fpga_switch_lookup(es->model,
|
||||
es->bit_pos[es->num_bit_pos].rev_dir = fpga_switch_lookup(es->model,
|
||||
es->model->first_routing_y, es->model->first_routing_x,
|
||||
strarray_find(&es->model->str, to_str),
|
||||
strarray_find(&es->model->str, from_str));
|
||||
if (es->mip[es->num_mips].rev_dir == NO_SWITCH) {
|
||||
if (es->bit_pos[es->num_bit_pos].rev_dir == NO_SWITCH) {
|
||||
fprintf(stderr, "#E rev routing switch %s -> %s not in model\n",
|
||||
to_str, from_str);
|
||||
FAIL(EINVAL);
|
||||
}
|
||||
} else
|
||||
es->mip[es->num_mips].rev_dir = NO_SWITCH;
|
||||
es->num_mips++;
|
||||
es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
|
||||
es->num_bit_pos++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -638,11 +640,11 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
|
|||
// turn switches into nets
|
||||
if (model->nets)
|
||||
HERE(); // should be empty here
|
||||
for (i = 0; i < es.num_sw_yx; i++) {
|
||||
for (i = 0; i < es.num_yx_pos; i++) {
|
||||
rc = fpga_net_new(model, &net_idx);
|
||||
if (rc) FAIL(rc);
|
||||
rc = fpga_net_add_sw(model, net_idx, es.sw_yx[i].y,
|
||||
es.sw_yx[i].x, &es.sw_yx[i].idx, 1);
|
||||
rc = fpga_net_add_sw(model, net_idx, es.yx_pos[i].y,
|
||||
es.yx_pos[i].x, &es.yx_pos[i].idx, 1);
|
||||
if (rc) FAIL(rc);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -650,7 +652,7 @@ fail:
|
|||
return rc;
|
||||
}
|
||||
|
||||
int printf_routing_mips(struct fpga_model* model)
|
||||
int printf_swbits(struct fpga_model* model)
|
||||
{
|
||||
struct extract_state es;
|
||||
char bit_str[129];
|
||||
|
|
@ -659,19 +661,19 @@ int printf_routing_mips(struct fpga_model* model)
|
|||
rc = construct_extract_state(&es, model);
|
||||
if (rc) FAIL(rc);
|
||||
bit_str[128] = 0;
|
||||
for (i = 0; i < es.num_mips; i++) {
|
||||
for (i = 0; i < es.num_bit_pos; i++) {
|
||||
for (j = 0; j < 128; j++)
|
||||
bit_str[j] = '0';
|
||||
if (es.mip[i].two_bits_val & 2)
|
||||
bit_str[es.mip[i].two_bits_o] = '1';
|
||||
if (es.mip[i].two_bits_val & 1)
|
||||
bit_str[es.mip[i].two_bits_o+1] = '1';
|
||||
bit_str[es.mip[i].one_bit_o] = '1';
|
||||
printf("mip%02i %s %s %s %s\n", es.mip[i].mip,
|
||||
fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.mip[i].uni_dir, SW_TO),
|
||||
if (es.bit_pos[i].two_bits_val & 2)
|
||||
bit_str[es.bit_pos[i].two_bits_o] = '1';
|
||||
if (es.bit_pos[i].two_bits_val & 1)
|
||||
bit_str[es.bit_pos[i].two_bits_o+1] = '1';
|
||||
bit_str[es.bit_pos[i].one_bit_o] = '1';
|
||||
printf("mi%02i %s %s %s %s\n", es.bit_pos[i].minor,
|
||||
fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.bit_pos[i].uni_dir, SW_TO),
|
||||
bit_str,
|
||||
fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.mip[i].uni_dir, SW_FROM),
|
||||
es.mip[i].rev_dir != NO_SWITCH ? "<->" : "->");
|
||||
fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.bit_pos[i].uni_dir, SW_FROM),
|
||||
es.bit_pos[i].rev_dir != NO_SWITCH ? "<->" : "->");
|
||||
}
|
||||
return 0;
|
||||
fail:
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user