suzanne.soy/fpgatools
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

switch cleanup

Browse Source
This commit is contained in:
Wolfgang Spraul 2012-09-13 03:35:16 +02:00
parent 0fa0e7f3c3
commit 279cd02600
6 changed files with 186 additions and 172 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -31,3 +31,4 @@ bit2fp.o
parts.o parts.o
autotest.tmp/ autotest.tmp/
autotest.out/ autotest.out/
compare.gold/

31
Makefile
View File

@ -148,22 +148,25 @@ libfpga-floorplan.a: $(LIBFPGA_FLOORPLAN_OBJS)
libfpga-control.a: $(LIBFPGA_CONTROL_OBJS) libfpga-control.a: $(LIBFPGA_CONTROL_OBJS)
$(AR) $@ $^ $(AR) $@ $^
xc6slx9_empty.fp: new_fp xc6slx9.fp: new_fp
./new_fp > $@ ./new_fp > $@
xc6slx9.svg: draw_svg_tiles xc6slx9.svg: draw_svg_tiles
./draw_svg_tiles | xmllint --pretty 1 - > $@ ./draw_svg_tiles | xmllint --pretty 1 - > $@
compare_all: compare.tiles compare.devs compare.conns compare.ports compare.sw compare_all: compare_tiles compare_devs compare_conns \
compare_ports compare_sw compare_swbits
compare.%: xc6slx9_empty.% compare_gold: compare.gold/xc6slx9.swbits
@comm -1 -2 $< compare_other.$* > compare_$*_matching.txt
compare_%: xc6slx9.%
@comm -1 -2 $< compare.gold/$< > compare_$*_matching.txt
@echo Matching lines - compare_$*_matching.txt: @echo Matching lines - compare_$*_matching.txt:
@cat compare_$*_matching.txt | wc -l @cat compare_$*_matching.txt | wc -l
@diff -u compare_other.$* $< > compare_$*_diff.txt || true @diff -u compare.gold/$< $< > compare_$*_diff.txt || true
@echo Missing lines - compare_$*_diff.txt @echo Missing lines - compare_$*_diff.txt
@cat compare_$*_diff.txt | grep ^-y | wc -l @cat compare_$*_diff.txt | grep ^-[^-] | wc -l
@cat compare_$*_diff.txt | grep ^+y > compare_$*_extra.txt || true @cat compare_$*_diff.txt | grep ^+[^+] > compare_$*_extra.txt || true
@if test -s compare_$*_extra.txt; then echo Extra lines - compare_$*_extra.txt: ; cat compare_$*_extra.txt; fi; @if test -s compare_$*_extra.txt; then echo Extra lines - compare_$*_extra.txt: ; cat compare_$*_extra.txt; fi;
%.tiles: %.fp %.tiles: %.fp
@ -190,6 +193,9 @@ compare.%: xc6slx9_empty.%
%.sw: %.fp %.sw: %.fp
@cat $<|awk '{if ($$1=="sw") printf "%s %s %s %s %s\n",$$2,$$3,$$4,$$5,$$6}'|sort >$@ @cat $<|awk '{if ($$1=="sw") printf "%s %s %s %s %s\n",$$2,$$3,$$4,$$5,$$6}'|sort >$@
%.swbits: bit2fp
./bit2fp --printf-swbits | sort > $@
clean: clean:
rm -f $(foreach test,$(TESTS),"autotest.out/autotest_$(test).diff_to_gold") rm -f $(foreach test,$(TESTS),"autotest.out/autotest_$(test).diff_to_gold")
rm -f $(foreach test,$(TESTS),"autotest.out/autotest_$(test).log") rm -f $(foreach test,$(TESTS),"autotest.out/autotest_$(test).log")
@ -206,17 +212,16 @@ clean:
bit2fp bit2fp.o \ bit2fp bit2fp.o \
pair2net pair2net.o \ pair2net pair2net.o \
libfpga-bit.a libfpga-control.a libfpga-cores.a libfpga-floorplan.a libfpga-model.a \ libfpga-bit.a libfpga-control.a libfpga-cores.a libfpga-floorplan.a libfpga-model.a \
xc6slx9_empty.fp xc6slx9.svg \ xc6slx9.fp xc6slx9.svg \
xc6slx9_empty.tiles xc6slx9_empty.devs xc6slx9_empty.conns \ xc6slx9.tiles xc6slx9.devs xc6slx9.conns \
xc6slx9_empty.ports xc6slx9_empty.sw xc6slx9_empty.cnets \ xc6slx9.ports xc6slx9.sw xc6slx9.cnets xc6slx9.swbits \
compare_other.tiles compare_other.devs compare_other.conns compare_other.ports \
compare_other.sw compare_other.cnets \
compare_tiles_matching.txt compare_tiles_diff.txt compare_tiles_extra.txt \ compare_tiles_matching.txt compare_tiles_diff.txt compare_tiles_extra.txt \
compare_devs_matching.txt compare_devs_diff.txt compare_devs_extra.txt \ compare_devs_matching.txt compare_devs_diff.txt compare_devs_extra.txt \
compare_conns_matching.txt compare_conns_diff.txt compare_conns_extra.txt \ compare_conns_matching.txt compare_conns_diff.txt compare_conns_extra.txt \
compare_ports_matching.txt compare_ports_diff.txt compare_ports_extra.txt \ compare_ports_matching.txt compare_ports_diff.txt compare_ports_extra.txt \
compare_sw_matching.txt compare_sw_diff.txt compare_sw_extra.txt \ compare_sw_matching.txt compare_sw_diff.txt compare_sw_extra.txt \
compare_cnets_matching.txt compare_cnets_diff.txt compare_cnets_extra.txt compare_cnets_matching.txt compare_cnets_diff.txt compare_cnets_extra.txt \
compare_swbits_matching.txt compare_swbits_diff.txt compare_swbits_extra.txt
install: all install: all
mkdir -p $(DESTDIR)/$(PREFIX)/bin/ mkdir -p $(DESTDIR)/$(PREFIX)/bin/

146
autotest.c
View File

@ -500,7 +500,9 @@ fail:
return rc; return rc;
} }
static int test_routing_sw_from_south(struct test_state* tstate, int test_routing_sw_from_iob(struct test_state* tstate,
swidx_t* done_list, int* done_list_len);
int test_routing_sw_from_iob(struct test_state* tstate,
swidx_t* done_list, int* done_list_len) swidx_t* done_list, int* done_list_len)
{ {
struct switch_to_yx switch_to; struct switch_to_yx switch_to;
@ -577,7 +579,7 @@ fail:
return rc; return rc;
} }
static int test_routing_sw_from_north(struct test_state* tstate, static int test_routing_sw_from_logic(struct test_state* tstate,
swidx_t* done_list, int* done_list_len) swidx_t* done_list, int* done_list_len)
{ {
struct fpga_device* dev; struct fpga_device* dev;
@ -585,79 +587,85 @@ static int test_routing_sw_from_north(struct test_state* tstate,
struct sw_conns conns; struct sw_conns conns;
const char* str; const char* str;
net_idx_t net; net_idx_t net;
int y, x, i, rc; int y, x, rel_y, i, rc;
y = 67; y = 67;
x = 13; x = 13;
for (i = '1'; i <= '6'; i++) {
rc = fdev_logic_set_lut(tstate->model, y, x, // We loop over this twice, once with rel_y==-1 and then with rel_y==+1
DEV_LOGM, LUT_A, 6, pf("A%c", i), ZTERM); // That way we come into the routing switchbox over the nr1/nl1 wires
if (rc) FAIL(rc); // from below, or sr1/sl1 wires from above.
rc = fdev_set_required_pins(tstate->model, y, x, for (rel_y = -1; rel_y <= 1; rel_y += 2) {
DEV_LOGIC, DEV_LOGM); for (i = '1'; i <= '6'; i++) {
if (rc) FAIL(rc); rc = fdev_logic_set_lut(tstate->model, y, x,
DEV_LOGM, LUT_A, 6, pf("A%c", i), ZTERM);
if (tstate->dry_run)
fdev_print_required_pins(tstate->model,
y, x, DEV_LOGIC, DEV_LOGM);
dev = fdev_p(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
if (!dev) FAIL(EINVAL);
if (!dev->pinw_req_in) FAIL(EINVAL);
rc = fpga_net_new(tstate->model, &net);
if (rc) FAIL(rc);
rc = fpga_net_add_port(tstate->model, net, y, x,
DEV_LOGIC, DEV_LOGM, dev->pinw_req_for_cfg[0]);
if (rc) FAIL(rc);
swto.model = tstate->model;
swto.start_y = y;
swto.start_x = x;
swto.start_switch = fdev_logic_pinstr_i(tstate->model,
dev->pinw_req_for_cfg[0]|LD1, LOGIC_M);
swto.from_to = SW_TO;
swto.rel_y = 0;
swto.rel_x = -1;
swto.target_connpt = STRIDX_NO_ENTRY;
rc = fpga_switch_to_rel(&swto);
if (rc) FAIL(rc);
if (!swto.set.len) FAIL(EINVAL);
if (tstate->dry_run)
printf_switch_to_rel_result(&swto);
rc = fpga_net_add_sw(tstate->model, net, swto.start_y,
swto.start_x, swto.set.sw, swto.set.len);
if (rc) FAIL(rc);
rc = construct_sw_conns(&conns, tstate->model, swto.dest_y, swto.dest_x,
swto.dest_connpt, SW_TO, /*max_depth*/ 1);
if (rc) FAIL(rc);
while (fpga_switch_conns(&conns) != NO_CONN) {
if (conns.dest_x != swto.dest_x
|| conns.dest_y != swto.dest_y+1)
continue;
str = strarray_lookup(&tstate->model->str, conns.dest_str_i);
if (!str) { HERE(); continue; }
if (strlen(str) < 5
|| str[2] != '1' || str[3] != 'B')
continue;
rc = fpga_net_add_sw(tstate->model, net, swto.dest_y,
swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
if (rc) FAIL(rc); if (rc) FAIL(rc);
rc = fdev_set_required_pins(tstate->model, y, x,
DEV_LOGIC, DEV_LOGM);
if (rc) FAIL(rc);
if (tstate->dry_run) if (tstate->dry_run)
fprintf_net(stdout, tstate->model, net); fdev_print_required_pins(tstate->model,
y, x, DEV_LOGIC, DEV_LOGM);
rc = test_switches(tstate, conns.dest_y, conns.dest_x, dev = fdev_p(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
conns.dest_str_i, net, done_list, done_list_len); if (!dev) FAIL(EINVAL);
if (!dev->pinw_req_in) FAIL(EINVAL);
rc = fpga_net_new(tstate->model, &net);
if (rc) FAIL(rc); if (rc) FAIL(rc);
rc = fpga_net_add_port(tstate->model, net, y, x,
rc = fpga_net_remove_sw(tstate->model, net, swto.dest_y, DEV_LOGIC, DEV_LOGM, dev->pinw_req_for_cfg[0]);
swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
if (rc) FAIL(rc); if (rc) FAIL(rc);
swto.model = tstate->model;
swto.start_y = y;
swto.start_x = x;
swto.start_switch = fdev_logic_pinstr_i(tstate->model,
dev->pinw_req_for_cfg[0]|LD1, LOGIC_M);
swto.from_to = SW_TO;
swto.rel_y = 0;
swto.rel_x = -1;
swto.target_connpt = STRIDX_NO_ENTRY;
rc = fpga_switch_to_rel(&swto);
if (rc) FAIL(rc);
if (!swto.set.len) FAIL(EINVAL);
if (tstate->dry_run)
printf_switch_to_rel_result(&swto);
rc = fpga_net_add_sw(tstate->model, net, swto.start_y,
swto.start_x, swto.set.sw, swto.set.len);
if (rc) FAIL(rc);
rc = construct_sw_conns(&conns, tstate->model, swto.dest_y, swto.dest_x,
swto.dest_connpt, SW_TO, /*max_depth*/ 1);
if (rc) FAIL(rc);
while (fpga_switch_conns(&conns) != NO_CONN) {
if (conns.dest_x != swto.dest_x
|| conns.dest_y != swto.dest_y+rel_y)
continue;
str = strarray_lookup(&tstate->model->str, conns.dest_str_i);
if (!str) { HERE(); continue; }
if (strlen(str) < 5
|| str[2] != '1' || str[3] != 'B')
continue;
rc = fpga_net_add_sw(tstate->model, net, swto.dest_y,
swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
if (rc) FAIL(rc);
if (tstate->dry_run)
fprintf_net(stdout, tstate->model, net);
rc = test_switches(tstate, conns.dest_y, conns.dest_x,
conns.dest_str_i, net, done_list, done_list_len);
if (rc) FAIL(rc);
rc = fpga_net_remove_sw(tstate->model, net, swto.dest_y,
swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
if (rc) FAIL(rc);
}
destruct_sw_conns(&conns);
fdev_delete(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
fpga_net_delete(tstate->model, net);
} }
destruct_sw_conns(&conns);
fdev_delete(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
fpga_net_delete(tstate->model, net);
} }
return 0; return 0;
fail: fail:
@ -744,9 +752,7 @@ static int test_routing_switches(struct test_state* tstate)
} }
} }
done_sw_len = 0; done_sw_len = 0;
rc = test_routing_sw_from_south(tstate, done_sw_list, &done_sw_len); rc = test_routing_sw_from_logic(tstate, done_sw_list, &done_sw_len);
if (rc) FAIL(rc);
rc = test_routing_sw_from_north(tstate, done_sw_list, &done_sw_len);
if (rc) FAIL(rc); if (rc) FAIL(rc);
return 0; return 0;
fail: fail:

2
bit.h
View File

@ -92,5 +92,5 @@ void free_config(struct fpga_config* cfg);
int write_bitfile(FILE* f, struct fpga_model* model); int write_bitfile(FILE* f, struct fpga_model* model);
int extract_model(struct fpga_model* model, struct fpga_bits* bits); int extract_model(struct fpga_model* model, struct fpga_bits* bits);
int printf_routing_mips(struct fpga_model* model); int printf_swbits(struct fpga_model* model);
int write_model(struct fpga_bits* bits, struct fpga_model* model); int write_model(struct fpga_bits* bits, struct fpga_model* model);

14
bit2fp.c
View File

@ -13,7 +13,7 @@ int main(int argc, char** argv)
{ {
struct fpga_model model; struct fpga_model model;
int bit_header, bit_regs, fp_header, pull_model, file_arg, flags; int bit_header, bit_regs, fp_header, pull_model, file_arg, flags;
int dump_routing_mips, rc = -1; int print_swbits, rc = -1;
struct fpga_config config; struct fpga_config config;
// parameters // parameters
@ -22,7 +22,7 @@ int main(int argc, char** argv)
"\n" "\n"
"%s - bitstream to floorplan\n" "%s - bitstream to floorplan\n"
"Usage: %s [--bit-header] [--bit-regs] [--no-model] [--no-fp-header]\n" "Usage: %s [--bit-header] [--bit-regs] [--no-model] [--no-fp-header]\n"
" %*s [--dump-routing-mips] <bitstream_file>\n" " %*s [--printf-swbits] <bitstream_file>\n"
"\n", argv[0], argv[0], (int) strlen(argv[0]), ""); "\n", argv[0], argv[0], (int) strlen(argv[0]), "");
goto fail; goto fail;
} }
@ -31,7 +31,7 @@ int main(int argc, char** argv)
pull_model = 1; pull_model = 1;
fp_header = 1; fp_header = 1;
file_arg = 1; file_arg = 1;
dump_routing_mips = 0; print_swbits = 0;
while (file_arg < argc while (file_arg < argc
&& !strncmp(argv[file_arg], "--", 2)) { && !strncmp(argv[file_arg], "--", 2)) {
if (!strcmp(argv[file_arg], "--bit-header")) if (!strcmp(argv[file_arg], "--bit-header"))
@ -42,8 +42,8 @@ int main(int argc, char** argv)
pull_model = 0; pull_model = 0;
else if (!strcmp(argv[file_arg], "--no-fp-header")) else if (!strcmp(argv[file_arg], "--no-fp-header"))
fp_header = 0; fp_header = 0;
else if (!strcmp(argv[file_arg], "--dump-routing-mips")) else if (!strcmp(argv[file_arg], "--printf-swbits"))
dump_routing_mips = 1; print_swbits = 1;
else break; else break;
file_arg++; file_arg++;
} }
@ -52,8 +52,8 @@ int main(int argc, char** argv)
if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS, if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING))) FAIL(rc); XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING))) FAIL(rc);
if (dump_routing_mips) { if (print_swbits) {
rc = printf_routing_mips(&model); rc = printf_swbits(&model);
if (rc) FAIL(rc); if (rc) FAIL(rc);
return 0; return 0;
} }

164
bit_frames.c
View File

@ -73,19 +73,26 @@ static struct bit_pos s_default_bits[] = {
{ 0, 1, 23, 1039 }, { 0, 1, 23, 1039 },
{ 2, 0, 3, 66 }}; { 2, 0, 3, 66 }};
// swpos_mip is relative to a tile, i.e. major (x) and // sw_bitpos is relative to a tile, i.e. major (x) and
// row/v64_i (y) are defined outside. // row/v64_i (y) are defined outside.
struct swpos_mip struct sw_bitpos
{ {
int mip; // 0-18, even only // minors 0-19 are minor pairs, minor will be set
int two_bits_o; // 0-127, even only // to the even beginning of the pair, two_bits_o and
// one_bit_o are within 2*64 bits of the two minors.
// Even bit offsets are from the first minor, odd bit
// offsets from the second minor.
// minor 20 is a regular single 64-bit minor.
int minor; // 0,2,4,..18 for pairs, 20 for single-minor
int two_bits_o; // 0-126 for pairs (even only), 0-62 for single-minor
int two_bits_val; // 0-3 int two_bits_val; // 0-3
int one_bit_o; // 0-127, 1-6 bits up or down from two-bit val int one_bit_o; // 1-6 positions up or down from two-bit pos
swidx_t uni_dir; swidx_t uni_dir;
swidx_t rev_dir; // NO_SWITCH for unidirectional switches swidx_t rev_dir; // NO_SWITCH for unidirectional switches
}; };
struct swpos_yx struct sw_yxpos
{ {
int y; int y;
int x; int x;
@ -98,12 +105,12 @@ struct extract_state
{ {
struct fpga_model* model; struct fpga_model* model;
struct fpga_bits* bits; struct fpga_bits* bits;
int num_mips; int num_bit_pos;
struct swpos_mip mip[MAX_SWITCHBOX_SIZE]; struct sw_bitpos bit_pos[MAX_SWITCHBOX_SIZE];
// yx switches are fully extracted ones pointing into the // yx switches are fully extracted ones pointing into the
// model, stored here for later processing into nets. // model, stored here for later processing into nets.
int num_sw_yx; int num_yx_pos;
struct swpos_yx sw_yx[MAX_YX_SWITCHES]; // needs to be dynamically alloced... struct sw_yxpos yx_pos[MAX_YX_SWITCHES]; // needs to be dynamically alloced...
}; };
static int extract_iobs(struct fpga_model* model, struct fpga_bits* bits) static int extract_iobs(struct fpga_model* model, struct fpga_bits* bits)
@ -315,7 +322,7 @@ fail:
} }
static int mip_is_set(struct extract_state* es, int y, int x, static int mip_is_set(struct extract_state* es, int y, int x,
struct swpos_mip* swpos, int* is_set) struct sw_bitpos* swpos, int* is_set)
{ {
int row_num, row_pos, start_in_frame, two_bits_val, rc; int row_num, row_pos, start_in_frame, two_bits_val, rc;
@ -329,15 +336,15 @@ static int mip_is_set(struct extract_state* es, int y, int x,
start_in_frame = row_pos*64; start_in_frame = row_pos*64;
two_bits_val = two_bits_val =
(get_bit(es->bits, row_num, es->model->x_major[x], swpos->mip, (get_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
start_in_frame + swpos->two_bits_o/2) << 1) start_in_frame + swpos->two_bits_o/2) << 1)
| (get_bit(es->bits, row_num, es->model->x_major[x], swpos->mip+1, | (get_bit(es->bits, row_num, es->model->x_major[x], swpos->minor+1,
start_in_frame + swpos->two_bits_o/2) << 2); start_in_frame + swpos->two_bits_o/2) << 2);
if (two_bits_val != swpos->two_bits_val) if (two_bits_val != swpos->two_bits_val)
return 0; return 0;
if (!get_bit(es->bits, row_num, es->model->x_major[x], if (!get_bit(es->bits, row_num, es->model->x_major[x],
swpos->mip + (swpos->one_bit_o&1), swpos->minor + (swpos->one_bit_o&1),
start_in_frame + swpos->one_bit_o/2)) start_in_frame + swpos->one_bit_o/2))
return 0; return 0;
*is_set = 1; *is_set = 1;
@ -347,7 +354,7 @@ fail:
} }
static int mip_clear_bits(struct extract_state* es, int y, int x, static int mip_clear_bits(struct extract_state* es, int y, int x,
struct swpos_mip* swpos) struct sw_bitpos* swpos)
{ {
int row_num, row_pos, start_in_frame, rc; int row_num, row_pos, start_in_frame, rc;
@ -359,11 +366,11 @@ static int mip_clear_bits(struct extract_state* es, int y, int x,
else else
start_in_frame = row_pos*64; start_in_frame = row_pos*64;
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->mip, clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
start_in_frame + swpos->two_bits_o/2); start_in_frame + swpos->two_bits_o/2);
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->mip + 1, clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor+ 1,
start_in_frame + swpos->two_bits_o/2); start_in_frame + swpos->two_bits_o/2);
clear_bit(es->bits, row_num, es->model->x_major[x], swpos->mip + (swpos->one_bit_o&1), clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor + (swpos->one_bit_o&1),
start_in_frame + swpos->one_bit_o/2); start_in_frame + swpos->one_bit_o/2);
return 0; return 0;
@ -379,27 +386,22 @@ static int extract_routing_switches(struct extract_state* es, int y, int x)
tile = YX_TILE(es->model, y, x); tile = YX_TILE(es->model, y, x);
if (y != 68 || x != 12) return 0; if (y != 68 || x != 12) return 0;
// build tile-relative model of all routing switches and for (i = 0; i < es->num_bit_pos; i++) {
// store in the extract state rc = mip_is_set(es, y, x, &es->bit_pos[i], &is_set);
if (!es->num_mips) {
}
for (i = 0; i < es->num_mips; i++) {
rc = mip_is_set(es, y, x, &es->mip[i], &is_set);
if (rc) FAIL(rc); if (rc) FAIL(rc);
if (!is_set) continue; if (!is_set) continue;
if (tile->switches[es->mip[i].uni_dir] & SWITCH_BIDIRECTIONAL) if (tile->switches[es->bit_pos[i].uni_dir] & SWITCH_BIDIRECTIONAL)
HERE(); HERE();
if (tile->switches[es->mip[i].uni_dir] & SWITCH_USED) if (tile->switches[es->bit_pos[i].uni_dir] & SWITCH_USED)
HERE(); HERE();
if (es->num_sw_yx >= MAX_YX_SWITCHES) if (es->num_yx_pos >= MAX_YX_SWITCHES)
{ FAIL(ENOTSUP); } { FAIL(ENOTSUP); }
es->sw_yx[es->num_sw_yx].y = y; es->yx_pos[es->num_yx_pos].y = y;
es->sw_yx[es->num_sw_yx].x = x; es->yx_pos[es->num_yx_pos].x = x;
es->sw_yx[es->num_sw_yx].idx = es->mip[i].uni_dir; es->yx_pos[es->num_yx_pos].idx = es->bit_pos[i].uni_dir;
es->num_sw_yx++; es->num_yx_pos++;
rc = mip_clear_bits(es, y, x, &es->mip[i]); rc = mip_clear_bits(es, y, x, &es->bit_pos[i]);
if (rc) FAIL(rc); if (rc) FAIL(rc);
} }
return 0; return 0;
@ -484,7 +486,7 @@ static int mod4_calc(int a, int b)
static int construct_extract_state(struct extract_state* es, struct fpga_model* model) static int construct_extract_state(struct extract_state* es, struct fpga_model* model)
{ {
char from_str[MAX_WIRENAME_LEN], to_str[MAX_WIRENAME_LEN]; char from_str[MAX_WIRENAME_LEN], to_str[MAX_WIRENAME_LEN];
int i, j, k, l, cur_mip, cur_two_bits_o, cur_two_bits_val, rc; int i, j, k, l, cur_pair_start, cur_two_bits_o, cur_two_bits_val, rc;
int logicin_i; int logicin_i;
memset(es, 0, sizeof(*es)); memset(es, 0, sizeof(*es));
@ -494,36 +496,36 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
// switches from logicout to dirwires (6*2*2*4*6=576 switches) // switches from logicout to dirwires (6*2*2*4*6=576 switches)
for (i = 0; i < DIRBEG_ROW; i++) { for (i = 0; i < DIRBEG_ROW; i++) {
cur_mip = (i/2)*2; cur_pair_start = (i/2)*2;
for (j = 0; j <= 3; j++) { // 4 wires for each dirwire for (j = 0; j <= 3; j++) { // 4 wires for each dirwire
for (k = 0; k <= 1; k++) { // two dirbeg rows for (k = 0; k <= 1; k++) { // two dirbeg rows
cur_two_bits_o = j*32 + k*16; cur_two_bits_o = j*32 + k*16;
if (i%2) cur_two_bits_o += 14; if (i%2) cur_two_bits_o += 14;
cur_two_bits_val = ((i%2)^k) ? 1 : 2; cur_two_bits_val = ((i%2)^k) ? 1 : 2;
for (l = 0; l < LOGOUT_ROW; l++) { for (l = 0; l < LOGOUT_ROW; l++) {
es->mip[es->num_mips].mip = cur_mip; es->bit_pos[es->num_bit_pos].minor = cur_pair_start;
es->mip[es->num_mips].two_bits_o = cur_two_bits_o; es->bit_pos[es->num_bit_pos].two_bits_o = cur_two_bits_o;
es->mip[es->num_mips].two_bits_val = cur_two_bits_val; es->bit_pos[es->num_bit_pos].two_bits_val = cur_two_bits_val;
es->mip[es->num_mips].one_bit_o = j*32+k*16+2+l*2; es->bit_pos[es->num_bit_pos].one_bit_o = j*32+k*16+2+l*2;
if (!((i%2)^k)) // right side (second minor) if (!((i%2)^k)) // right side (second minor)
es->mip[es->num_mips].one_bit_o++; es->bit_pos[es->num_bit_pos].one_bit_o++;
snprintf(from_str, sizeof(from_str), "LOGICOUT%i", logicout_matrix[j*LOGOUT_ROW + (k?5-l:l)]); snprintf(from_str, sizeof(from_str), "LOGICOUT%i", logicout_matrix[j*LOGOUT_ROW + (k?5-l:l)]);
snprintf(to_str, sizeof(to_str), "%sB%i", snprintf(to_str, sizeof(to_str), "%sB%i",
wire_base(dirbeg_matrix[k*DIRBEG_ROW+i]), mod4_calc(dirbeg_matrix_topnum[k*DIRBEG_ROW+i], -j)); wire_base(dirbeg_matrix[k*DIRBEG_ROW+i]), mod4_calc(dirbeg_matrix_topnum[k*DIRBEG_ROW+i], -j));
es->mip[es->num_mips].uni_dir = fpga_switch_lookup(es->model, es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
es->model->first_routing_y, es->model->first_routing_x, es->model->first_routing_y, es->model->first_routing_x,
strarray_find(&es->model->str, from_str), strarray_find(&es->model->str, from_str),
strarray_find(&es->model->str, to_str)); strarray_find(&es->model->str, to_str));
if (es->mip[es->num_mips].uni_dir == NO_SWITCH) { if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
fprintf(stderr, "#E routing switch %s -> %s not in model\n", fprintf(stderr, "#E routing switch %s -> %s not in model\n",
from_str, to_str); from_str, to_str);
FAIL(EINVAL); FAIL(EINVAL);
} }
es->mip[es->num_mips].rev_dir = NO_SWITCH; es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
es->num_mips++; es->num_bit_pos++;
} }
} }
} }
@ -535,42 +537,42 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
for (k = 0; k <= 1; k++) { // two switch destinations for (k = 0; k <= 1; k++) { // two switch destinations
// VCC // VCC
es->mip[es->num_mips].mip = i; es->bit_pos[es->num_bit_pos].minor = i;
es->mip[es->num_mips].two_bits_o = 32*j + (k?14:0); es->bit_pos[es->num_bit_pos].two_bits_o = 32*j + (k?14:0);
es->mip[es->num_mips].two_bits_val = 3; es->bit_pos[es->num_bit_pos].two_bits_val = 3;
es->mip[es->num_mips].one_bit_o = 32*j+2; es->bit_pos[es->num_bit_pos].one_bit_o = 32*j+2;
logicin_i = j*2*LOGIN_ROW + i-12 + k; logicin_i = j*2*LOGIN_ROW + i-12 + k;
if (i == 14 || i == 18) { if (i == 14 || i == 18) {
es->mip[es->num_mips].two_bits_o += 16; es->bit_pos[es->num_bit_pos].two_bits_o += 16;
es->mip[es->num_mips].one_bit_o += 16; es->bit_pos[es->num_bit_pos].one_bit_o += 16;
es->mip[es->num_mips].one_bit_o += !k; es->bit_pos[es->num_bit_pos].one_bit_o += !k;
logicin_i += LOGIN_ROW; logicin_i += LOGIN_ROW;
} else } else
es->mip[es->num_mips].one_bit_o += k; es->bit_pos[es->num_bit_pos].one_bit_o += k;
snprintf(to_str, sizeof(to_str), "LOGICIN_B%i", logicin_matrix[logicin_i]); snprintf(to_str, sizeof(to_str), "LOGICIN_B%i", logicin_matrix[logicin_i]);
es->mip[es->num_mips].uni_dir = fpga_switch_lookup(es->model, es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
es->model->first_routing_y, es->model->first_routing_x, es->model->first_routing_y, es->model->first_routing_x,
strarray_find(&es->model->str, "VCC_WIRE"), strarray_find(&es->model->str, "VCC_WIRE"),
strarray_find(&es->model->str, to_str)); strarray_find(&es->model->str, to_str));
if (es->mip[es->num_mips].uni_dir == NO_SWITCH) { if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
fprintf(stderr, "#E routing switch VCC_WIRE -> %s not in model\n", fprintf(stderr, "#E routing switch VCC_WIRE -> %s not in model\n",
to_str); to_str);
FAIL(EINVAL); FAIL(EINVAL);
} }
es->mip[es->num_mips].rev_dir = NO_SWITCH; es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
es->mip[es->num_mips+1] = es->mip[es->num_mips]; es->bit_pos[es->num_bit_pos+1] = es->bit_pos[es->num_bit_pos];
es->num_mips++; es->num_bit_pos++;
// GFAN // GFAN
if (i == 14 || i == 18) { if (i == 14 || i == 18) {
es->mip[es->num_mips].two_bits_o -= 16; es->bit_pos[es->num_bit_pos].two_bits_o -= 16;
es->mip[es->num_mips].one_bit_o -= 16; es->bit_pos[es->num_bit_pos].one_bit_o -= 16;
logicin_i -= LOGIN_ROW; logicin_i -= LOGIN_ROW;
} else { // 12 or 16 } else { // 12 or 16
es->mip[es->num_mips].two_bits_o += 16; es->bit_pos[es->num_bit_pos].two_bits_o += 16;
es->mip[es->num_mips].one_bit_o += 16; es->bit_pos[es->num_bit_pos].one_bit_o += 16;
logicin_i += LOGIN_ROW; logicin_i += LOGIN_ROW;
} }
snprintf(from_str, sizeof(from_str), "GFAN%i", j<2?1:0); snprintf(from_str, sizeof(from_str), "GFAN%i", j<2?1:0);
@ -578,11 +580,11 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
strcpy(to_str, "FAN_B"); strcpy(to_str, "FAN_B");
else else
snprintf(to_str, sizeof(to_str), "LOGICIN_B%i", logicin_matrix[logicin_i]); snprintf(to_str, sizeof(to_str), "LOGICIN_B%i", logicin_matrix[logicin_i]);
es->mip[es->num_mips].uni_dir = fpga_switch_lookup(es->model, es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
es->model->first_routing_y, es->model->first_routing_x, es->model->first_routing_y, es->model->first_routing_x,
strarray_find(&es->model->str, from_str), strarray_find(&es->model->str, from_str),
strarray_find(&es->model->str, to_str)); strarray_find(&es->model->str, to_str));
if (es->mip[es->num_mips].uni_dir == NO_SWITCH) { if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
fprintf(stderr, "#E routing switch %s -> %s not in model\n", fprintf(stderr, "#E routing switch %s -> %s not in model\n",
from_str, to_str); from_str, to_str);
FAIL(EINVAL); FAIL(EINVAL);
@ -593,18 +595,18 @@ static int construct_extract_state(struct extract_state* es, struct fpga_model*
|| logicin_matrix[logicin_i] == 35 || logicin_matrix[logicin_i] == 35
|| logicin_matrix[logicin_i] == 51 || logicin_matrix[logicin_i] == 51
|| logicin_matrix[logicin_i] == 53) { || logicin_matrix[logicin_i] == 53) {
es->mip[es->num_mips].rev_dir = fpga_switch_lookup(es->model, es->bit_pos[es->num_bit_pos].rev_dir = fpga_switch_lookup(es->model,
es->model->first_routing_y, es->model->first_routing_x, es->model->first_routing_y, es->model->first_routing_x,
strarray_find(&es->model->str, to_str), strarray_find(&es->model->str, to_str),
strarray_find(&es->model->str, from_str)); strarray_find(&es->model->str, from_str));
if (es->mip[es->num_mips].rev_dir == NO_SWITCH) { if (es->bit_pos[es->num_bit_pos].rev_dir == NO_SWITCH) {
fprintf(stderr, "#E rev routing switch %s -> %s not in model\n", fprintf(stderr, "#E rev routing switch %s -> %s not in model\n",
to_str, from_str); to_str, from_str);
FAIL(EINVAL); FAIL(EINVAL);
} }
} else } else
es->mip[es->num_mips].rev_dir = NO_SWITCH; es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
es->num_mips++; es->num_bit_pos++;
} }
} }
} }
@ -638,11 +640,11 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
// turn switches into nets // turn switches into nets
if (model->nets) if (model->nets)
HERE(); // should be empty here HERE(); // should be empty here
for (i = 0; i < es.num_sw_yx; i++) { for (i = 0; i < es.num_yx_pos; i++) {
rc = fpga_net_new(model, &net_idx); rc = fpga_net_new(model, &net_idx);
if (rc) FAIL(rc); if (rc) FAIL(rc);
rc = fpga_net_add_sw(model, net_idx, es.sw_yx[i].y, rc = fpga_net_add_sw(model, net_idx, es.yx_pos[i].y,
es.sw_yx[i].x, &es.sw_yx[i].idx, 1); es.yx_pos[i].x, &es.yx_pos[i].idx, 1);
if (rc) FAIL(rc); if (rc) FAIL(rc);
} }
return 0; return 0;
@ -650,7 +652,7 @@ fail:
return rc; return rc;
} }
int printf_routing_mips(struct fpga_model* model) int printf_swbits(struct fpga_model* model)
{ {
struct extract_state es; struct extract_state es;
char bit_str[129]; char bit_str[129];
@ -659,19 +661,19 @@ int printf_routing_mips(struct fpga_model* model)
rc = construct_extract_state(&es, model); rc = construct_extract_state(&es, model);
if (rc) FAIL(rc); if (rc) FAIL(rc);
bit_str[128] = 0; bit_str[128] = 0;
for (i = 0; i < es.num_mips; i++) { for (i = 0; i < es.num_bit_pos; i++) {
for (j = 0; j < 128; j++) for (j = 0; j < 128; j++)
bit_str[j] = '0'; bit_str[j] = '0';
if (es.mip[i].two_bits_val & 2) if (es.bit_pos[i].two_bits_val & 2)
bit_str[es.mip[i].two_bits_o] = '1'; bit_str[es.bit_pos[i].two_bits_o] = '1';
if (es.mip[i].two_bits_val & 1) if (es.bit_pos[i].two_bits_val & 1)
bit_str[es.mip[i].two_bits_o+1] = '1'; bit_str[es.bit_pos[i].two_bits_o+1] = '1';
bit_str[es.mip[i].one_bit_o] = '1'; bit_str[es.bit_pos[i].one_bit_o] = '1';
printf("mip%02i %s %s %s %s\n", es.mip[i].mip, printf("mi%02i %s %s %s %s\n", es.bit_pos[i].minor,
fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.mip[i].uni_dir, SW_TO), fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.bit_pos[i].uni_dir, SW_TO),
bit_str, bit_str,
fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.mip[i].uni_dir, SW_FROM), fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.bit_pos[i].uni_dir, SW_FROM),
es.mip[i].rev_dir != NO_SWITCH ? "<->" : "->"); es.bit_pos[i].rev_dir != NO_SWITCH ? "<->" : "->");
} }
return 0; return 0;
fail: fail: