moved switchbox to parts.c, cleanup
This commit is contained in:
Wolfgang Spraul
parent
4f51559aef
commit
2eeedfd5c8
704
bit_frames.c
704
bit_frames.c
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@ -73,25 +73,6 @@ static struct bit_pos s_default_bits[] = {
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{ 0, 1, 23, 1039 },
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{ 0, 1, 23, 1039 },
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{ 2, 0, 3, 66 }};
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{ 2, 0, 3, 66 }};
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// sw_bitpos is relative to a tile, i.e. major (x) and
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// row/v64_i (y) are defined outside.
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struct sw_bitpos
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{
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// minors 0-19 are minor pairs, minor will be set
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// to the even beginning of the pair, two_bits_o and
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// one_bit_o are within 2*64 bits of the two minors.
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// Even bit offsets are from the first minor, odd bit
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// offsets from the second minor.
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// minor 20 is a regular single 64-bit minor.
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int minor; // 0,2,4,..18 for pairs, 20 for single-minor
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int two_bits_o; // 0-126 for pairs (even only), 0-62 for single-minor
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int two_bits_val; // 0-3
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int one_bit_o; // 1-6 positions up or down from two-bit pos
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swidx_t uni_dir;
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swidx_t rev_dir; // NO_SWITCH for unidirectional switches
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};
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struct sw_yxpos
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struct sw_yxpos
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{
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{
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int y;
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int y;
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@ -105,8 +86,6 @@ struct extract_state
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{
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{
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struct fpga_model* model;
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struct fpga_model* model;
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struct fpga_bits* bits;
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struct fpga_bits* bits;
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int num_bit_pos;
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struct sw_bitpos bit_pos[MAX_SWITCHBOX_SIZE];
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// yx switches are fully extracted ones pointing into the
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// yx switches are fully extracted ones pointing into the
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// model, stored here for later processing into nets.
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// model, stored here for later processing into nets.
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int num_yx_pos;
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int num_yx_pos;
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@ -322,11 +301,10 @@ fail:
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}
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}
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static int bitpos_is_set(struct extract_state* es, int y, int x,
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static int bitpos_is_set(struct extract_state* es, int y, int x,
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struct sw_bitpos* swpos, int* is_set)
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struct xc6_routing_bitpos* swpos, int* is_set)
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{
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{
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int row_num, row_pos, start_in_frame, two_bits_val, rc;
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int row_num, row_pos, start_in_frame, two_bits_val, rc;
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// TODO: does not support minor20 correctly
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*is_set = 0;
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*is_set = 0;
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is_in_row(es->model, y, &row_num, &row_pos);
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is_in_row(es->model, y, &row_num, &row_pos);
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if (row_num == -1 || row_pos == -1
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if (row_num == -1 || row_pos == -1
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@ -336,6 +314,18 @@ static int bitpos_is_set(struct extract_state* es, int y, int x,
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else
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else
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start_in_frame = row_pos*64;
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start_in_frame = row_pos*64;
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if (swpos->minor == 20) {
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two_bits_val = (get_bit(es->bits, row_num, es->model->x_major[x],
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20, start_in_frame + swpos->two_bits_o) << 1)
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| (get_bit(es->bits, row_num, es->model->x_major[x],
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20, start_in_frame + swpos->two_bits_o+1) << 2);
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if (two_bits_val != swpos->two_bits_val)
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return 0;
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if (!get_bit(es->bits, row_num, es->model->x_major[x], 20,
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start_in_frame + swpos->one_bit_o))
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return 0;
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} else {
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two_bits_val =
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two_bits_val =
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(get_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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(get_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->two_bits_o/2) << 1)
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start_in_frame + swpos->two_bits_o/2) << 1)
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@ -348,6 +338,7 @@ static int bitpos_is_set(struct extract_state* es, int y, int x,
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swpos->minor + (swpos->one_bit_o&1),
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swpos->minor + (swpos->one_bit_o&1),
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start_in_frame + swpos->one_bit_o/2))
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start_in_frame + swpos->one_bit_o/2))
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return 0;
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return 0;
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}
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*is_set = 1;
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*is_set = 1;
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return 0;
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return 0;
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fail:
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fail:
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@ -355,11 +346,10 @@ fail:
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}
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}
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static int bitpos_clear_bits(struct extract_state* es, int y, int x,
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static int bitpos_clear_bits(struct extract_state* es, int y, int x,
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struct sw_bitpos* swpos)
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struct xc6_routing_bitpos* swpos)
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{
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{
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int row_num, row_pos, start_in_frame, rc;
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int row_num, row_pos, start_in_frame, rc;
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// TODO: does not support minor20 correctly
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is_in_row(es->model, y, &row_num, &row_pos);
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is_in_row(es->model, y, &row_num, &row_pos);
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if (row_num == -1 || row_pos == -1
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if (row_num == -1 || row_pos == -1
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|| row_pos == HCLK_POS) FAIL(EINVAL);
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|| row_pos == HCLK_POS) FAIL(EINVAL);
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@ -368,13 +358,21 @@ static int bitpos_clear_bits(struct extract_state* es, int y, int x,
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else
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else
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start_in_frame = row_pos*64;
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start_in_frame = row_pos*64;
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if (swpos->minor == 20) {
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->two_bits_o);
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->two_bits_o+1);
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->one_bit_o);
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} else {
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->two_bits_o/2);
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start_in_frame + swpos->two_bits_o/2);
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor + 1,
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor + 1,
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start_in_frame + swpos->two_bits_o/2);
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start_in_frame + swpos->two_bits_o/2);
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor + (swpos->one_bit_o&1),
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor + (swpos->one_bit_o&1),
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start_in_frame + swpos->one_bit_o/2);
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start_in_frame + swpos->one_bit_o/2);
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}
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return 0;
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return 0;
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fail:
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fail:
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return rc;
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return rc;
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@ -383,27 +381,34 @@ fail:
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static int extract_routing_switches(struct extract_state* es, int y, int x)
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static int extract_routing_switches(struct extract_state* es, int y, int x)
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{
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{
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struct fpga_tile* tile;
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struct fpga_tile* tile;
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swidx_t sw_idx;
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int i, is_set, rc;
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int i, is_set, rc;
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tile = YX_TILE(es->model, y, x);
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tile = YX_TILE(es->model, y, x);
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if (y != 68 || x != 12) return 0;
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if (y != 68 || x != 12) return 0;
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for (i = 0; i < es->num_bit_pos; i++) {
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for (i = 0; i < es->model->num_bitpos; i++) {
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rc = bitpos_is_set(es, y, x, &es->bit_pos[i], &is_set);
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rc = bitpos_is_set(es, y, x, &es->model->sw_bitpos[i], &is_set);
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if (rc) FAIL(rc);
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if (rc) FAIL(rc);
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if (!is_set) continue;
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if (!is_set) continue;
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if (tile->switches[es->bit_pos[i].uni_dir] & SWITCH_BIDIRECTIONAL)
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sw_idx = fpga_switch_lookup(es->model, y, x,
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fpga_wirestr_i(es->model, es->model->sw_bitpos[i].from),
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fpga_wirestr_i(es->model, es->model->sw_bitpos[i].to));
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if (sw_idx == NO_SWITCH) FAIL(EINVAL);
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// todo: es->model->sw_bitpos[i].bidir handling
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if (tile->switches[sw_idx] & SWITCH_BIDIRECTIONAL)
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HERE();
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HERE();
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if (tile->switches[es->bit_pos[i].uni_dir] & SWITCH_USED)
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if (tile->switches[sw_idx] & SWITCH_USED)
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HERE();
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HERE();
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if (es->num_yx_pos >= MAX_YX_SWITCHES)
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if (es->num_yx_pos >= MAX_YX_SWITCHES)
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{ FAIL(ENOTSUP); }
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{ FAIL(ENOTSUP); }
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es->yx_pos[es->num_yx_pos].y = y;
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es->yx_pos[es->num_yx_pos].y = y;
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es->yx_pos[es->num_yx_pos].x = x;
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es->yx_pos[es->num_yx_pos].x = x;
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es->yx_pos[es->num_yx_pos].idx = es->bit_pos[i].uni_dir;
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es->yx_pos[es->num_yx_pos].idx = sw_idx;
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es->num_yx_pos++;
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es->num_yx_pos++;
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rc = bitpos_clear_bits(es, y, x, &es->bit_pos[i]);
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rc = bitpos_clear_bits(es, y, x, &es->model->sw_bitpos[i]);
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if (rc) FAIL(rc);
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if (rc) FAIL(rc);
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}
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}
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return 0;
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return 0;
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@ -427,13 +432,6 @@ static int extract_switches(struct extract_state* es)
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rc = extract_routing_switches(es, y, x);
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rc = extract_routing_switches(es, y, x);
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if (rc) FAIL(rc);
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if (rc) FAIL(rc);
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}
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}
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#if 0
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// when all switches are supported, we can turn this
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// on to make the model more robust
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if (tile->num_switches)
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fprintf(stderr, "%i unsupported switches in y%02i x%02i\n",
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tile->num_switches, y, x);
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#endif
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}
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}
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}
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}
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return 0;
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return 0;
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@ -441,618 +439,14 @@ fail:
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return rc;
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return rc;
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}
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}
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#define LOGIN_ROW 2
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#define LOGIN_MIP_ROWS 8
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static const int logicin_matrix[] =
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{
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/*mip 12*/
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/* 000 */ LW + (LI_C6|LD1), LW + LI_D6,
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/* 016 */ LW + (LI_B1|LD1), LW + (LI_DI|LD1),
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/* 032 */ LW + (LI_C5|LD1), LW + LI_D5,
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/* 048 */ LW + (LI_CI|LD1), LW + LI_A2,
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/* 064 */ LW + (LI_C4|LD1), LW + LI_D4,
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/* 080 */ LW + LI_A1, LW + LI_CE,
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/* 096 */ LW + (LI_C3|LD1), LW + LI_D3,
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/* 112 */ LW + (LI_B2|LD1), LW + (LI_WE|LD1),
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/*mip 14*/
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/* 000 */ LW + LI_C1, LW + LI_DX,
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/* 016 */ LW + (LI_A3|LD1), LW + LI_B3,
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/* 032 */ LW + (LI_CX|LD1), LW + (LI_D2|LD1),
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/* 048 */ LW + (LI_A4|LD1), LW + LI_B4,
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/* 064 */ LW + (LI_D1|LD1), LW + LI_BX,
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/* 080 */ LW + (LI_A5|LD1), LW + LI_B5,
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/* 096 */ LW + (LI_AX|LD1), LW + LI_C2,
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/* 112 */ LW + (LI_A6|LD1), LW + LI_B6,
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/*mip 16*/
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/* 000 */ LW + (LI_B3|LD1), LW + LI_A3,
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/* 016 */ LW + (LI_C2|LD1), LW + (LI_DX|LD1),
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/* 032 */ LW + (LI_B4|LD1), LW + LI_A4,
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/* 048 */ LW + LI_CX, LW + LI_D1,
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/* 064 */ LW + (LI_B5|LD1), LW + LI_A5,
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/* 080 */ LW + (LI_BX|LD1), LW + LI_D2,
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/* 096 */ LW + (LI_B6|LD1), LW + LI_A6,
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/* 112 */ LW + (LI_C1|LD1), LW + LI_AX,
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/*mip 18*/
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/* 000 */ LW + LI_B2, FAN_B,
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/* 016 */ LW + (LI_D6|LD1), LW + LI_C6,
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/* 032 */ LW + (LI_A1|LD1), LW + (LI_CE|LD1),
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/* 048 */ LW + (LI_D5|LD1), LW + LI_C5,
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/* 064 */ LW + (LI_A2|LD1), LW + (LI_BI|LD1),
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/* 080 */ LW + (LI_D4|LD1), LW + LI_C4,
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/* 096 */ LW + (LI_AI|LD1), LW + LI_B1,
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/* 112 */ LW + (LI_D3|LD1), LW + LI_C3
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};
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struct sw_mip_src
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{
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int minor;
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int m0_sw_to;
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int m0_two_bits_o;
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int m0_two_bits_val;
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int m0_one_bit_start;
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int m1_sw_to;
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int m1_two_bits_o;
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int m1_two_bits_val;
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int m1_one_bit_start;
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int src_wire[6];
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};
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struct sw_mi20_src
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{
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int sw_to;
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int two_bits_o;
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int two_bits_val;
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int one_bit_start;
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int src_wire[6];
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};
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static int add_bitpos(struct extract_state* es, int minor, int sw_to, int two_bits_o,
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int two_bits_val, int one_bit_o, int sw_from)
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{
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// the first member of bidir switch pairs is where the bits reside
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static const int bidir[] = {
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LW + (LI_BX|LD1), FAN_B,
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LW + (LI_AX|LD1), GFAN0,
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LW + LI_AX, GFAN0,
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LW + (LI_CE|LD1), GFAN1,
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LW + (LI_CI|LD1), GFAN1,
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LW + LI_BX, LW + (LI_CI|LD1),
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LW + LI_BX, LW + (LI_DI|LD1),
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LW + (LI_AX|LD1), LW + (LI_CI|LD1),
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LW + (LI_BX|LD1), LW + (LI_CE|LD1),
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LW + LI_AX, LW + (LI_CE|LD1) };
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int i, rc;
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// bidirectional switches are ignored on one side, and
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// marked as bidir on the other side
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for (i = 0; i < sizeof(bidir)/sizeof(*bidir)/2; i++) {
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if (sw_from == bidir[i*2] && sw_to == bidir[i*2+1])
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// nothing to do where no bits reside
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return 0;
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}
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es->bit_pos[es->num_bit_pos].minor = minor,
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es->bit_pos[es->num_bit_pos].two_bits_o = two_bits_o;
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es->bit_pos[es->num_bit_pos].two_bits_val = two_bits_val;
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es->bit_pos[es->num_bit_pos].one_bit_o = one_bit_o;
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es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
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es->model->first_routing_y, es->model->first_routing_x,
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fpga_wirestr_i(es->model, sw_from),
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fpga_wirestr_i(es->model, sw_to));
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if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
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fprintf(stderr, "#E routing switch %s -> %s not in model\n",
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fpga_wirestr(es->model, sw_from),
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fpga_wirestr(es->model, sw_to));
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FAIL(EINVAL);
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}
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es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
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for (i = 0; i < sizeof(bidir)/sizeof(*bidir)/2; i++) {
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if (sw_from == bidir[i*2+1] && sw_to == bidir[i*2]) {
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es->bit_pos[es->num_bit_pos].rev_dir = fpga_switch_lookup(es->model,
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||||||
es->model->first_routing_y, es->model->first_routing_x,
|
|
||||||
fpga_wirestr_i(es->model, sw_to),
|
|
||||||
fpga_wirestr_i(es->model, sw_from));
|
|
||||||
if (es->bit_pos[es->num_bit_pos].rev_dir == NO_SWITCH) {
|
|
||||||
fprintf(stderr, "#E reverse routing switch %s -> %s not in model\n",
|
|
||||||
fpga_wirestr(es->model, sw_to),
|
|
||||||
fpga_wirestr(es->model, sw_from));
|
|
||||||
FAIL(EINVAL);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
es->num_bit_pos++;
|
|
||||||
return 0;
|
|
||||||
fail:
|
|
||||||
return rc;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int src_to_bitpos(struct extract_state* es, const struct sw_mip_src* src, int src_len)
|
|
||||||
{
|
|
||||||
int i, j, rc;
|
|
||||||
|
|
||||||
for (i = 0; i < src_len; i++) {
|
|
||||||
for (j = 0; j < sizeof(src->src_wire)/sizeof(src->src_wire[0]); j++) {
|
|
||||||
if (src[i].src_wire[j] == NO_WIRE) continue;
|
|
||||||
|
|
||||||
rc = add_bitpos(es, src[i].minor, src[i].m0_sw_to,
|
|
||||||
src[i].m0_two_bits_o, src[i].m0_two_bits_val,
|
|
||||||
src[i].m0_one_bit_start + j*2, src[i].src_wire[j]);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
rc = add_bitpos(es, src[i].minor, src[i].m1_sw_to,
|
|
||||||
src[i].m1_two_bits_o, src[i].m1_two_bits_val,
|
|
||||||
src[i].m1_one_bit_start + j*2, src[i].src_wire[j]);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
fail:
|
|
||||||
return rc;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int wire_decrement(int wire)
|
|
||||||
{
|
|
||||||
int _wire, flags;
|
|
||||||
|
|
||||||
if (wire >= DW && wire <= DW_LAST) {
|
|
||||||
_wire = wire - DW;
|
|
||||||
flags = _wire & DIR_FLAGS;
|
|
||||||
_wire &= ~DIR_FLAGS;
|
|
||||||
|
|
||||||
if (_wire%4 == 0)
|
|
||||||
return DW + ((_wire + 3) | flags);
|
|
||||||
return DW + ((_wire - 1) | flags);
|
|
||||||
}
|
|
||||||
if (wire >= LW && wire <= LW_LAST) {
|
|
||||||
_wire = wire - LW;
|
|
||||||
flags = _wire & LD1;
|
|
||||||
_wire &= ~LD1;
|
|
||||||
|
|
||||||
if (_wire == LO_A)
|
|
||||||
return LW + (LO_D|flags);
|
|
||||||
if (_wire == LO_AMUX)
|
|
||||||
return LW + (LO_DMUX|flags);
|
|
||||||
if (_wire == LO_AQ)
|
|
||||||
return LW + (LO_DQ|flags);
|
|
||||||
if ((_wire >= LO_B && _wire <= LO_D)
|
|
||||||
|| (_wire >= LO_BMUX && _wire <= LO_DMUX)
|
|
||||||
|| (_wire >= LO_BQ && _wire <= LO_DQ))
|
|
||||||
return LW + ((_wire-1)|flags);
|
|
||||||
}
|
|
||||||
if (wire == NO_WIRE) return wire;
|
|
||||||
HERE();
|
|
||||||
return wire;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int mip_to_bitpos(struct extract_state* es, int minor, int m0_two_bits_val,
|
|
||||||
int m0_one_bit_start, int m1_two_bits_val, int m1_one_bit_start, int (*src_wires)[8][6])
|
|
||||||
{
|
|
||||||
struct sw_mip_src src;
|
|
||||||
int i, j, rc;
|
|
||||||
|
|
||||||
src.minor = minor;
|
|
||||||
src.m0_two_bits_o = 0;
|
|
||||||
src.m0_two_bits_val = m0_two_bits_val;
|
|
||||||
src.m0_one_bit_start = m0_one_bit_start;
|
|
||||||
src.m1_two_bits_o = 14;
|
|
||||||
src.m1_two_bits_val = m1_two_bits_val;
|
|
||||||
src.m1_one_bit_start = m1_one_bit_start;
|
|
||||||
for (i = 0; i < 8; i++) {
|
|
||||||
int logicin_o = ((src.minor-12)/2)*LOGIN_MIP_ROWS*LOGIN_ROW;
|
|
||||||
logicin_o += i*LOGIN_ROW;
|
|
||||||
src.m0_sw_to = logicin_matrix[logicin_o+0];
|
|
||||||
src.m1_sw_to = logicin_matrix[logicin_o+1];
|
|
||||||
if (i) {
|
|
||||||
src.m0_two_bits_o += 16;
|
|
||||||
src.m0_one_bit_start += 16;
|
|
||||||
src.m1_two_bits_o += 16;
|
|
||||||
src.m1_one_bit_start += 16;
|
|
||||||
}
|
|
||||||
for (j = 0; j < sizeof(src.src_wire)/sizeof(src.src_wire[0]); j++)
|
|
||||||
src.src_wire[j] = (*src_wires)[i][j];
|
|
||||||
|
|
||||||
rc = src_to_bitpos(es, &src, /*src_len*/ 1);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
fail:
|
|
||||||
return rc;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int construct_extract_state(struct extract_state* es, struct fpga_model* model)
|
static int construct_extract_state(struct extract_state* es, struct fpga_model* model)
|
||||||
{
|
{
|
||||||
int i, j, k, rc;
|
int rc;
|
||||||
|
|
||||||
memset(es, 0, sizeof(*es));
|
memset(es, 0, sizeof(*es));
|
||||||
es->model = model;
|
es->model = model;
|
||||||
if (model->first_routing_y == -1)
|
if (model->first_routing_y == -1)
|
||||||
FAIL(EINVAL);
|
FAIL(EINVAL);
|
||||||
|
|
||||||
// mip 0-10 (6*288=1728 switches)
|
|
||||||
{ struct sw_mip_src src[] = {
|
|
||||||
{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 2, 3,
|
|
||||||
DW + ((W_NW4*4+3) | DIR_BEG), 14, 1, 2,
|
|
||||||
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
|
||||||
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
|
||||||
{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 1, 3,
|
|
||||||
DW + ((W_NW4*4+3) | DIR_BEG), 14, 2, 2,
|
|
||||||
{DW + ((W_SW2*4+2)|DIR_N3), DW + ((W_SS2*4+2)|DIR_N3), DW + ((W_WW2*4+2)|DIR_N3),
|
|
||||||
DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_NW2*4+3}},
|
|
||||||
{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 0, 3,
|
|
||||||
DW + ((W_NW4*4+3) | DIR_BEG), 14, 0, 2,
|
|
||||||
{DW + ((W_SW4*4+2)|DIR_N3), DW + ((W_SS4*4+2)|DIR_N3), DW + W_NE4*4+3,
|
|
||||||
DW + W_NN4*4+3, DW + W_NW4*4+3, DW + W_WW4*4+3}},
|
|
||||||
{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 2, 18,
|
|
||||||
DW + ((W_SW4*4+3) | DIR_BEG), 30, 1, 19,
|
|
||||||
{DW + W_SW2*4+3, DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0),
|
|
||||||
DW + W_SS2*4+3, DW + W_SE2*4+3, DW + W_EE2*4+3}},
|
|
||||||
{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 1, 18,
|
|
||||||
DW + ((W_SW4*4+3) | DIR_BEG), 30, 2, 19,
|
|
||||||
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
|
||||||
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
|
||||||
{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 0, 18,
|
|
||||||
DW + ((W_SW4*4+3) | DIR_BEG), 30, 0, 19,
|
|
||||||
{DW + W_SW4*4+3, DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0),
|
|
||||||
DW + ((W_NW4*4+0)|DIR_S0), DW + W_SE4*4+3, DW + W_EE4*4+3}},
|
|
||||||
|
|
||||||
{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 2, 3,
|
|
||||||
DW + ((W_NE4*4+3) | DIR_BEG), 14, 1, 2,
|
|
||||||
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
|
||||||
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
|
||||||
{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 1, 3,
|
|
||||||
DW + ((W_NE4*4+3) | DIR_BEG), 14, 2, 2,
|
|
||||||
{DW + W_EE2*4+3, DW + W_SE2*4+3, DW + ((W_WW2*4+2)|DIR_N3),
|
|
||||||
DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_NW2*4+3}},
|
|
||||||
{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 0, 3,
|
|
||||||
DW + ((W_NE4*4+3) | DIR_BEG), 14, 0, 2,
|
|
||||||
{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
|
|
||||||
DW + W_NN4*4+3, DW + W_NW4*4+3, DW + W_WW4*4+3}},
|
|
||||||
{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 2, 18,
|
|
||||||
DW + ((W_SE4*4+3) | DIR_BEG), 30, 1, 19,
|
|
||||||
{DW + W_SW2*4+3, DW + W_NN2*4+3, DW + W_NE2*4+3,
|
|
||||||
DW + W_SS2*4+3, DW + W_SE2*4+3, DW + W_EE2*4+3}},
|
|
||||||
{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 1, 18,
|
|
||||||
DW + ((W_SE4*4+3) | DIR_BEG), 30, 2, 19,
|
|
||||||
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
|
||||||
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
|
||||||
{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 0, 18,
|
|
||||||
DW + ((W_SE4*4+3) | DIR_BEG), 30, 0, 19,
|
|
||||||
{DW + W_SW4*4+3, DW + W_SS4*4+3, DW + W_NN4*4+3,
|
|
||||||
DW + W_NE4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}},
|
|
||||||
|
|
||||||
{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 2, 3,
|
|
||||||
DW + ((W_NN2*4+3) | DIR_BEG), 14, 1, 2,
|
|
||||||
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
|
||||||
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
|
||||||
{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 1, 3,
|
|
||||||
DW + ((W_NN2*4+3) | DIR_BEG), 14, 2, 2,
|
|
||||||
{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + ((W_WL1*4+2)|DIR_N3),
|
|
||||||
DW + W_WR1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
|
|
||||||
{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 0, 3,
|
|
||||||
DW + ((W_NN2*4+3) | DIR_BEG), 14, 0, 2,
|
|
||||||
{DW + W_NW4*4+3, DW + W_WW4*4+3, DW + W_NE4*4+3,
|
|
||||||
DW + W_NN4*4+3, DW + ((W_WW2*4+2)|DIR_N3), DW + W_NW2*4+3}},
|
|
||||||
{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 2, 18,
|
|
||||||
DW + ((W_SW2*4+3) | DIR_BEG), 30, 1, 19,
|
|
||||||
{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + ((W_WR1*4+0)|DIR_S0),
|
|
||||||
DW + W_WL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
|
|
||||||
{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 1, 18,
|
|
||||||
DW + ((W_SW2*4+3) | DIR_BEG), 30, 2, 19,
|
|
||||||
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
|
||||||
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
|
||||||
{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 0, 18,
|
|
||||||
DW + ((W_SW2*4+3) | DIR_BEG), 30, 0, 19,
|
|
||||||
{DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0), DW + W_SW4*4+3,
|
|
||||||
DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0), DW + ((W_NW4*4+0)|DIR_S0)}},
|
|
||||||
|
|
||||||
{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 2, 3,
|
|
||||||
DW + ((W_EE2*4+3) | DIR_BEG), 14, 1, 2,
|
|
||||||
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
|
||||||
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
|
||||||
{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 1, 3,
|
|
||||||
DW + ((W_EE2*4+3) | DIR_BEG), 14, 2, 2,
|
|
||||||
{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_EL1*4+3,
|
|
||||||
DW + W_ER1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
|
|
||||||
{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 0, 3,
|
|
||||||
DW + ((W_EE2*4+3) | DIR_BEG), 14, 0, 2,
|
|
||||||
{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
|
|
||||||
DW + W_NN4*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
|
||||||
{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 2, 18,
|
|
||||||
DW + ((W_SE2*4+3) | DIR_BEG), 30, 1, 19,
|
|
||||||
{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + W_ER1*4+3,
|
|
||||||
DW + W_EL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
|
|
||||||
{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 1, 18,
|
|
||||||
DW + ((W_SE2*4+3) | DIR_BEG), 30, 2, 19,
|
|
||||||
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
|
||||||
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
|
||||||
{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 0, 18,
|
|
||||||
DW + ((W_SE2*4+3) | DIR_BEG), 30, 0, 19,
|
|
||||||
{DW + W_SE2*4+3, DW + W_EE2*4+3, DW + W_SW4*4+3,
|
|
||||||
DW + W_SS4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}},
|
|
||||||
|
|
||||||
{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 2, 3,
|
|
||||||
DW + ((W_NL1*4+2) | DIR_BEG), 14, 1, 2,
|
|
||||||
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
|
||||||
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
|
||||||
{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 1, 3,
|
|
||||||
DW + ((W_NL1*4+2) | DIR_BEG), 14, 2, 2,
|
|
||||||
{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + ((W_WL1*4+2)|DIR_N3),
|
|
||||||
DW + W_WR1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
|
|
||||||
{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 0, 3,
|
|
||||||
DW + ((W_NL1*4+2) | DIR_BEG), 14, 0, 2,
|
|
||||||
{DW + W_NW4*4+3, DW + W_WW4*4+3, DW + W_NE4*4+3,
|
|
||||||
DW + W_NN4*4+3, DW + ((W_WW2*4+2)|DIR_N3), DW + W_NW2*4+3}},
|
|
||||||
{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 2, 18,
|
|
||||||
DW + ((W_WL1*4+2) | DIR_BEG), 30, 1, 19,
|
|
||||||
{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + ((W_WR1*4+0)|DIR_S0),
|
|
||||||
DW + W_WL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
|
|
||||||
{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 1, 18,
|
|
||||||
DW + ((W_WL1*4+2) | DIR_BEG), 30, 2, 19,
|
|
||||||
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
|
||||||
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
|
||||||
{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 0, 18,
|
|
||||||
DW + ((W_WL1*4+2) | DIR_BEG), 30, 0, 19,
|
|
||||||
{DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0), DW + W_SW4*4+3,
|
|
||||||
DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0), DW + ((W_NW4*4+0)|DIR_S0)}},
|
|
||||||
|
|
||||||
{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 2, 3,
|
|
||||||
DW + ((W_NR1*4+3) | DIR_BEG), 14, 1, 2,
|
|
||||||
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
|
||||||
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
|
||||||
{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 1, 3,
|
|
||||||
DW + ((W_NR1*4+3) | DIR_BEG), 14, 2, 2,
|
|
||||||
{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_EL1*4+3,
|
|
||||||
DW + W_ER1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
|
|
||||||
{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 0, 3,
|
|
||||||
DW + ((W_NR1*4+3) | DIR_BEG), 14, 0, 2,
|
|
||||||
{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
|
|
||||||
DW + W_NN4*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
|
||||||
{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 2, 18,
|
|
||||||
DW + ((W_ER1*4+0) | DIR_BEG), 30, 1, 19,
|
|
||||||
{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + W_ER1*4+3,
|
|
||||||
DW + W_EL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
|
|
||||||
{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 1, 18,
|
|
||||||
DW + ((W_ER1*4+0) | DIR_BEG), 30, 2, 19,
|
|
||||||
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
|
||||||
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
|
||||||
{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 0, 18,
|
|
||||||
DW + ((W_ER1*4+0) | DIR_BEG), 30, 0, 19,
|
|
||||||
{DW + W_SE2*4+3, DW + W_EE2*4+3, DW + W_SW4*4+3,
|
|
||||||
DW + W_SS4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}}};
|
|
||||||
|
|
||||||
for (i = 0;; i++) {
|
|
||||||
rc = src_to_bitpos(es, src, sizeof(src)/sizeof(*src));
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
if (i >= 3) break;
|
|
||||||
for (j = 0; j < sizeof(src)/sizeof(*src); j++) {
|
|
||||||
src[j].m0_sw_to = wire_decrement(src[j].m0_sw_to);
|
|
||||||
src[j].m0_two_bits_o += 32;
|
|
||||||
src[j].m0_one_bit_start += 32;
|
|
||||||
src[j].m1_sw_to = wire_decrement(src[j].m1_sw_to);
|
|
||||||
src[j].m1_two_bits_o += 32;
|
|
||||||
src[j].m1_one_bit_start += 32;
|
|
||||||
for (k = 0; k < sizeof(src[0].src_wire)/sizeof(src[0].src_wire[0]); k++)
|
|
||||||
src[j].src_wire[k] = wire_decrement(src[j].src_wire[k]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// mip 12-18, decrementing directional wires (1024 switches)
|
|
||||||
{ struct sw_mip_src src[] = {
|
|
||||||
{12, NO_WIRE, 0, 2, 2,
|
|
||||||
NO_WIRE, 14, 2, 3,
|
|
||||||
{DW + W_EL1*4+3, DW + W_ER1*4+3, DW + W_WL1*4+3,
|
|
||||||
DW + W_WR1*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
|
||||||
{12, NO_WIRE, 0, 0, 2,
|
|
||||||
NO_WIRE, 14, 0, 3,
|
|
||||||
{DW + W_SS2*4+3, DW + W_SW2*4+3, DW + ((W_NW2*4+0)|DIR_S0),
|
|
||||||
DW + W_WW2*4+3, DW + W_NE2*4+3, DW + W_NN2*4+3}},
|
|
||||||
{12, NO_WIRE, 0, 1, 2,
|
|
||||||
NO_WIRE, 14, 1, 3,
|
|
||||||
{NO_WIRE, NO_WIRE, DW + ((W_NL1*4+0)|DIR_S0),
|
|
||||||
DW + W_NR1*4+3, DW + W_SL1*4+3, DW + W_SR1*4+3}},
|
|
||||||
|
|
||||||
{14, NO_WIRE, 0, 1, 3,
|
|
||||||
NO_WIRE, 14, 1, 2,
|
|
||||||
{DW + ((W_EL1*4+0)|DIR_S0), DW + W_ER1*4+3, DW + W_WL1*4+3,
|
|
||||||
DW + ((W_WR1*4+0)|DIR_S0), DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
|
||||||
{14, NO_WIRE, 0, 0, 3,
|
|
||||||
NO_WIRE, 14, 0, 2,
|
|
||||||
{DW + W_SS2*4+3, DW + W_SW2*4+3, DW + ((W_NW2*4+0)|DIR_S0),
|
|
||||||
DW + W_WW2*4+3, DW + ((W_NE2*4+0)|DIR_S0), DW + ((W_NN2*4+0)|DIR_S0)}},
|
|
||||||
{14, NO_WIRE, 0, 2, 3,
|
|
||||||
NO_WIRE, 14, 2, 2,
|
|
||||||
{NO_WIRE, NO_WIRE, DW + ((W_NL1*4+0)|DIR_S0),
|
|
||||||
DW + W_NR1*4+3, DW + W_SL1*4+3, DW + W_SR1*4+3}},
|
|
||||||
|
|
||||||
{16, NO_WIRE, 0, 2, 2,
|
|
||||||
NO_WIRE, 14, 2, 3,
|
|
||||||
{DW + W_EL1*4+3, DW + W_ER1*4+3, DW + W_WL1*4+3,
|
|
||||||
DW + W_WR1*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
|
||||||
{16, NO_WIRE, 0, 0, 2,
|
|
||||||
NO_WIRE, 14, 0, 3,
|
|
||||||
{DW + W_SS2*4+3, DW + W_SW2*4+3, DW + W_NW2*4+3,
|
|
||||||
DW + ((W_WW2*4+2)|DIR_N3), DW + W_NE2*4+3, DW + W_NN2*4+3}},
|
|
||||||
{16, NO_WIRE, 0, 1, 2,
|
|
||||||
NO_WIRE, 14, 1, 3,
|
|
||||||
{NO_WIRE, NO_WIRE, DW + W_NL1*4+3,
|
|
||||||
DW + W_NR1*4+3, DW + W_SL1*4+3, DW + ((W_SR1*4+2)|DIR_N3)}},
|
|
||||||
|
|
||||||
{18, NO_WIRE, 0, 1, 3,
|
|
||||||
NO_WIRE, 14, 1, 2,
|
|
||||||
{DW + W_EL1*4+3, DW + ((W_ER1*4+2)|DIR_N3), DW + ((W_WL1*4+2)|DIR_N3),
|
|
||||||
DW + W_WR1*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
|
||||||
{18, NO_WIRE, 0, 0, 3,
|
|
||||||
NO_WIRE, 14, 0, 2,
|
|
||||||
{DW + ((W_SS2*4+2)|DIR_N3), DW + ((W_SW2*4+2)|DIR_N3), DW + W_NW2*4+3,
|
|
||||||
DW + ((W_WW2*4+2)|DIR_N3), DW + W_NE2*4+3, DW + W_NN2*4+3}},
|
|
||||||
{18, NO_WIRE, 0, 2, 3,
|
|
||||||
NO_WIRE, 14, 2, 2,
|
|
||||||
{NO_WIRE, NO_WIRE, DW + W_NL1*4+3,
|
|
||||||
DW + W_NR1*4+3, DW + W_SL1*4+3, DW + ((W_SR1*4+2)|DIR_N3)}}};
|
|
||||||
|
|
||||||
for (i = 0; i < 8; i++) {
|
|
||||||
for (j = 0; j < sizeof(src)/sizeof(*src); j++) {
|
|
||||||
|
|
||||||
int logicin_o = ((src[j].minor-12)/2)*LOGIN_MIP_ROWS*LOGIN_ROW;
|
|
||||||
logicin_o += i*LOGIN_ROW;
|
|
||||||
|
|
||||||
src[j].m0_sw_to = logicin_matrix[logicin_o+0];
|
|
||||||
src[j].m1_sw_to = logicin_matrix[logicin_o+1];
|
|
||||||
|
|
||||||
if (i) {
|
|
||||||
src[j].m0_two_bits_o += 16;
|
|
||||||
src[j].m0_one_bit_start += 16;
|
|
||||||
src[j].m1_two_bits_o += 16;
|
|
||||||
src[j].m1_one_bit_start += 16;
|
|
||||||
if (!(i%2)) // at 2, 4 and 6 we decrement the wires
|
|
||||||
for (k = 0; k < sizeof(src[0].src_wire)/sizeof(src[0].src_wire[0]); k++)
|
|
||||||
src[j].src_wire[k] = wire_decrement(src[j].src_wire[k]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
rc = src_to_bitpos(es, src, sizeof(src)/sizeof(*src));
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// VCC/GND/GFAN, logicin and logicout sources
|
|
||||||
// mip12-14
|
|
||||||
{ int logicin_src[8][6] = {
|
|
||||||
{VCC_WIRE, LW + (LO_D|LD1), LW + LO_DQ, LW + (LO_BMUX|LD1), LOGICIN_S62, LOGICIN_S20},
|
|
||||||
{GFAN1, LW + (LO_D|LD1), LW + LO_DQ, LW + (LO_BMUX|LD1), LOGICIN_S62, LOGICIN_S20},
|
|
||||||
{VCC_WIRE, LW + LO_C, LW + (LO_CQ|LD1), LW + LO_AMUX, LOGICIN_S62, LW + (LI_AX|LD1)},
|
|
||||||
{GFAN1, LW + LO_C, LW + (LO_CQ|LD1), LW + LO_AMUX, LOGICIN_S62, LW + (LI_AX|LD1)},
|
|
||||||
{VCC_WIRE, LW + (LO_B|LD1), LW + LO_BQ, LW + (LO_DMUX|LD1), LW + (LI_AX|LD1), LW + (LI_CI|LD1)},
|
|
||||||
{GFAN0, LW + (LO_B|LD1), LW + LO_BQ, LW + (LO_DMUX|LD1), LW + (LI_AX|LD1), LW + (LI_CI|LD1)},
|
|
||||||
{VCC_WIRE, LW + LO_A, LW + (LO_AQ|LD1), LW + LO_CMUX, LOGICIN20, LW + (LI_CI|LD1)},
|
|
||||||
{GFAN0, LW + LO_A, LW + (LO_AQ|LD1), LW + LO_CMUX, LOGICIN20, LW + (LI_CI|LD1)},
|
|
||||||
};
|
|
||||||
|
|
||||||
rc = mip_to_bitpos(es, 12, 3, 2, 3, 3, &logicin_src);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
|
|
||||||
logicin_src[1][0] = logicin_src[3][0] = logicin_src[5][0] = logicin_src[7][0] = VCC_WIRE;
|
|
||||||
logicin_src[0][0] = logicin_src[2][0] = GFAN1;
|
|
||||||
logicin_src[4][0] = logicin_src[6][0] = GFAN0;
|
|
||||||
rc = mip_to_bitpos(es, 14, 3, 3, 3, 2, &logicin_src);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
}
|
|
||||||
{ int logicin_src[8][6] = {
|
|
||||||
{ LW + LI_BX, LOGICIN52 },
|
|
||||||
{ LW + LI_BX, LOGICIN52 },
|
|
||||||
{ LW + LI_BX, LW + (LI_DI|LD1) },
|
|
||||||
{ LW + LI_BX, LW + (LI_DI|LD1) },
|
|
||||||
{ LW + (LI_DI|LD1), LOGICIN_N28 },
|
|
||||||
{ LW + (LI_DI|LD1), LOGICIN_N28 },
|
|
||||||
{ LOGICIN_N52, LOGICIN_N28 },
|
|
||||||
{ LOGICIN_N52, LOGICIN_N28 }};
|
|
||||||
|
|
||||||
rc = mip_to_bitpos(es, 12, 1, 2, 1, 3, &logicin_src);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
rc = mip_to_bitpos(es, 14, 2, 3, 2, 2, &logicin_src);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
}
|
|
||||||
// mip16-18
|
|
||||||
{ int logicin_src[8][6] = {
|
|
||||||
{VCC_WIRE, LW + LO_D, LW + (LO_DQ|LD1), LW + LO_BMUX, LOGICIN_S36, LOGICIN_S44},
|
|
||||||
{GFAN1, LW + LO_D, LW + (LO_DQ|LD1), LW + LO_BMUX, LOGICIN_S36, LOGICIN_S44},
|
|
||||||
{VCC_WIRE, LW + (LO_C|LD1), LW + LO_CQ, LW + (LO_AMUX|LD1), LOGICIN_S36, LW + LI_AX},
|
|
||||||
{GFAN1, LW + (LO_C|LD1), LW + LO_CQ, LW + (LO_AMUX|LD1), LOGICIN_S36, LW + LI_AX},
|
|
||||||
{VCC_WIRE, LW + LO_B, LW + (LO_BQ|LD1), LW + LO_DMUX, LW + LI_AX, LW + (LI_CE|LD1)},
|
|
||||||
{GFAN0, LW + LO_B, LW + (LO_BQ|LD1), LW + LO_DMUX, LW + LI_AX, LW + (LI_CE|LD1)},
|
|
||||||
{VCC_WIRE, LW + (LO_A|LD1), LW + LO_AQ, LW + (LO_CMUX|LD1), LOGICIN44, LW + (LI_CE|LD1)},
|
|
||||||
{GFAN0, LW + (LO_A|LD1), LW + LO_AQ, LW + (LO_CMUX|LD1), LOGICIN44, LW + (LI_CE|LD1)},
|
|
||||||
};
|
|
||||||
|
|
||||||
rc = mip_to_bitpos(es, 16, 3, 2, 3, 3, &logicin_src);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
|
|
||||||
logicin_src[1][0] = logicin_src[3][0] = logicin_src[5][0] = logicin_src[7][0] = VCC_WIRE;
|
|
||||||
logicin_src[0][0] = logicin_src[2][0] = GFAN1;
|
|
||||||
logicin_src[4][0] = logicin_src[6][0] = GFAN0;
|
|
||||||
rc = mip_to_bitpos(es, 18, 3, 3, 3, 2, &logicin_src);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
}
|
|
||||||
{ int logicin_src[8][6] = {
|
|
||||||
{ LW + (LI_BX|LD1), LOGICIN21 },
|
|
||||||
{ LW + (LI_BX|LD1), LOGICIN21 },
|
|
||||||
{ LW + (LI_BX|LD1), FAN_B },
|
|
||||||
{ LW + (LI_BX|LD1), FAN_B },
|
|
||||||
{ FAN_B, LOGICIN_N60 },
|
|
||||||
{ FAN_B, LOGICIN_N60 },
|
|
||||||
{ LOGICIN_N21, LOGICIN_N60 },
|
|
||||||
{ LOGICIN_N21, LOGICIN_N60 }};
|
|
||||||
|
|
||||||
rc = mip_to_bitpos(es, 16, 1, 2, 1, 3, &logicin_src);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
rc = mip_to_bitpos(es, 18, 2, 3, 2, 2, &logicin_src);
|
|
||||||
if (rc) FAIL(rc);
|
|
||||||
}
|
|
||||||
|
|
||||||
// minor 20 switches (SR, CLK, GFAN = 113 switches (4 bidir added on other side))
|
|
||||||
{ const struct sw_mi20_src src[] = {
|
|
||||||
{SR1, 6, 3, 0, {GCLK11, GCLK10, GCLK13, GCLK12, GCLK9, GCLK8}},
|
|
||||||
{SR1, 6, 2, 0, {DW+W_WR1*4+2, DW+W_NR1*4+2,
|
|
||||||
VCC_WIRE, GND_WIRE, DW+W_ER1*4+2, DW+W_SR1*4+2}},
|
|
||||||
{SR1, 6, 1, 0, {FAN_B, LW+(LI_DI|LD1), LW+(LI_BX|LD1),
|
|
||||||
LW+LI_BX, GCLK15, GCLK14}},
|
|
||||||
|
|
||||||
{SR0, 8, 3, 10, {GCLK8, GCLK9, GCLK10, GCLK13, GCLK12, GCLK11}},
|
|
||||||
{SR0, 8, 2, 10, {GCLK14, GCLK15, LW+(LI_DI|LD1), LW+(LI_BX|LD1),
|
|
||||||
LW+LI_BX, FAN_B}},
|
|
||||||
{SR0, 8, 1, 10, {DW+W_SR1*4+2, DW+W_ER1*4+2, DW+W_NR1*4+2,
|
|
||||||
VCC_WIRE, NO_WIRE, DW+W_WR1*4+2}},
|
|
||||||
|
|
||||||
{CLK0, 16, 3, 18, {GCLK0, GCLK1, GCLK2, GCLK5, GCLK4, GCLK3}},
|
|
||||||
{CLK0, 16, 2, 18, {GCLK6, GCLK7, GCLK8, GCLK11, GCLK10, GCLK9}},
|
|
||||||
{CLK0, 16, 1, 18, {GCLK12, GCLK13, GCLK14, LW+(LI_BX|LD1), LW+(LI_CI|LD1), GCLK15}},
|
|
||||||
{CLK0, 16, 0, 18, {DW+W_NR1*4+2, DW+W_WR1*4+2,
|
|
||||||
DW+W_SR1*4+1, VCC_WIRE, NO_WIRE, DW+W_ER1*4+1}},
|
|
||||||
|
|
||||||
{CLK1, 46, 3, 40, {GCLK3, GCLK2, GCLK5, GCLK4, GCLK1, GCLK0}},
|
|
||||||
{CLK1, 46, 2, 40, {GCLK15, GCLK14, LW+(LI_BX|LD1), LW+(LI_CI|LD1), GCLK13, GCLK12}},
|
|
||||||
{CLK1, 46, 1, 40, {GCLK9, GCLK8, GCLK11, GCLK10, GCLK7, GCLK6}},
|
|
||||||
{CLK1, 46, 0, 40, {DW+W_ER1*4+1, DW+W_SR1*4+1, VCC_WIRE,
|
|
||||||
NO_WIRE, DW+W_WR1*4+2, DW+W_NR1*4+2}},
|
|
||||||
|
|
||||||
{GFAN0, 54, 3, 48, {GCLK3, GCLK4, GCLK5, GCLK2, GCLK1, GCLK0}},
|
|
||||||
{GFAN0, 54, 2, 48, {DW+W_WR1*4+1, GND_WIRE, VCC_WIRE, DW+W_NR1*4+1, DW+W_ER1*4+1, DW+W_SR1*4+1}},
|
|
||||||
{GFAN0, 54, 1, 48, {LW+(LI_CE|LD1), NO_WIRE, NO_WIRE, LW+(LI_CI|LD1), GCLK7, GCLK6}},
|
|
||||||
|
|
||||||
{GFAN1, 56, 3, 58, {GCLK0, GCLK1, GCLK4, GCLK5, GCLK2, GCLK3}},
|
|
||||||
{GFAN1, 56, 2, 58, {GCLK6, GCLK7, LW+(LI_AX|LD1), LW+LI_AX, NO_WIRE, NO_WIRE}},
|
|
||||||
{GFAN1, 56, 1, 58, {DW+W_SR1*4+1, DW+W_ER1*4+1, GND_WIRE, VCC_WIRE, DW+W_NR1*4+1, DW+W_WR1*4+1}}};
|
|
||||||
|
|
||||||
for (i = 0; i < sizeof(src)/sizeof(*src); i++) {
|
|
||||||
for (j = 0; j < sizeof(src[0].src_wire)/sizeof(src[0].src_wire[0]); j++) {
|
|
||||||
if (src[i].src_wire[j] == NO_WIRE) continue;
|
|
||||||
|
|
||||||
es->bit_pos[es->num_bit_pos].minor = 20;
|
|
||||||
es->bit_pos[es->num_bit_pos].two_bits_o = src[i].two_bits_o;
|
|
||||||
es->bit_pos[es->num_bit_pos].two_bits_val = src[i].two_bits_val;
|
|
||||||
es->bit_pos[es->num_bit_pos].one_bit_o = src[i].one_bit_start + j;
|
|
||||||
es->bit_pos[es->num_bit_pos].uni_dir = fpga_switch_lookup(es->model,
|
|
||||||
es->model->first_routing_y, es->model->first_routing_x,
|
|
||||||
fpga_wirestr_i(es->model, src[i].src_wire[j]),
|
|
||||||
fpga_wirestr_i(es->model, src[i].sw_to));
|
|
||||||
if (es->bit_pos[es->num_bit_pos].uni_dir == NO_SWITCH) {
|
|
||||||
fprintf(stderr, "#E routing switch %s -> %s not in model\n",
|
|
||||||
fpga_wirestr(es->model, src[i].src_wire[j]),
|
|
||||||
fpga_wirestr(es->model, src[i].sw_to));
|
|
||||||
FAIL(EINVAL);
|
|
||||||
}
|
|
||||||
es->bit_pos[es->num_bit_pos].rev_dir = NO_SWITCH;
|
|
||||||
es->num_bit_pos++;
|
|
||||||
}
|
|
||||||
}}
|
|
||||||
return 0;
|
return 0;
|
||||||
fail:
|
fail:
|
||||||
return rc;
|
return rc;
|
||||||
|
|
@ -1103,23 +497,23 @@ int printf_swbits(struct fpga_model* model)
|
||||||
|
|
||||||
rc = construct_extract_state(&es, model);
|
rc = construct_extract_state(&es, model);
|
||||||
if (rc) FAIL(rc);
|
if (rc) FAIL(rc);
|
||||||
for (i = 0; i < es.num_bit_pos; i++) {
|
for (i = 0; i < model->num_bitpos; i++) {
|
||||||
|
|
||||||
width = (es.bit_pos[i].minor == 20) ? 64 : 128;
|
width = (model->sw_bitpos[i].minor == 20) ? 64 : 128;
|
||||||
for (j = 0; j < width; j++)
|
for (j = 0; j < width; j++)
|
||||||
bit_str[j] = '0';
|
bit_str[j] = '0';
|
||||||
bit_str[j] = 0;
|
bit_str[j] = 0;
|
||||||
|
|
||||||
if (es.bit_pos[i].two_bits_val & 2)
|
if (model->sw_bitpos[i].two_bits_val & 2)
|
||||||
bit_str[es.bit_pos[i].two_bits_o] = '1';
|
bit_str[model->sw_bitpos[i].two_bits_o] = '1';
|
||||||
if (es.bit_pos[i].two_bits_val & 1)
|
if (model->sw_bitpos[i].two_bits_val & 1)
|
||||||
bit_str[es.bit_pos[i].two_bits_o+1] = '1';
|
bit_str[model->sw_bitpos[i].two_bits_o+1] = '1';
|
||||||
bit_str[es.bit_pos[i].one_bit_o] = '1';
|
bit_str[model->sw_bitpos[i].one_bit_o] = '1';
|
||||||
printf("mi%02i %s %s %s %s\n", es.bit_pos[i].minor,
|
printf("mi%02i %s %s %s %s\n", model->sw_bitpos[i].minor,
|
||||||
fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.bit_pos[i].uni_dir, SW_TO),
|
fpga_wirestr(model, model->sw_bitpos[i].to),
|
||||||
bit_str,
|
bit_str,
|
||||||
fpga_switch_str(model, model->first_routing_y, model->first_routing_x, es.bit_pos[i].uni_dir, SW_FROM),
|
fpga_wirestr(model, model->sw_bitpos[i].from),
|
||||||
es.bit_pos[i].rev_dir != NO_SWITCH ? "<->" : "->");
|
model->sw_bitpos[i].bidir ? "<->" : "->");
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
fail:
|
fail:
|
||||||
|
|
|
||||||
|
|
@ -134,6 +134,7 @@ void fpga_swset_print(struct fpga_model* model, int y, int x,
|
||||||
// switches were found and writen to same_sw.
|
// switches were found and writen to same_sw.
|
||||||
int fpga_switch_same_fromto(struct fpga_model* model, int y, int x,
|
int fpga_switch_same_fromto(struct fpga_model* model, int y, int x,
|
||||||
swidx_t sw, int from_to, swidx_t* same_sw, int *same_len);
|
swidx_t sw, int from_to, swidx_t* same_sw, int *same_len);
|
||||||
|
// fpga_switch_lookup() returns NO_SWITCH if switch not found.
|
||||||
swidx_t fpga_switch_lookup(struct fpga_model* model, int y, int x,
|
swidx_t fpga_switch_lookup(struct fpga_model* model, int y, int x,
|
||||||
str16_t from_str_i, str16_t to_str_i);
|
str16_t from_str_i, str16_t to_str_i);
|
||||||
|
|
||||||
|
|
|
||||||
2
model.h
2
model.h
|
|
@ -72,6 +72,8 @@ struct fpga_model
|
||||||
// 'majors' in the bitstream.
|
// 'majors' in the bitstream.
|
||||||
int x_major[512];
|
int x_major[512];
|
||||||
|
|
||||||
|
struct xc6_routing_bitpos* sw_bitpos;
|
||||||
|
int num_bitpos;
|
||||||
int first_routing_y, first_routing_x;
|
int first_routing_y, first_routing_x;
|
||||||
|
|
||||||
struct fpga_tile* tiles;
|
struct fpga_tile* tiles;
|
||||||
|
|
|
||||||
|
|
@ -7,6 +7,7 @@
|
||||||
|
|
||||||
#include <stdarg.h>
|
#include <stdarg.h>
|
||||||
#include "model.h"
|
#include "model.h"
|
||||||
|
#include "parts.h"
|
||||||
|
|
||||||
static int s_high_speed_replicate = 1;
|
static int s_high_speed_replicate = 1;
|
||||||
|
|
||||||
|
|
@ -23,6 +24,8 @@ int fpga_build_model(struct fpga_model* model, int fpga_rows,
|
||||||
strncpy(model->cfg_right_wiring, right_wiring,
|
strncpy(model->cfg_right_wiring, right_wiring,
|
||||||
sizeof(model->cfg_right_wiring)-1);
|
sizeof(model->cfg_right_wiring)-1);
|
||||||
strarray_init(&model->str, STRIDX_64K);
|
strarray_init(&model->str, STRIDX_64K);
|
||||||
|
rc = get_xc6_routing_bitpos(&model->sw_bitpos, &model->num_bitpos);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
model->first_routing_y = -1;
|
model->first_routing_y = -1;
|
||||||
model->first_routing_x = -1;
|
model->first_routing_x = -1;
|
||||||
|
|
||||||
|
|
@ -63,6 +66,7 @@ void fpga_free_model(struct fpga_model* model)
|
||||||
free(model->tmp_str);
|
free(model->tmp_str);
|
||||||
strarray_free(&model->str);
|
strarray_free(&model->str);
|
||||||
free(model->tiles);
|
free(model->tiles);
|
||||||
|
free_xc6_routing_bitpos(model->sw_bitpos);
|
||||||
memset(model, 0, sizeof(*model));
|
memset(model, 0, sizeof(*model));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
624
parts.c
624
parts.c
|
|
@ -5,7 +5,8 @@
|
||||||
// For details see the UNLICENSE file at the root of the source tree.
|
// For details see the UNLICENSE file at the root of the source tree.
|
||||||
//
|
//
|
||||||
|
|
||||||
#include "helper.h"
|
#include "model.h"
|
||||||
|
#include "control.h"
|
||||||
#include "parts.h"
|
#include "parts.h"
|
||||||
|
|
||||||
const char* iob_xc6slx9_sitenames[IOB_WORDS*2/8] =
|
const char* iob_xc6slx9_sitenames[IOB_WORDS*2/8] =
|
||||||
|
|
@ -131,3 +132,624 @@ enum major_type get_major_type(int idcode, int major)
|
||||||
EXIT(1);
|
EXIT(1);
|
||||||
return major_types[major];
|
return major_types[major];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// routing switches
|
||||||
|
//
|
||||||
|
|
||||||
|
struct sw_mip_src
|
||||||
|
{
|
||||||
|
int minor;
|
||||||
|
|
||||||
|
int m0_sw_to;
|
||||||
|
int m0_two_bits_o;
|
||||||
|
int m0_two_bits_val;
|
||||||
|
int m0_one_bit_start;
|
||||||
|
|
||||||
|
int m1_sw_to;
|
||||||
|
int m1_two_bits_o;
|
||||||
|
int m1_two_bits_val;
|
||||||
|
int m1_one_bit_start;
|
||||||
|
|
||||||
|
int from_w[6];
|
||||||
|
};
|
||||||
|
|
||||||
|
// returns:
|
||||||
|
// 1 for the active side of a bidir switch, where the bits reside
|
||||||
|
// 0 for a unidirectional switch
|
||||||
|
// -1 for the passive side of a bidir switch, where no bits reside
|
||||||
|
static int bidir_check(int sw_to, int sw_from)
|
||||||
|
{
|
||||||
|
// the first member of bidir switch pairs is where the bits reside
|
||||||
|
static const int bidir[] = {
|
||||||
|
LW + (LI_BX|LD1), FAN_B,
|
||||||
|
LW + (LI_AX|LD1), GFAN0,
|
||||||
|
LW + LI_AX, GFAN0,
|
||||||
|
LW + (LI_CE|LD1), GFAN1,
|
||||||
|
LW + (LI_CI|LD1), GFAN1,
|
||||||
|
LW + LI_BX, LW + (LI_CI|LD1),
|
||||||
|
LW + LI_BX, LW + (LI_DI|LD1),
|
||||||
|
LW + (LI_AX|LD1), LW + (LI_CI|LD1),
|
||||||
|
LW + (LI_BX|LD1), LW + (LI_CE|LD1),
|
||||||
|
LW + LI_AX, LW + (LI_CE|LD1) };
|
||||||
|
int i;
|
||||||
|
|
||||||
|
// bidirectional switches are ignored on one side, and
|
||||||
|
// marked as bidir on the other side
|
||||||
|
for (i = 0; i < sizeof(bidir)/sizeof(*bidir)/2; i++) {
|
||||||
|
if (sw_from == bidir[i*2] && sw_to == bidir[i*2+1])
|
||||||
|
// nothing to do where no bits reside
|
||||||
|
return -1;
|
||||||
|
if (sw_from == bidir[i*2+1] && sw_to == bidir[i*2])
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int wire_decrement(int wire)
|
||||||
|
{
|
||||||
|
int _wire, flags;
|
||||||
|
|
||||||
|
if (wire >= DW && wire <= DW_LAST) {
|
||||||
|
_wire = wire - DW;
|
||||||
|
flags = _wire & DIR_FLAGS;
|
||||||
|
_wire &= ~DIR_FLAGS;
|
||||||
|
|
||||||
|
if (_wire%4 == 0)
|
||||||
|
return DW + ((_wire + 3) | flags);
|
||||||
|
return DW + ((_wire - 1) | flags);
|
||||||
|
}
|
||||||
|
if (wire >= LW && wire <= LW_LAST) {
|
||||||
|
_wire = wire - LW;
|
||||||
|
flags = _wire & LD1;
|
||||||
|
_wire &= ~LD1;
|
||||||
|
|
||||||
|
if (_wire == LO_A)
|
||||||
|
return LW + (LO_D|flags);
|
||||||
|
if (_wire == LO_AMUX)
|
||||||
|
return LW + (LO_DMUX|flags);
|
||||||
|
if (_wire == LO_AQ)
|
||||||
|
return LW + (LO_DQ|flags);
|
||||||
|
if ((_wire >= LO_B && _wire <= LO_D)
|
||||||
|
|| (_wire >= LO_BMUX && _wire <= LO_DMUX)
|
||||||
|
|| (_wire >= LO_BQ && _wire <= LO_DQ))
|
||||||
|
return LW + ((_wire-1)|flags);
|
||||||
|
}
|
||||||
|
if (wire == NO_WIRE) return wire;
|
||||||
|
HERE();
|
||||||
|
return wire;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int src_to_bitpos(struct xc6_routing_bitpos* bitpos, int* cur_el, int max_el,
|
||||||
|
const struct sw_mip_src* src, int src_len)
|
||||||
|
{
|
||||||
|
int i, j, bidir, rc;
|
||||||
|
|
||||||
|
for (i = 0; i < src_len; i++) {
|
||||||
|
for (j = 0; j < sizeof(src->from_w)/sizeof(src->from_w[0]); j++) {
|
||||||
|
if (src[i].from_w[j] == NO_WIRE) continue;
|
||||||
|
|
||||||
|
bidir = bidir_check(src[i].m0_sw_to, src[i].from_w[j]);
|
||||||
|
if (bidir != -1) {
|
||||||
|
if (*cur_el >= max_el) FAIL(EINVAL);
|
||||||
|
bitpos[*cur_el].from = src[i].from_w[j];
|
||||||
|
bitpos[*cur_el].to = src[i].m0_sw_to;
|
||||||
|
bitpos[*cur_el].bidir = bidir;
|
||||||
|
bitpos[*cur_el].minor = src[i].minor;
|
||||||
|
bitpos[*cur_el].two_bits_o = src[i].m0_two_bits_o;
|
||||||
|
bitpos[*cur_el].two_bits_val = src[i].m0_two_bits_val;
|
||||||
|
bitpos[*cur_el].one_bit_o = src[i].m0_one_bit_start + j*2;
|
||||||
|
(*cur_el)++;
|
||||||
|
}
|
||||||
|
|
||||||
|
bidir = bidir_check(src[i].m1_sw_to, src[i].from_w[j]);
|
||||||
|
if (bidir != -1) {
|
||||||
|
if (*cur_el >= max_el) FAIL(EINVAL);
|
||||||
|
bitpos[*cur_el].from = src[i].from_w[j];
|
||||||
|
bitpos[*cur_el].to = src[i].m1_sw_to;
|
||||||
|
bitpos[*cur_el].bidir = bidir;
|
||||||
|
bitpos[*cur_el].minor = src[i].minor;
|
||||||
|
bitpos[*cur_el].two_bits_o = src[i].m1_two_bits_o;
|
||||||
|
bitpos[*cur_el].two_bits_val = src[i].m1_two_bits_val;
|
||||||
|
bitpos[*cur_el].one_bit_o = src[i].m1_one_bit_start + j*2;
|
||||||
|
(*cur_el)++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
fail:
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define LOGIN_ROW 2
|
||||||
|
#define LOGIN_MIP_ROWS 8
|
||||||
|
static const int logicin_matrix[] =
|
||||||
|
{
|
||||||
|
/*mip 12*/
|
||||||
|
/* 000 */ LW + (LI_C6|LD1), LW + LI_D6,
|
||||||
|
/* 016 */ LW + (LI_B1|LD1), LW + (LI_DI|LD1),
|
||||||
|
/* 032 */ LW + (LI_C5|LD1), LW + LI_D5,
|
||||||
|
/* 048 */ LW + (LI_CI|LD1), LW + LI_A2,
|
||||||
|
/* 064 */ LW + (LI_C4|LD1), LW + LI_D4,
|
||||||
|
/* 080 */ LW + LI_A1, LW + LI_CE,
|
||||||
|
/* 096 */ LW + (LI_C3|LD1), LW + LI_D3,
|
||||||
|
/* 112 */ LW + (LI_B2|LD1), LW + (LI_WE|LD1),
|
||||||
|
|
||||||
|
/*mip 14*/
|
||||||
|
/* 000 */ LW + LI_C1, LW + LI_DX,
|
||||||
|
/* 016 */ LW + (LI_A3|LD1), LW + LI_B3,
|
||||||
|
/* 032 */ LW + (LI_CX|LD1), LW + (LI_D2|LD1),
|
||||||
|
/* 048 */ LW + (LI_A4|LD1), LW + LI_B4,
|
||||||
|
/* 064 */ LW + (LI_D1|LD1), LW + LI_BX,
|
||||||
|
/* 080 */ LW + (LI_A5|LD1), LW + LI_B5,
|
||||||
|
/* 096 */ LW + (LI_AX|LD1), LW + LI_C2,
|
||||||
|
/* 112 */ LW + (LI_A6|LD1), LW + LI_B6,
|
||||||
|
|
||||||
|
/*mip 16*/
|
||||||
|
/* 000 */ LW + (LI_B3|LD1), LW + LI_A3,
|
||||||
|
/* 016 */ LW + (LI_C2|LD1), LW + (LI_DX|LD1),
|
||||||
|
/* 032 */ LW + (LI_B4|LD1), LW + LI_A4,
|
||||||
|
/* 048 */ LW + LI_CX, LW + LI_D1,
|
||||||
|
/* 064 */ LW + (LI_B5|LD1), LW + LI_A5,
|
||||||
|
/* 080 */ LW + (LI_BX|LD1), LW + LI_D2,
|
||||||
|
/* 096 */ LW + (LI_B6|LD1), LW + LI_A6,
|
||||||
|
/* 112 */ LW + (LI_C1|LD1), LW + LI_AX,
|
||||||
|
|
||||||
|
/*mip 18*/
|
||||||
|
/* 000 */ LW + LI_B2, FAN_B,
|
||||||
|
/* 016 */ LW + (LI_D6|LD1), LW + LI_C6,
|
||||||
|
/* 032 */ LW + (LI_A1|LD1), LW + (LI_CE|LD1),
|
||||||
|
/* 048 */ LW + (LI_D5|LD1), LW + LI_C5,
|
||||||
|
/* 064 */ LW + (LI_A2|LD1), LW + (LI_BI|LD1),
|
||||||
|
/* 080 */ LW + (LI_D4|LD1), LW + LI_C4,
|
||||||
|
/* 096 */ LW + (LI_AI|LD1), LW + LI_B1,
|
||||||
|
/* 112 */ LW + (LI_D3|LD1), LW + LI_C3
|
||||||
|
};
|
||||||
|
|
||||||
|
static int mip_to_bitpos(struct xc6_routing_bitpos* bitpos, int* cur_el,
|
||||||
|
int max_el, int minor, int m0_two_bits_val, int m0_one_bit_start,
|
||||||
|
int m1_two_bits_val, int m1_one_bit_start, int (*from_ws)[8][6])
|
||||||
|
{
|
||||||
|
struct sw_mip_src src;
|
||||||
|
int i, j, rc;
|
||||||
|
|
||||||
|
src.minor = minor;
|
||||||
|
src.m0_two_bits_o = 0;
|
||||||
|
src.m0_two_bits_val = m0_two_bits_val;
|
||||||
|
src.m0_one_bit_start = m0_one_bit_start;
|
||||||
|
src.m1_two_bits_o = 14;
|
||||||
|
src.m1_two_bits_val = m1_two_bits_val;
|
||||||
|
src.m1_one_bit_start = m1_one_bit_start;
|
||||||
|
for (i = 0; i < 8; i++) {
|
||||||
|
int logicin_o = ((src.minor-12)/2)*LOGIN_MIP_ROWS*LOGIN_ROW;
|
||||||
|
logicin_o += i*LOGIN_ROW;
|
||||||
|
src.m0_sw_to = logicin_matrix[logicin_o+0];
|
||||||
|
src.m1_sw_to = logicin_matrix[logicin_o+1];
|
||||||
|
if (i) {
|
||||||
|
src.m0_two_bits_o += 16;
|
||||||
|
src.m0_one_bit_start += 16;
|
||||||
|
src.m1_two_bits_o += 16;
|
||||||
|
src.m1_one_bit_start += 16;
|
||||||
|
}
|
||||||
|
for (j = 0; j < sizeof(src.from_w)/sizeof(src.from_w[0]); j++)
|
||||||
|
src.from_w[j] = (*from_ws)[i][j];
|
||||||
|
|
||||||
|
rc = src_to_bitpos(bitpos, cur_el, max_el, &src, /*src_len*/ 1);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
fail:
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
int get_xc6_routing_bitpos(struct xc6_routing_bitpos** bitpos, int* num_bitpos)
|
||||||
|
{
|
||||||
|
int i, j, k, rc;
|
||||||
|
|
||||||
|
*num_bitpos = 0;
|
||||||
|
*bitpos = malloc(MAX_SWITCHBOX_SIZE * sizeof(**bitpos));
|
||||||
|
if (!(*bitpos)) FAIL(ENOMEM);
|
||||||
|
|
||||||
|
// mip 0-10 (6*288=1728 switches)
|
||||||
|
{ struct sw_mip_src src[] = {
|
||||||
|
{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 2, 3,
|
||||||
|
DW + ((W_NW4*4+3) | DIR_BEG), 14, 1, 2,
|
||||||
|
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
||||||
|
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
||||||
|
{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 1, 3,
|
||||||
|
DW + ((W_NW4*4+3) | DIR_BEG), 14, 2, 2,
|
||||||
|
{DW + ((W_SW2*4+2)|DIR_N3), DW + ((W_SS2*4+2)|DIR_N3), DW + ((W_WW2*4+2)|DIR_N3),
|
||||||
|
DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_NW2*4+3}},
|
||||||
|
{0, DW + ((W_WW4*4+3) | DIR_BEG), 0, 0, 3,
|
||||||
|
DW + ((W_NW4*4+3) | DIR_BEG), 14, 0, 2,
|
||||||
|
{DW + ((W_SW4*4+2)|DIR_N3), DW + ((W_SS4*4+2)|DIR_N3), DW + W_NE4*4+3,
|
||||||
|
DW + W_NN4*4+3, DW + W_NW4*4+3, DW + W_WW4*4+3}},
|
||||||
|
{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 2, 18,
|
||||||
|
DW + ((W_SW4*4+3) | DIR_BEG), 30, 1, 19,
|
||||||
|
{DW + W_SW2*4+3, DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0),
|
||||||
|
DW + W_SS2*4+3, DW + W_SE2*4+3, DW + W_EE2*4+3}},
|
||||||
|
{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 1, 18,
|
||||||
|
DW + ((W_SW4*4+3) | DIR_BEG), 30, 2, 19,
|
||||||
|
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
||||||
|
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
||||||
|
{0, DW + ((W_SS4*4+3) | DIR_BEG), 16, 0, 18,
|
||||||
|
DW + ((W_SW4*4+3) | DIR_BEG), 30, 0, 19,
|
||||||
|
{DW + W_SW4*4+3, DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0),
|
||||||
|
DW + ((W_NW4*4+0)|DIR_S0), DW + W_SE4*4+3, DW + W_EE4*4+3}},
|
||||||
|
|
||||||
|
{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 2, 3,
|
||||||
|
DW + ((W_NE4*4+3) | DIR_BEG), 14, 1, 2,
|
||||||
|
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
||||||
|
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
||||||
|
{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 1, 3,
|
||||||
|
DW + ((W_NE4*4+3) | DIR_BEG), 14, 2, 2,
|
||||||
|
{DW + W_EE2*4+3, DW + W_SE2*4+3, DW + ((W_WW2*4+2)|DIR_N3),
|
||||||
|
DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_NW2*4+3}},
|
||||||
|
{2, DW + ((W_NN4*4+3) | DIR_BEG), 0, 0, 3,
|
||||||
|
DW + ((W_NE4*4+3) | DIR_BEG), 14, 0, 2,
|
||||||
|
{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
|
||||||
|
DW + W_NN4*4+3, DW + W_NW4*4+3, DW + W_WW4*4+3}},
|
||||||
|
{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 2, 18,
|
||||||
|
DW + ((W_SE4*4+3) | DIR_BEG), 30, 1, 19,
|
||||||
|
{DW + W_SW2*4+3, DW + W_NN2*4+3, DW + W_NE2*4+3,
|
||||||
|
DW + W_SS2*4+3, DW + W_SE2*4+3, DW + W_EE2*4+3}},
|
||||||
|
{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 1, 18,
|
||||||
|
DW + ((W_SE4*4+3) | DIR_BEG), 30, 2, 19,
|
||||||
|
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
||||||
|
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
||||||
|
{2, DW + ((W_EE4*4+3) | DIR_BEG), 16, 0, 18,
|
||||||
|
DW + ((W_SE4*4+3) | DIR_BEG), 30, 0, 19,
|
||||||
|
{DW + W_SW4*4+3, DW + W_SS4*4+3, DW + W_NN4*4+3,
|
||||||
|
DW + W_NE4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}},
|
||||||
|
|
||||||
|
{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 2, 3,
|
||||||
|
DW + ((W_NN2*4+3) | DIR_BEG), 14, 1, 2,
|
||||||
|
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
||||||
|
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
||||||
|
{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 1, 3,
|
||||||
|
DW + ((W_NN2*4+3) | DIR_BEG), 14, 2, 2,
|
||||||
|
{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + ((W_WL1*4+2)|DIR_N3),
|
||||||
|
DW + W_WR1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
|
||||||
|
{4, DW + ((W_NW2*4+3) | DIR_BEG), 0, 0, 3,
|
||||||
|
DW + ((W_NN2*4+3) | DIR_BEG), 14, 0, 2,
|
||||||
|
{DW + W_NW4*4+3, DW + W_WW4*4+3, DW + W_NE4*4+3,
|
||||||
|
DW + W_NN4*4+3, DW + ((W_WW2*4+2)|DIR_N3), DW + W_NW2*4+3}},
|
||||||
|
{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 2, 18,
|
||||||
|
DW + ((W_SW2*4+3) | DIR_BEG), 30, 1, 19,
|
||||||
|
{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + ((W_WR1*4+0)|DIR_S0),
|
||||||
|
DW + W_WL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
|
||||||
|
{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 1, 18,
|
||||||
|
DW + ((W_SW2*4+3) | DIR_BEG), 30, 2, 19,
|
||||||
|
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
||||||
|
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
||||||
|
{4, DW + ((W_WW2*4+3) | DIR_BEG), 16, 0, 18,
|
||||||
|
DW + ((W_SW2*4+3) | DIR_BEG), 30, 0, 19,
|
||||||
|
{DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0), DW + W_SW4*4+3,
|
||||||
|
DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0), DW + ((W_NW4*4+0)|DIR_S0)}},
|
||||||
|
|
||||||
|
{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 2, 3,
|
||||||
|
DW + ((W_EE2*4+3) | DIR_BEG), 14, 1, 2,
|
||||||
|
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
||||||
|
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
||||||
|
{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 1, 3,
|
||||||
|
DW + ((W_EE2*4+3) | DIR_BEG), 14, 2, 2,
|
||||||
|
{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_EL1*4+3,
|
||||||
|
DW + W_ER1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
|
||||||
|
{6, DW + ((W_NE2*4+3) | DIR_BEG), 0, 0, 3,
|
||||||
|
DW + ((W_EE2*4+3) | DIR_BEG), 14, 0, 2,
|
||||||
|
{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
|
||||||
|
DW + W_NN4*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
||||||
|
{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 2, 18,
|
||||||
|
DW + ((W_SE2*4+3) | DIR_BEG), 30, 1, 19,
|
||||||
|
{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + W_ER1*4+3,
|
||||||
|
DW + W_EL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
|
||||||
|
{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 1, 18,
|
||||||
|
DW + ((W_SE2*4+3) | DIR_BEG), 30, 2, 19,
|
||||||
|
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
||||||
|
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
||||||
|
{6, DW + ((W_SS2*4+3) | DIR_BEG), 16, 0, 18,
|
||||||
|
DW + ((W_SE2*4+3) | DIR_BEG), 30, 0, 19,
|
||||||
|
{DW + W_SE2*4+3, DW + W_EE2*4+3, DW + W_SW4*4+3,
|
||||||
|
DW + W_SS4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}},
|
||||||
|
|
||||||
|
{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 2, 3,
|
||||||
|
DW + ((W_NL1*4+2) | DIR_BEG), 14, 1, 2,
|
||||||
|
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
||||||
|
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
||||||
|
{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 1, 3,
|
||||||
|
DW + ((W_NL1*4+2) | DIR_BEG), 14, 2, 2,
|
||||||
|
{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + ((W_WL1*4+2)|DIR_N3),
|
||||||
|
DW + W_WR1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
|
||||||
|
{8, DW + ((W_WR1*4+0) | DIR_BEG), 0, 0, 3,
|
||||||
|
DW + ((W_NL1*4+2) | DIR_BEG), 14, 0, 2,
|
||||||
|
{DW + W_NW4*4+3, DW + W_WW4*4+3, DW + W_NE4*4+3,
|
||||||
|
DW + W_NN4*4+3, DW + ((W_WW2*4+2)|DIR_N3), DW + W_NW2*4+3}},
|
||||||
|
{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 2, 18,
|
||||||
|
DW + ((W_WL1*4+2) | DIR_BEG), 30, 1, 19,
|
||||||
|
{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + ((W_WR1*4+0)|DIR_S0),
|
||||||
|
DW + W_WL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
|
||||||
|
{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 1, 18,
|
||||||
|
DW + ((W_WL1*4+2) | DIR_BEG), 30, 2, 19,
|
||||||
|
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
||||||
|
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
||||||
|
{8, DW + ((W_SR1*4+0) | DIR_BEG), 16, 0, 18,
|
||||||
|
DW + ((W_WL1*4+2) | DIR_BEG), 30, 0, 19,
|
||||||
|
{DW + W_WW2*4+3, DW + ((W_NW2*4+0)|DIR_S0), DW + W_SW4*4+3,
|
||||||
|
DW + W_SS4*4+3, DW + ((W_WW4*4+0)|DIR_S0), DW + ((W_NW4*4+0)|DIR_S0)}},
|
||||||
|
|
||||||
|
{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 2, 3,
|
||||||
|
DW + ((W_NR1*4+3) | DIR_BEG), 14, 1, 2,
|
||||||
|
{LW + (LO_BMUX|LD1), LW + (LO_DQ|LD1), LW + (LO_D|LD1),
|
||||||
|
LW + LO_BMUX, LW + LO_DQ, LW + LO_D}},
|
||||||
|
{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 1, 3,
|
||||||
|
DW + ((W_NR1*4+3) | DIR_BEG), 14, 2, 2,
|
||||||
|
{DW + W_NE2*4+3, DW + W_NN2*4+3, DW + W_EL1*4+3,
|
||||||
|
DW + W_ER1*4+3, DW + W_NR1*4+3, DW + W_NL1*4+3}},
|
||||||
|
{10, DW + ((W_EL1*4+2) | DIR_BEG), 0, 0, 3,
|
||||||
|
DW + ((W_NR1*4+3) | DIR_BEG), 14, 0, 2,
|
||||||
|
{DW + W_EE4*4+3, DW + W_SE4*4+3, DW + W_NE4*4+3,
|
||||||
|
DW + W_NN4*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
||||||
|
{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 2, 18,
|
||||||
|
DW + ((W_ER1*4+0) | DIR_BEG), 30, 1, 19,
|
||||||
|
{DW + W_SR1*4+3, DW + W_SL1*4+3, DW + W_ER1*4+3,
|
||||||
|
DW + W_EL1*4+3, DW + W_SW2*4+3, DW + W_SS2*4+3}},
|
||||||
|
{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 1, 18,
|
||||||
|
DW + ((W_ER1*4+0) | DIR_BEG), 30, 2, 19,
|
||||||
|
{LW + LO_D, LW + LO_DQ, LW + LO_BMUX,
|
||||||
|
LW + (LO_D|LD1), LW + (LO_DQ|LD1), LW + (LO_BMUX|LD1)}},
|
||||||
|
{10, DW + ((W_SL1*4+3) | DIR_BEG), 16, 0, 18,
|
||||||
|
DW + ((W_ER1*4+0) | DIR_BEG), 30, 0, 19,
|
||||||
|
{DW + W_SE2*4+3, DW + W_EE2*4+3, DW + W_SW4*4+3,
|
||||||
|
DW + W_SS4*4+3, DW + W_SE4*4+3, DW + W_EE4*4+3}}};
|
||||||
|
|
||||||
|
for (i = 0;; i++) {
|
||||||
|
rc = src_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
src, sizeof(src)/sizeof(*src));
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
if (i >= 3) break;
|
||||||
|
for (j = 0; j < sizeof(src)/sizeof(*src); j++) {
|
||||||
|
src[j].m0_sw_to = wire_decrement(src[j].m0_sw_to);
|
||||||
|
src[j].m0_two_bits_o += 32;
|
||||||
|
src[j].m0_one_bit_start += 32;
|
||||||
|
src[j].m1_sw_to = wire_decrement(src[j].m1_sw_to);
|
||||||
|
src[j].m1_two_bits_o += 32;
|
||||||
|
src[j].m1_one_bit_start += 32;
|
||||||
|
for (k = 0; k < sizeof(src[0].from_w)/sizeof(src[0].from_w[0]); k++)
|
||||||
|
src[j].from_w[k] = wire_decrement(src[j].from_w[k]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// mip 12-18, decrementing directional wires (1024 switches)
|
||||||
|
{ struct sw_mip_src src[] = {
|
||||||
|
{12, NO_WIRE, 0, 2, 2,
|
||||||
|
NO_WIRE, 14, 2, 3,
|
||||||
|
{DW + W_EL1*4+3, DW + W_ER1*4+3, DW + W_WL1*4+3,
|
||||||
|
DW + W_WR1*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
||||||
|
{12, NO_WIRE, 0, 0, 2,
|
||||||
|
NO_WIRE, 14, 0, 3,
|
||||||
|
{DW + W_SS2*4+3, DW + W_SW2*4+3, DW + ((W_NW2*4+0)|DIR_S0),
|
||||||
|
DW + W_WW2*4+3, DW + W_NE2*4+3, DW + W_NN2*4+3}},
|
||||||
|
{12, NO_WIRE, 0, 1, 2,
|
||||||
|
NO_WIRE, 14, 1, 3,
|
||||||
|
{NO_WIRE, NO_WIRE, DW + ((W_NL1*4+0)|DIR_S0),
|
||||||
|
DW + W_NR1*4+3, DW + W_SL1*4+3, DW + W_SR1*4+3}},
|
||||||
|
|
||||||
|
{14, NO_WIRE, 0, 1, 3,
|
||||||
|
NO_WIRE, 14, 1, 2,
|
||||||
|
{DW + ((W_EL1*4+0)|DIR_S0), DW + W_ER1*4+3, DW + W_WL1*4+3,
|
||||||
|
DW + ((W_WR1*4+0)|DIR_S0), DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
||||||
|
{14, NO_WIRE, 0, 0, 3,
|
||||||
|
NO_WIRE, 14, 0, 2,
|
||||||
|
{DW + W_SS2*4+3, DW + W_SW2*4+3, DW + ((W_NW2*4+0)|DIR_S0),
|
||||||
|
DW + W_WW2*4+3, DW + ((W_NE2*4+0)|DIR_S0), DW + ((W_NN2*4+0)|DIR_S0)}},
|
||||||
|
{14, NO_WIRE, 0, 2, 3,
|
||||||
|
NO_WIRE, 14, 2, 2,
|
||||||
|
{NO_WIRE, NO_WIRE, DW + ((W_NL1*4+0)|DIR_S0),
|
||||||
|
DW + W_NR1*4+3, DW + W_SL1*4+3, DW + W_SR1*4+3}},
|
||||||
|
|
||||||
|
{16, NO_WIRE, 0, 2, 2,
|
||||||
|
NO_WIRE, 14, 2, 3,
|
||||||
|
{DW + W_EL1*4+3, DW + W_ER1*4+3, DW + W_WL1*4+3,
|
||||||
|
DW + W_WR1*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
||||||
|
{16, NO_WIRE, 0, 0, 2,
|
||||||
|
NO_WIRE, 14, 0, 3,
|
||||||
|
{DW + W_SS2*4+3, DW + W_SW2*4+3, DW + W_NW2*4+3,
|
||||||
|
DW + ((W_WW2*4+2)|DIR_N3), DW + W_NE2*4+3, DW + W_NN2*4+3}},
|
||||||
|
{16, NO_WIRE, 0, 1, 2,
|
||||||
|
NO_WIRE, 14, 1, 3,
|
||||||
|
{NO_WIRE, NO_WIRE, DW + W_NL1*4+3,
|
||||||
|
DW + W_NR1*4+3, DW + W_SL1*4+3, DW + ((W_SR1*4+2)|DIR_N3)}},
|
||||||
|
|
||||||
|
{18, NO_WIRE, 0, 1, 3,
|
||||||
|
NO_WIRE, 14, 1, 2,
|
||||||
|
{DW + W_EL1*4+3, DW + ((W_ER1*4+2)|DIR_N3), DW + ((W_WL1*4+2)|DIR_N3),
|
||||||
|
DW + W_WR1*4+3, DW + W_EE2*4+3, DW + W_SE2*4+3}},
|
||||||
|
{18, NO_WIRE, 0, 0, 3,
|
||||||
|
NO_WIRE, 14, 0, 2,
|
||||||
|
{DW + ((W_SS2*4+2)|DIR_N3), DW + ((W_SW2*4+2)|DIR_N3), DW + W_NW2*4+3,
|
||||||
|
DW + ((W_WW2*4+2)|DIR_N3), DW + W_NE2*4+3, DW + W_NN2*4+3}},
|
||||||
|
{18, NO_WIRE, 0, 2, 3,
|
||||||
|
NO_WIRE, 14, 2, 2,
|
||||||
|
{NO_WIRE, NO_WIRE, DW + W_NL1*4+3,
|
||||||
|
DW + W_NR1*4+3, DW + W_SL1*4+3, DW + ((W_SR1*4+2)|DIR_N3)}}};
|
||||||
|
|
||||||
|
for (i = 0; i < 8; i++) {
|
||||||
|
for (j = 0; j < sizeof(src)/sizeof(*src); j++) {
|
||||||
|
|
||||||
|
int logicin_o = ((src[j].minor-12)/2)*LOGIN_MIP_ROWS*LOGIN_ROW;
|
||||||
|
logicin_o += i*LOGIN_ROW;
|
||||||
|
|
||||||
|
src[j].m0_sw_to = logicin_matrix[logicin_o+0];
|
||||||
|
src[j].m1_sw_to = logicin_matrix[logicin_o+1];
|
||||||
|
|
||||||
|
if (i) {
|
||||||
|
src[j].m0_two_bits_o += 16;
|
||||||
|
src[j].m0_one_bit_start += 16;
|
||||||
|
src[j].m1_two_bits_o += 16;
|
||||||
|
src[j].m1_one_bit_start += 16;
|
||||||
|
if (!(i%2)) // at 2, 4 and 6 we decrement the wires
|
||||||
|
for (k = 0; k < sizeof(src[0].from_w)/sizeof(src[0].from_w[0]); k++)
|
||||||
|
src[j].from_w[k] = wire_decrement(src[j].from_w[k]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
rc = src_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
src, sizeof(src)/sizeof(*src));
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// VCC/GND/GFAN, logicin and logicout sources
|
||||||
|
// mip12-14
|
||||||
|
{ int logicin_src[8][6] = {
|
||||||
|
{VCC_WIRE, LW + (LO_D|LD1), LW + LO_DQ, LW + (LO_BMUX|LD1), LOGICIN_S62, LOGICIN_S20},
|
||||||
|
{GFAN1, LW + (LO_D|LD1), LW + LO_DQ, LW + (LO_BMUX|LD1), LOGICIN_S62, LOGICIN_S20},
|
||||||
|
{VCC_WIRE, LW + LO_C, LW + (LO_CQ|LD1), LW + LO_AMUX, LOGICIN_S62, LW + (LI_AX|LD1)},
|
||||||
|
{GFAN1, LW + LO_C, LW + (LO_CQ|LD1), LW + LO_AMUX, LOGICIN_S62, LW + (LI_AX|LD1)},
|
||||||
|
{VCC_WIRE, LW + (LO_B|LD1), LW + LO_BQ, LW + (LO_DMUX|LD1), LW + (LI_AX|LD1), LW + (LI_CI|LD1)},
|
||||||
|
{GFAN0, LW + (LO_B|LD1), LW + LO_BQ, LW + (LO_DMUX|LD1), LW + (LI_AX|LD1), LW + (LI_CI|LD1)},
|
||||||
|
{VCC_WIRE, LW + LO_A, LW + (LO_AQ|LD1), LW + LO_CMUX, LOGICIN20, LW + (LI_CI|LD1)},
|
||||||
|
{GFAN0, LW + LO_A, LW + (LO_AQ|LD1), LW + LO_CMUX, LOGICIN20, LW + (LI_CI|LD1)},
|
||||||
|
};
|
||||||
|
|
||||||
|
rc = mip_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
12, 3, 2, 3, 3, &logicin_src);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
|
||||||
|
logicin_src[1][0] = logicin_src[3][0] = logicin_src[5][0] = logicin_src[7][0] = VCC_WIRE;
|
||||||
|
logicin_src[0][0] = logicin_src[2][0] = GFAN1;
|
||||||
|
logicin_src[4][0] = logicin_src[6][0] = GFAN0;
|
||||||
|
rc = mip_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
14, 3, 3, 3, 2, &logicin_src);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
}
|
||||||
|
{ int logicin_src[8][6] = {
|
||||||
|
{ LW + LI_BX, LOGICIN52 },
|
||||||
|
{ LW + LI_BX, LOGICIN52 },
|
||||||
|
{ LW + LI_BX, LW + (LI_DI|LD1) },
|
||||||
|
{ LW + LI_BX, LW + (LI_DI|LD1) },
|
||||||
|
{ LW + (LI_DI|LD1), LOGICIN_N28 },
|
||||||
|
{ LW + (LI_DI|LD1), LOGICIN_N28 },
|
||||||
|
{ LOGICIN_N52, LOGICIN_N28 },
|
||||||
|
{ LOGICIN_N52, LOGICIN_N28 }};
|
||||||
|
|
||||||
|
rc = mip_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
12, 1, 2, 1, 3, &logicin_src);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
rc = mip_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
14, 2, 3, 2, 2, &logicin_src);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
}
|
||||||
|
// mip16-18
|
||||||
|
{ int logicin_src[8][6] = {
|
||||||
|
{VCC_WIRE, LW + LO_D, LW + (LO_DQ|LD1), LW + LO_BMUX, LOGICIN_S36, LOGICIN_S44},
|
||||||
|
{GFAN1, LW + LO_D, LW + (LO_DQ|LD1), LW + LO_BMUX, LOGICIN_S36, LOGICIN_S44},
|
||||||
|
{VCC_WIRE, LW + (LO_C|LD1), LW + LO_CQ, LW + (LO_AMUX|LD1), LOGICIN_S36, LW + LI_AX},
|
||||||
|
{GFAN1, LW + (LO_C|LD1), LW + LO_CQ, LW + (LO_AMUX|LD1), LOGICIN_S36, LW + LI_AX},
|
||||||
|
{VCC_WIRE, LW + LO_B, LW + (LO_BQ|LD1), LW + LO_DMUX, LW + LI_AX, LW + (LI_CE|LD1)},
|
||||||
|
{GFAN0, LW + LO_B, LW + (LO_BQ|LD1), LW + LO_DMUX, LW + LI_AX, LW + (LI_CE|LD1)},
|
||||||
|
{VCC_WIRE, LW + (LO_A|LD1), LW + LO_AQ, LW + (LO_CMUX|LD1), LOGICIN44, LW + (LI_CE|LD1)},
|
||||||
|
{GFAN0, LW + (LO_A|LD1), LW + LO_AQ, LW + (LO_CMUX|LD1), LOGICIN44, LW + (LI_CE|LD1)},
|
||||||
|
};
|
||||||
|
|
||||||
|
rc = mip_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
16, 3, 2, 3, 3, &logicin_src);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
|
||||||
|
logicin_src[1][0] = logicin_src[3][0] = logicin_src[5][0] = logicin_src[7][0] = VCC_WIRE;
|
||||||
|
logicin_src[0][0] = logicin_src[2][0] = GFAN1;
|
||||||
|
logicin_src[4][0] = logicin_src[6][0] = GFAN0;
|
||||||
|
rc = mip_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
18, 3, 3, 3, 2, &logicin_src);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
}
|
||||||
|
{ int logicin_src[8][6] = {
|
||||||
|
{ LW + (LI_BX|LD1), LOGICIN21 },
|
||||||
|
{ LW + (LI_BX|LD1), LOGICIN21 },
|
||||||
|
{ LW + (LI_BX|LD1), FAN_B },
|
||||||
|
{ LW + (LI_BX|LD1), FAN_B },
|
||||||
|
{ FAN_B, LOGICIN_N60 },
|
||||||
|
{ FAN_B, LOGICIN_N60 },
|
||||||
|
{ LOGICIN_N21, LOGICIN_N60 },
|
||||||
|
{ LOGICIN_N21, LOGICIN_N60 }};
|
||||||
|
|
||||||
|
rc = mip_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
16, 1, 2, 1, 3, &logicin_src);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
rc = mip_to_bitpos(*bitpos, num_bitpos, MAX_SWITCHBOX_SIZE,
|
||||||
|
18, 2, 3, 2, 2, &logicin_src);
|
||||||
|
if (rc) FAIL(rc);
|
||||||
|
}
|
||||||
|
|
||||||
|
// minor 20 switches (SR, CLK, GFAN = 113 switches (4 bidir added on other side))
|
||||||
|
{ const struct sw_mip_src src[] = {
|
||||||
|
{20, SR1, 6, 3, 0, .from_w =
|
||||||
|
{GCLK11, GCLK10, GCLK13, GCLK12, GCLK9, GCLK8}},
|
||||||
|
{20, SR1, 6, 2, 0, .from_w =
|
||||||
|
{DW+W_WR1*4+2, DW+W_NR1*4+2, VCC_WIRE, GND_WIRE, DW+W_ER1*4+2, DW+W_SR1*4+2}},
|
||||||
|
{20, SR1, 6, 1, 0, .from_w =
|
||||||
|
{FAN_B, LW+(LI_DI|LD1), LW+(LI_BX|LD1), LW+LI_BX, GCLK15, GCLK14}},
|
||||||
|
|
||||||
|
{20, SR0, 8, 3, 10, .from_w =
|
||||||
|
{GCLK8, GCLK9, GCLK10, GCLK13, GCLK12, GCLK11}},
|
||||||
|
{20, SR0, 8, 2, 10, .from_w =
|
||||||
|
{GCLK14, GCLK15, LW+(LI_DI|LD1), LW+(LI_BX|LD1), LW+LI_BX, FAN_B}},
|
||||||
|
{20, SR0, 8, 1, 10, .from_w = {DW+W_SR1*4+2, DW+W_ER1*4+2, DW+W_NR1*4+2,
|
||||||
|
VCC_WIRE, NO_WIRE, DW+W_WR1*4+2}},
|
||||||
|
|
||||||
|
{20, CLK0, 16, 3, 18, .from_w =
|
||||||
|
{GCLK0, GCLK1, GCLK2, GCLK5, GCLK4, GCLK3}},
|
||||||
|
{20, CLK0, 16, 2, 18, .from_w =
|
||||||
|
{GCLK6, GCLK7, GCLK8, GCLK11, GCLK10, GCLK9}},
|
||||||
|
{20, CLK0, 16, 1, 18, .from_w =
|
||||||
|
{GCLK12, GCLK13, GCLK14, LW+(LI_BX|LD1), LW+(LI_CI|LD1), GCLK15}},
|
||||||
|
{20, CLK0, 16, 0, 18, .from_w =
|
||||||
|
{DW+W_NR1*4+2, DW+W_WR1*4+2, DW+W_SR1*4+1, VCC_WIRE, NO_WIRE, DW+W_ER1*4+1}},
|
||||||
|
|
||||||
|
{20, CLK1, 46, 3, 40, .from_w =
|
||||||
|
{GCLK3, GCLK2, GCLK5, GCLK4, GCLK1, GCLK0}},
|
||||||
|
{20, CLK1, 46, 2, 40, .from_w =
|
||||||
|
{GCLK15, GCLK14, LW+(LI_BX|LD1), LW+(LI_CI|LD1), GCLK13, GCLK12}},
|
||||||
|
{20, CLK1, 46, 1, 40, .from_w =
|
||||||
|
{GCLK9, GCLK8, GCLK11, GCLK10, GCLK7, GCLK6}},
|
||||||
|
{20, CLK1, 46, 0, 40, .from_w =
|
||||||
|
{DW+W_ER1*4+1, DW+W_SR1*4+1, VCC_WIRE, NO_WIRE, DW+W_WR1*4+2, DW+W_NR1*4+2}},
|
||||||
|
|
||||||
|
{20, GFAN0, 54, 3, 48, .from_w =
|
||||||
|
{GCLK3, GCLK4, GCLK5, GCLK2, GCLK1, GCLK0}},
|
||||||
|
{20, GFAN0, 54, 2, 48, .from_w =
|
||||||
|
{DW+W_WR1*4+1, GND_WIRE, VCC_WIRE, DW+W_NR1*4+1, DW+W_ER1*4+1, DW+W_SR1*4+1}},
|
||||||
|
{20, GFAN0, 54, 1, 48, .from_w =
|
||||||
|
{LW+(LI_CE|LD1), NO_WIRE, NO_WIRE, LW+(LI_CI|LD1), GCLK7, GCLK6}},
|
||||||
|
|
||||||
|
{20, GFAN1, 56, 3, 58, .from_w =
|
||||||
|
{GCLK0, GCLK1, GCLK4, GCLK5, GCLK2, GCLK3}},
|
||||||
|
{20, GFAN1, 56, 2, 58, .from_w =
|
||||||
|
{GCLK6, GCLK7, LW+(LI_AX|LD1), LW+LI_AX, NO_WIRE, NO_WIRE}},
|
||||||
|
{20, GFAN1, 56, 1, 58, .from_w =
|
||||||
|
{DW+W_SR1*4+1, DW+W_ER1*4+1, GND_WIRE, VCC_WIRE, DW+W_NR1*4+1, DW+W_WR1*4+1}}};
|
||||||
|
|
||||||
|
for (i = 0; i < sizeof(src)/sizeof(*src); i++) {
|
||||||
|
for (j = 0; j < sizeof(src[0].from_w)/sizeof(src[0].from_w[0]); j++) {
|
||||||
|
if (src[i].from_w[j] == NO_WIRE) continue;
|
||||||
|
|
||||||
|
if (*num_bitpos >= MAX_SWITCHBOX_SIZE) FAIL(EINVAL);
|
||||||
|
(*bitpos)[*num_bitpos].from = src[i].from_w[j];
|
||||||
|
(*bitpos)[*num_bitpos].to = src[i].m0_sw_to;
|
||||||
|
(*bitpos)[*num_bitpos].bidir = 0;
|
||||||
|
(*bitpos)[*num_bitpos].minor = 20;
|
||||||
|
(*bitpos)[*num_bitpos].two_bits_o = src[i].m0_two_bits_o;
|
||||||
|
(*bitpos)[*num_bitpos].two_bits_val = src[i].m0_two_bits_val;
|
||||||
|
(*bitpos)[*num_bitpos].one_bit_o = src[i].m0_one_bit_start + j;
|
||||||
|
(*num_bitpos)++;
|
||||||
|
}
|
||||||
|
}}
|
||||||
|
return 0;
|
||||||
|
fail:
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
void free_xc6_routing_bitpos(struct xc6_routing_bitpos* bitpos)
|
||||||
|
{
|
||||||
|
free(bitpos);
|
||||||
|
}
|
||||||
|
|
|
||||||
25
parts.h
25
parts.h
|
|
@ -46,3 +46,28 @@ enum major_type get_major_type(int idcode, int major);
|
||||||
|
|
||||||
int get_num_iobs(int idcode);
|
int get_num_iobs(int idcode);
|
||||||
const char* get_iob_sitename(int idcode, int idx);
|
const char* get_iob_sitename(int idcode, int idx);
|
||||||
|
|
||||||
|
// The routing bitpos is relative to a tile, i.e. major (x)
|
||||||
|
// and row/v64_i (y) are defined outside.
|
||||||
|
struct xc6_routing_bitpos
|
||||||
|
{
|
||||||
|
// from and to are enum extra_wires values from model.h
|
||||||
|
int from;
|
||||||
|
int to;
|
||||||
|
int bidir;
|
||||||
|
|
||||||
|
// minors 0-19 are minor pairs, minor will be set
|
||||||
|
// to the even beginning of the pair, two_bits_o and
|
||||||
|
// one_bit_o are within 2*64 bits of the two minors.
|
||||||
|
// Even bit offsets are from the first minor, odd bit
|
||||||
|
// offsets from the second minor.
|
||||||
|
// minor 20 is a regular single 64-bit minor.
|
||||||
|
|
||||||
|
int minor; // 0,2,4,..18 for pairs, 20 for single-minor
|
||||||
|
int two_bits_o; // 0-126 for pairs (even only), 0-62 for single-minor
|
||||||
|
int two_bits_val; // 0-3
|
||||||
|
int one_bit_o; // 1-6 positions up or down from two-bit pos
|
||||||
|
};
|
||||||
|
|
||||||
|
int get_xc6_routing_bitpos(struct xc6_routing_bitpos** bitpos, int* num_bitpos);
|
||||||
|
void free_xc6_routing_bitpos(struct xc6_routing_bitpos* bitpos);
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue
Block a user