more routing work
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25cb653c2e
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3249be1a28
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@ -176,8 +176,8 @@ int main(int argc, char** argv)
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_CQ);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C5);
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// fnet_add_port(&model, net, iob_led_y, iob_led_x, DEV_IOB,
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// iob_led_type_idx, IOB_IN_O);
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fnet_add_port(&model, net, iob_led_y, iob_led_x, DEV_IOB,
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iob_led_type_idx, IOB_IN_O);
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fnet_route(&model, net);
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write_floorplan(stdout, &model, FP_DEFAULT);
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@ -2536,6 +2536,12 @@ static int fpga_switch_2sets(struct fpga_model* model, int from_y, int from_x,
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construct_sw_conns(&conns, model, from_y, from_x, from_pt,
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SW_FROM, /*max_depth*/ 2, NO_NET);
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while (fpga_switch_conns(&conns) != NO_CONN) {
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#ifdef DBG_SWITCH_2SETS
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printf(" sw %s conn y%i-x%i-%s\n", fmt_swset(model, from_y,
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from_x, &conns.chain.set, SW_FROM),
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conns.dest_y, conns.dest_x,
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strarray_lookup(&model->str, conns.dest_str_i));
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#endif
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if (conns.dest_y != to_y
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|| conns.dest_x != to_x) continue;
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for (i = 0; i < to_switches.len; i++) {
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@ -2554,6 +2560,72 @@ static int fpga_switch_2sets(struct fpga_model* model, int from_y, int from_x,
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RC_RETURN(model);
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}
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static int fnet_dir_route(struct fpga_model* model, int from_y, int from_x,
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str16_t from_pt, int to_y, int to_x, str16_t to_pt, net_idx_t net_i)
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{
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struct sw_set from_set, to_set;
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struct switch_to_rel switch_to_rel;
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int dist;
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RC_CHECK(model);
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do {
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fpga_switch_2sets(model, from_y, from_x, from_pt, to_y, to_x, to_pt,
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&from_set, &to_set);
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RC_CHECK(model);
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if (from_set.len && to_set.len) {
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fnet_add_sw(model, net_i, from_y, from_x, from_set.sw, from_set.len);
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fnet_add_sw(model, net_i, to_y, to_x, to_set.sw, to_set.len);
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RC_RETURN(model);
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}
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dist = abs(to_y - from_y) + abs(to_x - from_x);
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// Go through all single-depth conns and try
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// switch_2sets from there.
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if (dist <= 4) {
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struct sw_conns sw_conns;
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construct_sw_conns(&sw_conns, model, from_y, from_x,
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from_pt, SW_FROM, /*max_depth*/ 1, net_i);
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RC_CHECK(model);
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while (fpga_switch_conns(&sw_conns) != NO_CONN) {
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if ((fpga_switch_first(model, sw_conns.dest_y, sw_conns.dest_x,
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sw_conns.dest_str_i, SW_FROM) == NO_SWITCH)
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|| (abs(sw_conns.dest_y - from_y) + abs(sw_conns.dest_x - from_x) >= dist))
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continue;
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fpga_switch_2sets(model, sw_conns.dest_y,
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sw_conns.dest_x, sw_conns.dest_str_i,
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to_y, to_x, to_pt, &from_set, &to_set);
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RC_CHECK(model);
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if (from_set.len && to_set.len) {
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fnet_add_sw(model, net_i, from_y, from_x, sw_conns.chain.set.sw, sw_conns.chain.set.len);
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fnet_add_sw(model, net_i, sw_conns.dest_y, sw_conns.dest_x, from_set.sw, from_set.len);
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fnet_add_sw(model, net_i, to_y, to_x, to_set.sw, to_set.len);
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destruct_sw_conns(&sw_conns);
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RC_RETURN(model);
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}
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}
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destruct_sw_conns(&sw_conns);
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}
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switch_to_rel.model = model;
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switch_to_rel.start_y = from_y;
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switch_to_rel.start_x = from_x;
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switch_to_rel.start_switch = from_pt;
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switch_to_rel.from_to = SW_FROM;
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switch_to_rel.flags = SWTO_REL_WEAK_TARGET;
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switch_to_rel.rel_y = to_y - from_y;
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switch_to_rel.rel_x = to_x - from_x;
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switch_to_rel.target_connpt = STRIDX_NO_ENTRY;
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fpga_switch_to_rel(&switch_to_rel);
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RC_ASSERT(model, switch_to_rel.set.len);
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fnet_add_sw(model, net_i, switch_to_rel.start_y, switch_to_rel.start_x,
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switch_to_rel.set.sw, switch_to_rel.set.len);
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from_y = switch_to_rel.dest_y;
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from_x = switch_to_rel.dest_x;
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from_pt = switch_to_rel.dest_connpt;
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} while (1);
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RC_RETURN(model);
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}
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static int fpga_switch_2sets_add(struct fpga_model* model, int from_y, int from_x,
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str16_t from_pt, int to_y, int to_x, str16_t to_pt, net_idx_t net_i)
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{
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@ -2804,7 +2876,7 @@ static int fnet_route_logic_to_iob(struct fpga_model *model, net_idx_t net_i, in
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switch_to_rel.set.len);
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// route from logic routing to ilogic routing
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fpga_switch_2sets_add(model, switch_to_rel.dest_y,
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fnet_dir_route(model, switch_to_rel.dest_y,
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switch_to_rel.dest_x, switch_to_rel.dest_connpt,
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switch_to_yx.dest_y, switch_to_yx.dest_x, switch_to_yx.dest_connpt,
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net_i);
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