From 4d576e55fded3b0cbfb7e04a426b699de84dd5b5 Mon Sep 17 00:00:00 2001 From: Wolfgang Spraul Date: Sun, 26 Aug 2012 09:13:02 +0200 Subject: [PATCH] minor fixes, slow Sunday... --- autotest.c | 17 ++------- control.c | 101 ++++++++++++++++++++++++++++++++++++++++------------ control.h | 2 ++ floorplan.c | 53 ++------------------------- model.h | 3 +- 5 files changed, 87 insertions(+), 89 deletions(-) diff --git a/autotest.c b/autotest.c index c4a34c0..0f9ca23 100644 --- a/autotest.c +++ b/autotest.c @@ -161,7 +161,8 @@ int main(int argc, char** argv) P48_dev->iob.suspend = SUSP_3STATE; // configure logic - logic_dev_idx = fpga_dev_idx(&model, /*y*/ 68, /*x*/ 13, DEV_LOGIC, DEV_LOGX); + logic_dev_idx = fpga_dev_idx(&model, /*y*/ 68, /*x*/ 13, + DEV_LOGIC, DEV_LOGX); if (logic_dev_idx == NO_DEV) FAIL(EINVAL); logic_dev = FPGA_DEV(&model, /*y*/ 68, /*x*/ 13, logic_dev_idx); logic_dev->instantiated = 1; @@ -182,8 +183,6 @@ int main(int argc, char** argv) logic_dev_idx, LOGIC_IN_D3); if (rc) FAIL(rc); -printf("P46 I pinw %s\n", strarray_lookup(&model.str, P46_dev->pinw[IOB_OUT_I])); - switch_to.yx_req = YX_DEV_ILOGIC; switch_to.flags = SWTO_YX_DEF; switch_to.model = &model; @@ -196,8 +195,6 @@ printf("P46 I pinw %s\n", strarray_lookup(&model.str, P46_dev->pinw[IOB_OUT_I])) switch_to.x, &switch_to.set); if (rc) FAIL(rc); -printf(" %s\n", fmt_swset(&model, switch_to.y, switch_to.x, &switch_to.set, SW_FROM)); - switch_to.yx_req = YX_ROUTING_TILE; switch_to.flags = SWTO_YX_DEF; switch_to.y = switch_to.dest_y; @@ -209,8 +206,6 @@ printf(" %s\n", fmt_swset(&model, switch_to.y, switch_to.x, &switch_to.set, SW_F switch_to.x, &switch_to.set); if (rc) FAIL(rc); -printf(" %s\n", fmt_swset(&model, switch_to.y, switch_to.x, &switch_to.set, SW_FROM)); - switch_to.yx_req = YX_ROUTING_TO_FABLOGIC; switch_to.flags = SWTO_YX_CLOSEST; switch_to.y = switch_to.dest_y; @@ -222,8 +217,6 @@ printf(" %s\n", fmt_swset(&model, switch_to.y, switch_to.x, &switch_to.set, SW_F switch_to.x, &switch_to.set); if (rc) FAIL(rc); -printf(" %s\n", fmt_swset(&model, switch_to.y, switch_to.x, &switch_to.set, SW_FROM)); - switch_to.yx_req = YX_DEV_LOGIC; switch_to.flags = SWTO_YX_TARGET_CONNPT|SWTO_YX_MAX_SWITCH_DEPTH; switch_to.y = switch_to.dest_y; @@ -248,8 +241,6 @@ printf(" %s\n", fmt_swset(&model, switch_to.y, switch_to.x, &switch_to.set, SW_F switch_to.x, &switch_to.set); if (rc) FAIL(rc); -printf(" %s\n", fmt_swset(&model, switch_to.y, switch_to.x, &switch_to.set, SW_FROM)); - { struct sw_chain c = { .model = &model, .y = switch_to.dest_y, @@ -260,15 +251,11 @@ printf(" %s\n", fmt_swset(&model, switch_to.y, switch_to.x, &switch_to.set, SW_F if (c.set.len == 0) { HERE(); FAIL(EINVAL); } rc = fpga_net_add_switches(&model, P46_net, c.y, c.x, &c.set); if (rc) FAIL(rc); -printf(" %s\n", fmt_swset(&model, c.y, c.x, &c.set, SW_FROM)); } rc = diff_printf(&tstate); if (rc) FAIL(rc); - printf("\n"); - printf("P48 O pinw %s\n", strarray_lookup(&model.str, P48_dev->pinw[IOB_IN_O])); - printf("\n"); printf("O Test suite completed.\n"); TIME_AND_MEM(); diff --git a/control.c b/control.c index d1f2666..324699b 100644 --- a/control.c +++ b/control.c @@ -846,24 +846,25 @@ int fpga_switch_to_yx(struct switch_to_yx* p) static int fpga_net_useidx(struct fpga_model* model, net_idx_t new_idx) { - int rc; + void* new_ptr; + int new_array_size, rc; if (new_idx <= NO_NET) FAIL(EINVAL); - if ((new_idx-1) < model->num_nets) - return 0; - if ((new_idx-1) >= (model->num_nets+NET_ALLOC_INCREMENT-1) - /NET_ALLOC_INCREMENT*NET_ALLOC_INCREMENT) { - void* new_ptr; - int new_len; + if (new_idx > model->highest_used_net) + model->highest_used_net = new_idx; - new_len = ((new_idx-1)/NET_ALLOC_INCREMENT+1) - *NET_ALLOC_INCREMENT*sizeof(*model->nets); - new_ptr = realloc(model->nets, new_len); - if (!new_ptr) FAIL(ENOMEM); - model->nets = new_ptr; - } - model->nets[(new_idx-1)].len = 0; - model->num_nets++; + if ((new_idx-1) < model->nets_array_size) + return 0; + + new_array_size = ((new_idx-1)/NET_ALLOC_INCREMENT+1)*NET_ALLOC_INCREMENT; + new_ptr = realloc(model->nets, new_array_size*sizeof(*model->nets)); + if (!new_ptr) FAIL(ENOMEM); + // the memset will set the 'len' of each new net to 0 + memset(new_ptr + model->nets_array_size*sizeof(*model->nets), 0, + (new_array_size - model->nets_array_size)*sizeof(*model->nets)); + + model->nets = new_ptr; + model->nets_array_size = new_array_size; return 0; fail: return rc; @@ -873,10 +874,10 @@ int fpga_net_new(struct fpga_model* model, net_idx_t* new_idx) { int rc; - rc = fpga_net_useidx(model, model->num_nets+1); + // highest_used_net is initialized to NO_NET which becomes 1 + rc = fpga_net_useidx(model, model->highest_used_net+1); if (rc) return rc; - *new_idx = model->num_nets+1; - model->num_nets++; + *new_idx = model->highest_used_net; return 0; } @@ -885,7 +886,7 @@ int fpga_net_enum(struct fpga_model* model, net_idx_t last, net_idx_t* next) int i; // last can be NO_NET which becomes 1 = the first net index - for (i = last+1; i <= model->num_nets; i++) { + for (i = last+1; i <= model->highest_used_net; i++) { if (model->nets[i-1].len) { *next = i; return 0; @@ -898,9 +899,9 @@ int fpga_net_enum(struct fpga_model* model, net_idx_t last, net_idx_t* next) struct fpga_net* fpga_net_get(struct fpga_model* model, net_idx_t net_i) { if (net_i <= NO_NET - || net_i > model->num_nets) { - fprintf(stderr, "%s:%i net_i %i num_nets %i\n", __FILE__, - __LINE__, net_i, model->num_nets); + || net_i > model->highest_used_net) { + fprintf(stderr, "%s:%i net_i %i highest_used %i\n", __FILE__, + __LINE__, net_i, model->highest_used_net); return 0; } return &model->nets[net_i-1]; @@ -959,5 +960,59 @@ void fpga_net_free_all(struct fpga_model* model) { free(model->nets); model->nets = 0; - model->num_nets = 0; + model->nets_array_size = 0; + model->highest_used_net = 0; +} + +static void fprintf_inout_pin(FILE* f, struct fpga_model* model, + net_idx_t net_i, struct net_el* el) +{ + struct fpga_tile* tile; + pinw_idx_t pinw_i; + dev_idx_t dev_idx; + int in_pin; + const char* pin_str; + char buf[1024]; + + if (!(el->idx & NET_IDX_IS_PINW)) + { HERE(); return; } + + tile = YX_TILE(model, el->y, el->x); + dev_idx = el->dev_idx; + if (dev_idx < 0 || dev_idx >= tile->num_devs) + { HERE(); return; } + pinw_i = el->idx & NET_IDX_MASK; + if (pinw_i < 0 || pinw_i >= tile->devs[dev_idx].num_pinw_total) + { HERE(); return; } + in_pin = pinw_i < tile->devs[dev_idx].num_pinw_in; + + pin_str = fpgadev_pinw_idx2str(tile->devs[dev_idx].type, pinw_i); + if (!pin_str) { HERE(); return; } + + snprintf(buf, sizeof(buf), "net %i %s y%02i x%02i %s %i pin %s\n", + net_i, in_pin ? "in" : "out", el->y, el->x, + fpgadev_str(tile->devs[dev_idx].type), + fpga_dev_typeidx(model, el->y, el->x, dev_idx), + pin_str); + fprintf(f, buf); +} + +void fprintf_net(FILE* f, struct fpga_model* model, net_idx_t net_i) +{ + struct fpga_net* net; + int i; + + net = fpga_net_get(model, net_i); + if (!net) { HERE(); return; } + for (i = 0; i < net->len; i++) { + if (net->el[i].idx & NET_IDX_IS_PINW) { + fprintf_inout_pin(f, model, net_i, &net->el[i]); + continue; + } + // switch + fprintf(f, "net %i sw y%02i x%02i %s\n", + net_i, net->el[i].y, net->el[i].x, + fpga_switch_print(model, net->el[i].y, + net->el[i].x, net->el[i].idx)); + } } diff --git a/control.h b/control.h index c8eda95..e66dd76 100644 --- a/control.h +++ b/control.h @@ -218,3 +218,5 @@ int fpga_net_add_port(struct fpga_model* model, net_idx_t net_i, int fpga_net_add_switches(struct fpga_model* model, net_idx_t net_i, int y, int x, const struct sw_set* set); void fpga_net_free_all(struct fpga_model* model); + +void fprintf_net(FILE* f, struct fpga_model* model, net_idx_t net_i); diff --git a/floorplan.c b/floorplan.c index 3945fd7..617b3f4 100644 --- a/floorplan.c +++ b/floorplan.c @@ -548,61 +548,14 @@ int printf_switches(FILE* f, struct fpga_model* model) return 0; } -static void printf_inout_pin(FILE* f, struct fpga_model* model, - net_idx_t net_i, struct net_el* el) -{ - struct fpga_tile* tile; - pinw_idx_t pinw_i; - dev_idx_t dev_idx; - int in_pin; - const char* pin_str; - char buf[1024]; - - if (!(el->idx & NET_IDX_IS_PINW)) - { HERE(); return; } - - tile = YX_TILE(model, el->y, el->x); - dev_idx = el->dev_idx; - if (dev_idx < 0 || dev_idx >= tile->num_devs) - { HERE(); return; } - pinw_i = el->idx & NET_IDX_MASK; - if (pinw_i < 0 || pinw_i >= tile->devs[dev_idx].num_pinw_total) - { HERE(); return; } - in_pin = pinw_i < tile->devs[dev_idx].num_pinw_in; - - pin_str = fpgadev_pinw_idx2str(tile->devs[dev_idx].type, pinw_i); - if (!pin_str) { HERE(); return; } - - snprintf(buf, sizeof(buf), "net %i %s y%02i x%02i %s %i pin %s\n", - net_i, in_pin ? "in" : "out", el->y, el->x, - fpgadev_str(tile->devs[dev_idx].type), - fpga_dev_typeidx(model, el->y, el->x, dev_idx), - pin_str); - fprintf(f, buf); -} - int printf_nets(FILE* f, struct fpga_model* model) { net_idx_t net_i; - struct fpga_net* net; - int i, rc; + int rc; net_i = NO_NET; - while (!(rc = fpga_net_enum(model, net_i, &net_i)) && net_i != NO_NET) { - net = fpga_net_get(model, net_i); - if (!net) FAIL(rc); - for (i = 0; i < net->len; i++) { - if (net->el[i].idx & NET_IDX_IS_PINW) { - printf_inout_pin(f, model, net_i, &net->el[i]); - continue; - } - // switch - fprintf(f, "net %i sw y%02i x%02i %s\n", - net_i, net->el[i].y, net->el[i].x, - fpga_switch_print(model, net->el[i].y, - net->el[i].x, net->el[i].idx)); - } - } + while (!(rc = fpga_net_enum(model, net_i, &net_i)) && net_i != NO_NET) + fprintf_net(f, model, net_i); if (rc) FAIL(rc); return 0; fail: diff --git a/model.h b/model.h index cf07f18..81821b0 100644 --- a/model.h +++ b/model.h @@ -75,7 +75,8 @@ struct fpga_model struct fpga_tile* tiles; struct hashed_strarray str; - int num_nets; + int nets_array_size; + int highest_used_net; // 1-based net_idx_t struct fpga_net* nets; // tmp_str will be allocated to hold max(x_width, y_height)