diff --git a/model.c b/model.c
index 4481f85..a79b3e7 100644
--- a/model.c
+++ b/model.c
@@ -136,6 +136,92 @@ static int init_devices(struct fpga_model* model)
 	int x, y, i, j;
 	struct fpga_tile* tile;
 
+	// DCM, PLL_ADV
+	for (i = 0; i < model->cfg_rows; i++) {
+		y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
+		if (y > model->center_y) y++; // central regs
+		tile = YX_TILE(model, y-1, model->center_x-CMTPLL_FROM_CENTER_O);
+		if (i%2) {
+			tile->devices[tile->num_devices++].type = DEV_DCM;
+			tile->devices[tile->num_devices++].type = DEV_DCM;
+		} else
+			tile->devices[tile->num_devices++].type = DEV_PLL_ADV;
+	}
+
+	// BSCAN
+	tile = YX_TILE(model, TOP_IO_TILES, model->x_width-RIGHT_IO_DEVS_O);
+	tile->devices[tile->num_devices++].type = DEV_BSCAN;
+	tile->devices[tile->num_devices++].type = DEV_BSCAN;
+
+	// BSCAN, OCT_CALIBRATE
+	tile = YX_TILE(model, TOP_IO_TILES+1, model->x_width-RIGHT_IO_DEVS_O);
+	tile->devices[tile->num_devices++].type = DEV_BSCAN;
+	tile->devices[tile->num_devices++].type = DEV_BSCAN;
+	tile->devices[tile->num_devices++].type = DEV_OCT_CALIBRATE;
+
+	// ICAP, SPI_ACCESS, OCT_CALIBRATE
+	tile = YX_TILE(model, model->y_height-BOT_IO_TILES-1,
+		model->x_width-RIGHT_IO_DEVS_O);
+	tile->devices[tile->num_devices++].type = DEV_ICAP;
+	tile->devices[tile->num_devices++].type = DEV_SPI_ACCESS;
+	tile->devices[tile->num_devices++].type = DEV_OCT_CALIBRATE;
+
+	// STARTUP, POST_CRC_INTERNAL, SLAVE_SPI, SUSPEND_SYNC
+	tile = YX_TILE(model, model->y_height-BOT_IO_TILES-2,
+		model->x_width-RIGHT_IO_DEVS_O);
+	tile->devices[tile->num_devices++].type = DEV_STARTUP;
+	tile->devices[tile->num_devices++].type = DEV_POST_CRC_INTERNAL;
+	tile->devices[tile->num_devices++].type = DEV_SLAVE_SPI;
+	tile->devices[tile->num_devices++].type = DEV_SUSPEND_SYNC;
+
+	// BUFGMUX
+	tile = YX_TILE(model, model->center_y, model->center_x);
+	for (i = 0; i < 16; i++)
+		tile->devices[tile->num_devices++].type = DEV_BUFGMUX;
+
+	// BUFIO, BUFIO_FB, BUFPLL, BUFPLL_MCB
+	tile = YX_TILE(model, TOP_OUTER_ROW, model->center_x-CMTPLL_FROM_CENTER_O);
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL;
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL;
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
+	for (j = 0; j < 8; j++) {
+		tile->devices[tile->num_devices++].type = DEV_BUFIO;
+		tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
+	}
+	tile = YX_TILE(model, model->center_y, LEFT_OUTER_COL);
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL;
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL;
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
+	for (j = 0; j < 8; j++) {
+		tile->devices[tile->num_devices++].type = DEV_BUFIO;
+		tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
+	}
+	tile = YX_TILE(model, model->center_y, model->x_width - RIGHT_OUTER_O);
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL;
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL;
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
+	for (j = 0; j < 8; j++) {
+		tile->devices[tile->num_devices++].type = DEV_BUFIO;
+		tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
+	}
+	tile = YX_TILE(model, model->y_height - BOT_OUTER_ROW, model->center_x-CMTPLL_FROM_CENTER_O);
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL;
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL;
+	tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
+	for (j = 0; j < 8; j++) {
+		tile->devices[tile->num_devices++].type = DEV_BUFIO;
+		tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
+	}
+	
+	// BUFH
+	for (i = 0; i < model->cfg_rows; i++) {
+		y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
+		if (y > model->center_y) y++; // central regs
+		tile = YX_TILE(model, y, model->center_x);
+		for (j = 0; j < 32; j++)
+			tile->devices[tile->num_devices++].type = DEV_BUFH;
+	}
+
 	// BRAM
 	for (x = 0; x < model->x_width; x++) {
 		if (is_atx(X_FABRIC_BRAM_COL, model, x)) {
@@ -513,10 +599,10 @@ static int init_wires(struct fpga_model* model)
 {
 	int rc;
 
-	rc = run_gclk(model);
+	rc = run_logic_inout(model);
 	if (rc) goto xout;
 
-	rc = run_logic_inout(model);
+	rc = run_gclk(model);
 	if (rc) goto xout;
 
 	rc = run_direction_wires(model);
@@ -1162,7 +1248,7 @@ static int run_logic_inout(struct fpga_model* model)
 				}
 			}
 		}
-		if (is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) {
+		if (is_atx(X_FABRIC_BRAM_ROUTING_COL|X_FABRIC_MACC_ROUTING_COL, model, x)) {
 			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
 				if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
 						model, y))
@@ -1174,6 +1260,52 @@ static int run_logic_inout(struct fpga_model* model)
 					if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "BRAM_LOGICOUT%i_INT1", 0))) goto xout;
 					if ((rc = add_conn_range(model, NOPREF_BI_F, y, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "BRAM_LOGICOUT%i_INT0", 0))) goto xout;
 				}
+				if (YX_TILE(model, y, x)[2].flags & TF_MACC_DEV) {
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y-3, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "MACC_LOGICOUT%i_INT3", 0))) goto xout;
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y-2, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "MACC_LOGICOUT%i_INT2", 0))) goto xout;
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "MACC_LOGICOUT%i_INT1", 0))) goto xout;
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "MACC_LOGICOUT%i_INT0", 0))) goto xout;
+				}
+			}
+		}
+		if (is_atx(X_CENTER_ROUTING_COL, model, x)) {
+			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
+				if (is_aty(Y_ROW_HORIZ_AXSYMM, model, y)) {
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x, "LOGICOUT%i", 0, 23, y-1, x+1, "INT_INTERFACE_LOGICOUT%i", 0))) goto xout;
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y+1, x, "LOGICOUT%i", 0, 23, y+1, x+1, "INT_INTERFACE_LOGICOUT%i", 0))) goto xout;
+					if (YX_TILE(model, y-1, x+2)->flags & TF_DCM_DEV) {
+						if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y-1, x+2, "DCM_CLB2_LOGICOUT%i", 0))) goto xout;
+						if ((rc = add_conn_range(model, NOPREF_BI_F, y+1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y-1, x+2, "DCM_CLB1_LOGICOUT%i", 0))) goto xout;
+					} else if (YX_TILE(model, y-1, x+2)->flags & TF_PLL_DEV) {
+						if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y-1, x+2, "PLL_CLB2_LOGICOUT%i", 0))) goto xout;
+						if ((rc = add_conn_range(model, NOPREF_BI_F, y+1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y-1, x+2, "PLL_CLB1_LOGICOUT%i", 0))) goto xout;
+					}
+				}
+				if (is_aty(Y_CHIP_HORIZ_REGS, model, y)) {
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x, "LOGICOUT%i", 0, 23, y-1, x+1, "INT_INTERFACE_REGC_LOGICOUT%i", 0))) goto xout;
+				}
+			}
+		}
+		if (is_atx(X_LEFT_IO_ROUTING_COL|X_RIGHT_IO_ROUTING_COL, model, x)) {
+			int wired_side, local_size;
+			if (is_atx(X_LEFT_IO_ROUTING_COL, model, x)) {
+				local_size = 1;
+				wired_side = Y_LEFT_WIRED;
+			} else {
+				local_size = 2;
+				wired_side = Y_RIGHT_WIRED;
+			}
+			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
+				if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
+						model, y))
+					continue;
+				if (y < TOP_IO_TILES+local_size || y > model->y_height-BOT_IO_TILES-local_size-1) {
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICOUT%i", 0, 23, y, x+1, "INT_INTERFACE_LOCAL_LOGICOUT%i", 0))) goto xout;
+				} else if (is_aty(wired_side, model, y)) {
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICOUT%i", 0, 23, y, x+1, "IOI_LOGICOUT%i", 0))) goto xout;
+				} else {
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICOUT%i", 0, 23, y, x+1, "INT_INTERFACE_LOGICOUT%i", 0))) goto xout;
+				}
 			}
 		}
 	}
diff --git a/model.h b/model.h
index 7379a39..4d10c14 100644
--- a/model.h
+++ b/model.h
@@ -138,11 +138,12 @@ enum fpga_tile_type
 #define TOP_IO_TILES		2
 #define TOP_OUTER_ROW		0
 #define TOP_INNER_ROW		1
-#define BOT_IO_TILES		2
 #define HALF_ROW		8
 #define LAST_POS_IN_ROW		16 // including hclk at 8
+#define ROW_SIZE		(HALF_ROW+1+HALF_ROW)
 
 // Some offsets that are being deducted from their origin
+#define BOT_IO_TILES		2
 #define BOT_OUTER_ROW		1
 #define BOT_INNER_ROW		2
 #define RIGHT_OUTER_O		1
@@ -244,7 +245,23 @@ enum fpgadev_type
 	DEV_OLOGIC,
 	DEV_IODELAY,
 	DEV_BRAM16,
-	DEV_BRAM8
+	DEV_BRAM8,
+	DEV_BUFH,
+	DEV_BUFIO,
+	DEV_BUFIO_FB,
+	DEV_BUFPLL,
+	DEV_BUFPLL_MCB,
+	DEV_BUFGMUX,
+	DEV_BSCAN,
+	DEV_DCM,
+	DEV_PLL_ADV,
+	DEV_ICAP,
+	DEV_POST_CRC_INTERNAL,
+	DEV_STARTUP,
+	DEV_SLAVE_SPI,
+	DEV_SUSPEND_SYNC,
+	DEV_OCT_CALIBRATE,
+	DEV_SPI_ACCESS
 };
 
 struct fpgadev_logic_x
diff --git a/new_fp.c b/new_fp.c
index 2b10e0e..3a14350 100644
--- a/new_fp.c
+++ b/new_fp.c
@@ -158,6 +158,54 @@ int printf_devices(struct fpga_model* model)
 					case DEV_BRAM8:
 						printf("device y%02i x%02i RAMB8BWER\n", y, x);
 						break;
+					case DEV_BUFH:
+						printf("device y%02i x%02i BUFH\n", y, x);
+						break;
+					case DEV_BUFIO:
+						printf("device y%02i x%02i BUFIO2\n", y, x);
+						break;
+					case DEV_BUFIO_FB:
+						printf("device y%02i x%02i BUFIO2FB\n", y, x);
+						break;
+					case DEV_BUFPLL:
+						printf("device y%02i x%02i BUFPLL\n", y, x);
+						break;
+					case DEV_BUFPLL_MCB:
+						printf("device y%02i x%02i BUFPLL_MCB\n", y, x);
+						break;
+					case DEV_BUFGMUX:
+						printf("device y%02i x%02i BUFGMUX\n", y, x);
+						break;
+					case DEV_BSCAN:
+						printf("device y%02i x%02i BSCAN\n", y, x);
+						break;
+					case DEV_DCM:
+						printf("device y%02i x%02i DCM\n", y, x);
+						break;
+					case DEV_PLL_ADV:
+						printf("device y%02i x%02i PLL_ADV\n", y, x);
+						break;
+					case DEV_ICAP:
+						printf("device y%02i x%02i ICAP\n", y, x);
+						break;
+					case DEV_POST_CRC_INTERNAL:
+						printf("device y%02i x%02i POST_CRC_INTERNAL\n", y, x);
+						break;
+					case DEV_STARTUP:
+						printf("device y%02i x%02i STARTUP\n", y, x);
+						break;
+					case DEV_SLAVE_SPI:
+						printf("device y%02i x%02i SLAVE_SPI\n", y, x);
+						break;
+					case DEV_SUSPEND_SYNC:
+						printf("device y%02i x%02i SUSPEND_SYNC\n", y, x);
+						break;
+					case DEV_OCT_CALIBRATE:
+						printf("device y%02i x%02i OCT_CALIBRATE\n", y, x);
+						break;
+					case DEV_SPI_ACCESS:
+						printf("device y%02i x%02i SPI_ACCESS\n", y, x);
+						break;
 				}
 			}
 		}