better iologic switch support
This commit is contained in:
Wolfgang Spraul
parent
99a855dddd
commit
62db4b6911
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@ -611,31 +611,280 @@ static int find_bitpos(struct fpga_model* model, int y, int x, swidx_t sw)
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return -1;
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}
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static int write_routing_sw(struct fpga_bits* bits, struct fpga_model* model, int y, int x)
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{
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struct fpga_tile* tile;
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int i, bit_pos, rc;
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// go through enabled switches, lookup in sw_bitpos
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// and set bits
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tile = YX_TILE(model, y, x);
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for (i = 0; i < tile->num_switches; i++) {
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if (!(tile->switches[i] & SWITCH_USED))
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continue;
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bit_pos = find_bitpos(model, y, x, i);
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if (bit_pos == -1) {
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HERE();
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continue;
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}
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rc = bitpos_set_bits(bits, model, y, x,
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&model->sw_bitpos[bit_pos]);
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if (rc) FAIL(rc);
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}
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return 0;
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fail:
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return rc;
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}
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#define MAX_IOLOGIC_SWBLOCK 4
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#define MAX_IOLOGIC_BITS 4
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struct iologic_sw_pos
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{
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const char* to[MAX_IOLOGIC_SWBLOCK];
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const char* from[MAX_IOLOGIC_SWBLOCK];
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int minor[MAX_IOLOGIC_BITS];
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int b64[MAX_IOLOGIC_BITS];
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};
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struct iologic_sw_pos s_left_io_swpos[] = { {{0}} };
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struct iologic_sw_pos s_right_io_swpos[] = { {{0}} };
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struct iologic_sw_pos s_top_outer_io_swpos[] = { {{0}} };
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struct iologic_sw_pos s_top_inner_io_swpos[] = { {{0}} };
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struct iologic_sw_pos s_bot_inner_io_swpos[] =
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{
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// input
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{{"D_ILOGIC_IDATAIN_IODELAY_S"}, {"BIOI_INNER_IBUF0"},
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{23, 23, -1},
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{28, 29}},
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{{"D_ILOGIC_SITE"}, {"D_ILOGIC_IDATAIN_IODELAY"}, {26, -1}, {20}},
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{{"D_ILOGIC_SITE_S"}, {"D_ILOGIC_IDATAIN_IODELAY_S"}, {26, -1}, {23}},
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{{"DFB_ILOGIC_SITE"}, {"D_ILOGIC_SITE"}, {28, -1}, {63}},
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{{"DFB_ILOGIC_SITE_S"}, {"D_ILOGIC_SITE_S"}, {28, -1}, {0}},
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{{"FABRICOUT_ILOGIC_SITE"}, {"D_ILOGIC_SITE"}, {29, -1}, {49}},
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{{"FABRICOUT_ILOGIC_SITE_S"}, {"D_ILOGIC_SITE_S"}, {29, -1}, {14}},
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// output
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{{"OQ_OLOGIC_SITE", "BIOI_INNER_O0"},
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{"D1_OLOGIC_SITE", "OQ_OLOGIC_SITE"},
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{26, 27, 28, -1},
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{40, 21, 57}},
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{{"OQ_OLOGIC_SITE_S", "BIOI_INNER_O1"},
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{"D1_OLOGIC_SITE_S", "OQ_OLOGIC_SITE_S"},
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{26, 27, 28, -1},
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{43, 56, 6}},
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{{"IOI_LOGICOUT0"}, {"IOI_INTER_LOGICOUT0"}, {-1}},
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{{"IOI_LOGICOUT7"}, {"IOI_INTER_LOGICOUT7"}, {-1}},
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{{"IOI_INTER_LOGICOUT0"}, {"FABRICOUT_ILOGIC_SITE"}, {-1}},
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{{"IOI_INTER_LOGICOUT7"}, {"FABRICOUT_ILOGIC_SITE_S"}, {-1}},
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{{"D_ILOGIC_IDATAIN_IODELAY"}, {"BIOI_INNER_IBUF0"}, {-1}},
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{{"D_ILOGIC_IDATAIN_IODELAY_S"}, {"BIOI_INNER_IBUF1"}, {-1}},
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{{"D1_OLOGIC_SITE"}, {"IOI_LOGICINB31"}, {-1}},
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{{0}}
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};
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struct iologic_sw_pos s_bot_outer_io_swpos[] =
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{
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// input
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{{"D_ILOGIC_IDATAIN_IODELAY_S"}, {"BIOI_OUTER_IBUF0"},
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{23, 23, -1},
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{28, 29}},
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{{"D_ILOGIC_SITE"}, {"D_ILOGIC_IDATAIN_IODELAY"}, {26, -1}, {20}},
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{{"D_ILOGIC_SITE_S"}, {"D_ILOGIC_IDATAIN_IODELAY_S"}, {26, -1}, {23}},
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{{"DFB_ILOGIC_SITE"}, {"D_ILOGIC_SITE"}, {28, -1}, {63}},
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{{"DFB_ILOGIC_SITE_S"}, {"D_ILOGIC_SITE_S"}, {28, -1}, {0}},
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{{"FABRICOUT_ILOGIC_SITE"}, {"D_ILOGIC_SITE"}, {29, -1}, {49}},
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{{"FABRICOUT_ILOGIC_SITE_S"}, {"D_ILOGIC_SITE_S"}, {29, -1}, {14}},
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// output
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{{"OQ_OLOGIC_SITE", "BIOI_OUTER_O0"},
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{"D1_OLOGIC_SITE", "OQ_OLOGIC_SITE"},
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{26, 27, 28, -1},
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{40, 21, 57}},
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{{"OQ_OLOGIC_SITE_S", "BIOI_OUTER_O1"},
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{"D1_OLOGIC_SITE_S", "OQ_OLOGIC_SITE_S"},
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{26, 27, 28, -1},
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{43, 56, 6}},
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{{"OQ_OLOGIC_SITE", "BIOI_OUTER_O0"},
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{"D1_OLOGIC_SITE", "OQ_OLOGIC_SITE"},
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{26, 27, 28, -1},
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{40, 21, 57}},
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{{"IOI_LOGICOUT0"}, {"IOI_INTER_LOGICOUT0"}, {-1}},
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{{"IOI_LOGICOUT7"}, {"IOI_INTER_LOGICOUT7"}, {-1}},
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{{"IOI_INTER_LOGICOUT0"}, {"FABRICOUT_ILOGIC_SITE"}, {-1}},
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{{"IOI_INTER_LOGICOUT7"}, {"FABRICOUT_ILOGIC_SITE_S"}, {-1}},
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{{"D_ILOGIC_IDATAIN_IODELAY"}, {"BIOI_INNER_IBUF0"}, {-1}},
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{{"D_ILOGIC_IDATAIN_IODELAY_S"}, {"BIOI_INNER_IBUF1"}, {-1}},
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{{"D1_OLOGIC_SITE"}, {"IOI_LOGICINB31"}, {-1}},
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{{0}}
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};
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struct str_sw
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{
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const char* from_str;
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const char* to_str;
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};
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static int get_used_switches(struct fpga_model* model, int y, int x,
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struct str_sw** str_sw, int* num_sw)
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{
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int i, num_used, rc;
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struct fpga_tile* tile;
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tile = YX_TILE(model, y, x);
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num_used = 0;
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for (i = 0; i < tile->num_switches; i++) {
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if (tile->switches[i] & SWITCH_USED)
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num_used++;
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}
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if (!num_used) {
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*num_sw = 0;
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*str_sw = 0;
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return 0;
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}
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*str_sw = malloc(num_used * sizeof(**str_sw));
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if (!(*str_sw)) FAIL(ENOMEM);
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*num_sw = 0;
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for (i = 0; i < tile->num_switches; i++) {
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if (!(tile->switches[i] & SWITCH_USED))
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continue;
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(*str_sw)[*num_sw].from_str =
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fpga_switch_str(model, y, x, i, SW_FROM);
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(*str_sw)[*num_sw].to_str =
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fpga_switch_str(model, y, x, i, SW_TO);
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(*num_sw)++;
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}
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return 0;
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fail:
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return rc;
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}
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// returns the number of found to-from pairs from search_sw that
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// were found in the str_sw array, but only if all of the to-from
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// pairs in search_sw were found. The found array then contains
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// the indices into str_sw were the matches were made.
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// If not all to-from pairs were found (or none), returns 0.
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static int find_switches(struct iologic_sw_pos* search_sw,
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struct str_sw* str_sw, int num_str_sw, int (*found)[MAX_IOLOGIC_SWBLOCK])
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{
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int i, j;
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for (i = 0; i < MAX_IOLOGIC_SWBLOCK && search_sw->to[i]; i++) {
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for (j = 0; j < num_str_sw; j++) {
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if (!str_sw[j].to_str)
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continue;
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if (strcmp(str_sw[j].to_str, search_sw->to[i])
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|| strcmp(str_sw[j].from_str, search_sw->from[i]))
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continue;
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(*found)[i] = j;
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break;
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}
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if (j >= num_str_sw)
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return 0;
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}
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return i;
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}
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static int write_iologic_sw(struct fpga_bits* bits, struct fpga_model* model,
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int y, int x)
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{
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int i, j, row_num, row_pos, start_in_frame, rc;
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struct iologic_sw_pos* sw_pos;
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struct str_sw* str_sw;
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int found_i[MAX_IOLOGIC_SWBLOCK];
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int num_sw, num_found;
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if (x < LEFT_SIDE_WIDTH) {
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if (x != LEFT_IO_DEVS) FAIL(EINVAL);
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sw_pos = s_left_io_swpos;
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} else if (x >= model->x_width-RIGHT_SIDE_WIDTH) {
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if (x != model->x_width - RIGHT_IO_DEVS_O) FAIL(EINVAL);
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sw_pos = s_right_io_swpos;
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} else if (y == TOP_OUTER_IO)
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sw_pos = s_top_outer_io_swpos;
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else if (y == TOP_INNER_IO)
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sw_pos = s_top_inner_io_swpos;
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else if (y == model->y_height-BOT_INNER_IO)
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sw_pos = s_bot_inner_io_swpos;
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else if (y == model->y_height-BOT_OUTER_IO)
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sw_pos = s_bot_outer_io_swpos;
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else FAIL(EINVAL);
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is_in_row(model, y, &row_num, &row_pos);
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if (row_num == -1 || row_pos == -1
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|| row_pos == HCLK_POS) FAIL(EINVAL);
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if (row_pos > HCLK_POS)
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start_in_frame = (row_pos-1)*64 + 16;
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else
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start_in_frame = row_pos*64;
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rc = get_used_switches(model, y, x, &str_sw, &num_sw);
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if (rc) FAIL(rc);
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for (i = 0; sw_pos[i].to[0]; i++) {
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if (!(num_found = find_switches(&sw_pos[i], str_sw,
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num_sw, &found_i))) continue;
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for (j = 0; sw_pos[i].minor[j] != -1; j++) {
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set_bit(bits, row_num, model->x_major[x],
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sw_pos[i].minor[j], start_in_frame
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+ sw_pos[i].b64[j]);
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}
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// remove switches from 'used' array
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for (j = 0; j < num_found; j++)
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str_sw[found_i[j]].to_str = 0;
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}
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// check whether all switches were found
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for (i = 0; i < num_sw; i++) {
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if (!str_sw[i].to_str)
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continue;
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fprintf(stderr, "#E %s:%i unsupported switch "
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"y%02i x%02i %s -> %s\n", __FILE__, __LINE__,
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y, x, str_sw[i].from_str, str_sw[i].to_str);
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}
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free(str_sw);
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return 0;
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fail:
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return rc;
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}
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static int write_switches(struct fpga_bits* bits, struct fpga_model* model)
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{
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struct fpga_tile* tile;
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int x, y, i, bit_pos, rc;
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int x, y, i, rc;
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for (x = 0; x < model->x_width; x++) {
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for (y = 0; y < model->y_height; y++) {
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if (!is_atx(X_ROUTING_COL, model, x)
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|| y < TOP_IO_TILES
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|| y >= model->y_height-BOT_IO_TILES
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|| is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y))
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if (is_atx(X_ROUTING_COL, model, x)
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&& y >= TOP_IO_TILES
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&& y < model->y_height-BOT_IO_TILES
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&& !is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y)) {
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rc = write_routing_sw(bits, model, y, x);
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if (rc) FAIL(rc);
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continue;
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}
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if (is_atyx(YX_DEV_ILOGIC, model, y, x)) {
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rc = write_iologic_sw(bits, model, y, x);
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if (rc) FAIL(rc);
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continue;
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}
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// todo: there are probably switches in logic and
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// iob that need bits, and switches in other
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// tiles that need no bits...
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if (is_atyx(YX_DEV_LOGIC|YX_DEV_IOB, model, y, x))
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continue;
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tile = YX_TILE(model, y, x);
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// go through enabled switches, lookup in sw_bitpos
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// and set bits
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for (i = 0; i < tile->num_switches; i++) {
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if (!(tile->switches[i] & SWITCH_USED))
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continue;
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bit_pos = find_bitpos(model, y, x, i);
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if (bit_pos == -1)
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continue;
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rc = bitpos_set_bits(bits, model, y, x,
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&model->sw_bitpos[bit_pos]);
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if (rc) FAIL(rc);
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fprintf(stderr, "#E %s:%i unsupported switch "
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"y%02i x%02i %s\n", __FILE__, __LINE__,
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y, x,
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fpga_switch_print(model, y, x, i));
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}
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}
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}
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@ -292,6 +292,7 @@ int is_atx(int check, struct fpga_model* model, int x);
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#define YX_DEV_ILOGIC 0x0008
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#define YX_DEV_OLOGIC 0x0010
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#define YX_DEV_LOGIC 0x0020
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#define YX_DEV_IOB 0x0040
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int is_atyx(int check, struct fpga_model* model, int y, int x);
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@ -591,6 +591,7 @@ int is_atyx(int check, struct fpga_model* model, int y, int x)
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if (check & YX_DEV_ILOGIC && has_device(model, y, x, DEV_ILOGIC)) return 1;
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if (check & YX_DEV_OLOGIC && has_device(model, y, x, DEV_OLOGIC)) return 1;
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if (check & YX_DEV_LOGIC && has_device(model, y, x, DEV_LOGIC)) return 1;
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if (check & YX_DEV_IOB && has_device(model, y, x, DEV_IOB)) return 1;
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return 0;
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}
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