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more switch work

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This commit is contained in:
Wolfgang Spraul 2012-10-20 16:03:35 +02:00
parent 8d4c6dfe82
commit 63ec0e2253
4 changed files with 1003 additions and 52 deletions
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10
libs/model.h
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@ -169,8 +169,9 @@ enum fpga_tile_type
#define LAST_POS_IN_ROW 16 // including hclk at 8
#define ROW_SIZE (HALF_ROW+1+HALF_ROW)
#define CENTER_TOP_IOB_O 3 // deduct from center_x
#define CENTER_BOT_IOB_O 1 // add to center_x
#define CENTER_X_PLUS_1 1 // logic col adjacent to center
#define CENTER_TOP_IOB_O 3 // deduct from center_y
#define CENTER_BOT_IOB_O 1 // add to center_y
// Some offsets that are being deducted from their origin
#define BOT_IO_TILES 2
@ -214,6 +215,7 @@ enum fpga_tile_type
// TF_WIRED is only set for x==0 on the left side or x==x_width-1
// on the right side.
#define TF_WIRED 0x00008000
#define TF_CENTER_MIDBUF 0x00010000
#define Y_INNER_TOP 0x0001
#define Y_INNER_BOTTOM 0x0002
@ -295,6 +297,7 @@ int is_atx(int check, struct fpga_model* model, int x);
#define YX_DEV_OLOGIC 0x0010
#define YX_DEV_LOGIC 0x0020
#define YX_DEV_IOB 0x0040
#define YX_CENTER_MIDBUF 0x0080
int is_atyx(int check, struct fpga_model* model, int y, int x);
@ -789,8 +792,11 @@ int add_connpt_name(struct fpga_model* model, int y, int x,
const char* connpt_name, int warn_if_duplicate, uint16_t* name_i,
int* conn_point_o);
// has_device() and has_device_type() return the number of devices
// for the given type or type/subtype.
int has_device(struct fpga_model* model, int y, int x, int dev);
int has_device_type(struct fpga_model* model, int y, int x, int dev, int subtype);
int add_connpt_2(struct fpga_model* model, int y, int x,
const char* connpt_name, const char* suffix1, const char* suffix2,
int dup_warn);

27
libs/model_helper.c
View File

@ -126,33 +126,28 @@ int add_connpt_name(struct fpga_model* model, int y, int x,
int has_device(struct fpga_model* model, int y, int x, int dev)
{
struct fpga_tile* tile = YX_TILE(model, y, x);
int i;
int i, type_count;
type_count = 0;
for (i = 0; i < tile->num_devs; i++) {
if (tile->devs[i].type == dev)
return 1;
type_count++;
}
return 0;
return type_count;
}
int has_device_type(struct fpga_model* model, int y, int x, int dev, int subtype)
{
struct fpga_tile* tile = YX_TILE(model, y, x);
int i;
int i, type_subtype_count;
type_subtype_count = 0;
for (i = 0; i < tile->num_devs; i++) {
if (tile->devs[i].type == dev) {
switch (dev) {
case DEV_LOGIC:
case DEV_IOB:
if (tile->devs[i].subtype == subtype)
return 1;
break;
default: EXIT(1);
}
}
if (tile->devs[i].type == dev
&& tile->devs[i].subtype == subtype)
type_subtype_count++;
}
return 0;
return type_subtype_count;
}
int add_connpt_2(struct fpga_model* model, int y, int x,
@ -417,6 +412,7 @@ int add_switch_set(struct fpga_model* model, int y, int x, const char* prefix,
int i, j, from_len, to_len, rc;
char from[64], to[64];
if (!prefix) prefix = "";
for (i = 0; pairs[i*2][0]; i++) {
snprintf(from, sizeof(from), "%s%s", prefix, pairs[i*2]);
snprintf(to, sizeof(to), "%s%s", prefix, pairs[i*2+1]);
@ -592,6 +588,7 @@ int is_atyx(int check, struct fpga_model* model, int y, int x)
if (check & YX_DEV_OLOGIC && has_device(model, y, x, DEV_OLOGIC)) return 1;
if (check & YX_DEV_LOGIC && has_device(model, y, x, DEV_LOGIC)) return 1;
if (check & YX_DEV_IOB && has_device(model, y, x, DEV_IOB)) return 1;
if (check & YX_CENTER_MIDBUF && tile->flags & TF_CENTER_MIDBUF) return 1;
return 0;
}

1006
libs/model_switches.c
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File diff suppressed because it is too large Load Diff

12
libs/model_tiles.c
View File

@ -289,17 +289,19 @@ int init_tiles(struct fpga_model* model)
if (l == 15) {
if (k == model->cfg_rows*3/4)
model->tiles[(row_top_y+l+1)*tile_columns + i + 3].type = REGV_MIDBUF_T;
else if (k == model->cfg_rows/4)
else if (k == model->cfg_rows/4) {
model->tiles[(row_top_y+l+1)*tile_columns + i + 3].flags |= TF_CENTER_MIDBUF;
model->tiles[(row_top_y+l+1)*tile_columns + i + 3].type = REGV_HCLKBUF_B;
else
} else
model->tiles[(row_top_y+l+1)*tile_columns + i + 3].type = REGV_BRK;
} else if (l == 0 && k == model->cfg_rows*3/4-1) {
model->tiles[(row_top_y+l)*tile_columns + i + 3].flags |= TF_CENTER_MIDBUF;
model->tiles[(row_top_y+l)*tile_columns + i + 3].type = REGV_HCLKBUF_T;
} else if (l == 0 && k == model->cfg_rows/4-1) {
} else if (l == 0 && k == model->cfg_rows/4-1)
model->tiles[(row_top_y+l)*tile_columns + i + 3].type = REGV_MIDBUF_B;
} else if (l == 8) {
else if (l == 8)
model->tiles[(row_top_y+l+1)*tile_columns + i + 3].type = (k<model->cfg_rows/2) ? REGV_B : REGV_T;
} else
else
model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i + 3].type = REGV;
}
model->tiles[(row_top_y+8)*tile_columns + i].type = HCLK_ROUTING_XL;