diff --git a/model.h b/model.h
index 70d6369..3e6d4c1 100644
--- a/model.h
+++ b/model.h
@@ -237,6 +237,11 @@ int is_aty(int check, struct fpga_model* model, int y);
 					 |X_LEFT_IO_ROUTING_COL \
 					 |X_RIGHT_IO_ROUTING_COL)
 
+// todo and realizations:
+// * maybe the center_logic and routing cols can also be
+//   seen as just a regular xl logic and routing cols.
+// * maybe the many special cases for bram are better
+//   tied to no-io columns
 #define X_OUTER_LEFT			0x00000001
 #define X_INNER_LEFT			0x00000002
 #define X_INNER_RIGHT			0x00000004
@@ -337,34 +342,23 @@ enum fpgadev_type
 // data can safely be initialized to 0 meaning unconfigured.
 
 enum { LOGIC_M = 1, LOGIC_L, LOGIC_X };
+// LUT_ macros to make the pinw arrays more readable
+enum { LUT_A = 0, LUT_B, LUT_C, LUT_D };
+enum { LUT_1 = 0, LUT_2, LUT_3, LUT_4, LUT_5, LUT_6 };
 
 struct fpgadev_logic
 {
-// M_A1..A6, M_AX
-// X_A1 or XX_A1 for L
+	// pinwires that don't exist for a specific device
+	// will be set to STRIDX_NO_ENTRY
+
    	// for X, L and M:
-	str16_t pinw_in_A1, pinw_in_A2, pinw_in_A3, pinw_in_A4, pinw_in_A5,
-		pinw_in_A6, pinw_in_AX;
-	str16_t pinw_in_B1, pinw_in_B2, pinw_in_B3, pinw_in_B4, pinw_in_B5,
-		pinw_in_B6, pinw_in_BX;
-	str16_t pinw_in_C1, pinw_in_C2, pinw_in_C3, pinw_in_C4, pinw_in_C5,
-		pinw_in_C6, pinw_in_CX;
-	str16_t pinw_in_D1, pinw_in_D2, pinw_in_D3, pinw_in_D4, pinw_in_D5,
-		pinw_in_D6, pinw_in_DX;
-// M_CLK, M_CE, M_SR
+	str16_t pinw_in[4][6], pinw_in_X[4];
 	str16_t pinw_in_CLK, pinw_in_CE, pinw_in_SR;
-// M_A, M_AMUX, M_AQ
-	str16_t pinw_out_A, pinw_out_AMUX, pinw_out_AQ;
-	str16_t pinw_out_B, pinw_out_BMUX, pinw_out_BQ;
-	str16_t pinw_out_C, pinw_out_CMUX, pinw_out_CQ;
-	str16_t pinw_out_D, pinw_out_DMUX, pinw_out_DQ;
+	str16_t pinw_out[4], pinw_out_MUX[4], pinw_out_Q[4];
 	// only for L and M:
-// M_CIN, M_COUT
-// L_CIN, XL_COUT
-        str16_t pinw_in_CIN, pinw_out_COUT;
+        str16_t pinw_in_CIN, pinw_out_COUT; // not all devs have this
 	// only for M:
-// M_WE, M_AI-DI
-        str16_t pinw_in_WE, pinw_in_AI, pinw_in_BI, pinw_in_CI, pinw_in_DI;
+        str16_t pinw_in_WE, pinw_in_I[4];
 
 	int subtype; // LOGIC_M, LOGIC_L or LOGIC_X
 	int A_used, B_used, C_used, D_used;
diff --git a/model_devices.c b/model_devices.c
index b66053b..d49cc23 100644
--- a/model_devices.c
+++ b/model_devices.c
@@ -9,135 +9,12 @@
 #include "model.h"
 #include "control.h"
 
-void free_devices(struct fpga_model* model)
-{
-	int i, j;
-	for (i = 0; i < model->x_width * model->y_height; i++) {
-		if (!model->tiles[i].num_devs)
-			continue;
-		EXIT(!model->tiles[i].devs);
-		for (j = 0; j < model->tiles[i].num_devs; j++) {
-			if (model->tiles[i].devs[j].type != DEV_LOGIC)
-				continue;
-			free(model->tiles[i].devs[i].logic.A6_lut);
-			model->tiles[i].devs[i].logic.A6_lut = 0;
-			free(model->tiles[i].devs[i].logic.B6_lut);
-			model->tiles[i].devs[i].logic.B6_lut = 0;
-			free(model->tiles[i].devs[i].logic.C6_lut);
-			model->tiles[i].devs[i].logic.C6_lut = 0;
-			free(model->tiles[i].devs[i].logic.D6_lut);
-			model->tiles[i].devs[i].logic.D6_lut = 0;
-		}
-		free(model->tiles[i].devs);
-		model->tiles[i].devs = 0;
-		model->tiles[i].num_devs = 0;
-	}
-}
-
-static int init_iob(struct fpga_model* model, int y, int x,
-	int idx, int subtype)
-{
-	struct fpga_tile* tile;
-	const char* prefix;
-	int type_idx, rc;
-	char tmp_str[128];
-
-	tile = YX_TILE(model, y, x);
-	tile->devs[idx].iob.subtype = subtype;
-	type_idx = fpga_dev_typecount(model, y, x, DEV_IOB, idx);
-	if (!y)
-		prefix = "TIOB";
-	else if (y == model->y_height - BOT_OUTER_ROW)
-		prefix = "BIOB";
-	else if (x == 0)
-		prefix = "LIOB";
-	else if (x == model->x_width - RIGHT_OUTER_O)
-		prefix = "RIOB";
-	else
-		FAIL(EINVAL);
-
-	snprintf(tmp_str, sizeof(tmp_str), "%s_O%i_PINW", prefix, type_idx);
-	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
-		&tile->devs[idx].iob.pinw_in_O, 0);
-	if (rc) FAIL(rc);
-
-	snprintf(tmp_str, sizeof(tmp_str), "%s_T%i_PINW", prefix, type_idx);
-	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
-		&tile->devs[idx].iob.pinw_in_T, 0);
-	if (rc) FAIL(rc);
-	snprintf(tmp_str, sizeof(tmp_str), "%s_IBUF%i_PINW", prefix, type_idx);
-	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
-		&tile->devs[idx].iob.pinw_out_I, 0);
-	if (rc) FAIL(rc);
-	snprintf(tmp_str, sizeof(tmp_str), "%s_PADOUT%i", prefix, type_idx);
-	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
-		&tile->devs[idx].iob.pinw_out_PADOUT, 0);
-	if (rc) FAIL(rc);
-	snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFI_IN%i", prefix, type_idx);
-	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
-		&tile->devs[idx].iob.pinw_in_DIFFI_IN, 0);
-	if (rc) FAIL(rc);
-	snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFO_IN%i", prefix, type_idx);
-	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
-		&tile->devs[idx].iob.pinw_in_DIFFO_IN, 0);
-	if (rc) FAIL(rc);
-	snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFO_OUT%i", prefix, type_idx);
-	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
-		&tile->devs[idx].iob.pinw_out_DIFFO_OUT, 0);
-	if (rc) FAIL(rc);
-
-	if (!x && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 1)
-		strcpy(tmp_str, "LIOB_TOP_PCI_RDY0");
-	else if (!x && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 0)
-		strcpy(tmp_str, "LIOB_BOT_PCI_RDY0");
-	else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 0)
-		strcpy(tmp_str, "RIOB_BOT_PCI_RDY0");
-	else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 1)
-		strcpy(tmp_str, "RIOB_TOP_PCI_RDY1");
-	else {
-		snprintf(tmp_str, sizeof(tmp_str),
-			"%s_PCI_RDY%i", prefix, type_idx);
-	}
-	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
-		&tile->devs[idx].iob.pinw_out_PCI_RDY, 0);
-	if (rc) FAIL(rc);
-	return 0;
-fail:
-	return rc;
-}
-
-#define DEV_INCREMENT 8
-
 static int add_dev(struct fpga_model* model,
-	int y, int x, int type, int subtype)
-{
-	struct fpga_tile* tile;
-	int new_dev_i;
-	int rc;
-
-	tile = YX_TILE(model, y, x);
-	if (!(tile->num_devs % DEV_INCREMENT)) {
-		void* new_ptr = realloc(tile->devs,
-			(tile->num_devs+DEV_INCREMENT)*sizeof(*tile->devs));
-		EXIT(!new_ptr);
-		memset(new_ptr + tile->num_devs * sizeof(*tile->devs),
-			0, DEV_INCREMENT*sizeof(*tile->devs));
-		tile->devs = new_ptr;
-	}
-	new_dev_i = tile->num_devs;
-	tile->num_devs++;
-
-	// init new device
-	tile->devs[new_dev_i].type = type;
-	if (type == DEV_IOB) {
-		rc = init_iob(model, y, x, new_dev_i, subtype);
-		if (rc) FAIL(rc);
-	} else if (type == DEV_LOGIC)
-		tile->devs[new_dev_i].logic.subtype = subtype;
-	return 0;
-fail:
-	return rc;
-}
+	int y, int x, int type, int subtype);
+static int init_iob(struct fpga_model* model, int y, int x,
+	int idx, int subtype);
+static int init_logic(struct fpga_model* model, int y, int x,
+	int idx, int subtype);
 
 int init_devices(struct fpga_model* model)
 {
@@ -424,3 +301,231 @@ int init_devices(struct fpga_model* model)
 fail:
 	return rc;
 }
+
+void free_devices(struct fpga_model* model)
+{
+	int i, j;
+	for (i = 0; i < model->x_width * model->y_height; i++) {
+		if (!model->tiles[i].num_devs)
+			continue;
+		EXIT(!model->tiles[i].devs);
+		for (j = 0; j < model->tiles[i].num_devs; j++) {
+			if (model->tiles[i].devs[j].type != DEV_LOGIC)
+				continue;
+			free(model->tiles[i].devs[i].logic.A6_lut);
+			model->tiles[i].devs[i].logic.A6_lut = 0;
+			free(model->tiles[i].devs[i].logic.B6_lut);
+			model->tiles[i].devs[i].logic.B6_lut = 0;
+			free(model->tiles[i].devs[i].logic.C6_lut);
+			model->tiles[i].devs[i].logic.C6_lut = 0;
+			free(model->tiles[i].devs[i].logic.D6_lut);
+			model->tiles[i].devs[i].logic.D6_lut = 0;
+		}
+		free(model->tiles[i].devs);
+		model->tiles[i].devs = 0;
+		model->tiles[i].num_devs = 0;
+	}
+}
+
+#define DEV_INCREMENT 8
+
+static int add_dev(struct fpga_model* model,
+	int y, int x, int type, int subtype)
+{
+	struct fpga_tile* tile;
+	int new_dev_i;
+	int rc;
+
+	tile = YX_TILE(model, y, x);
+	if (!(tile->num_devs % DEV_INCREMENT)) {
+		void* new_ptr = realloc(tile->devs,
+			(tile->num_devs+DEV_INCREMENT)*sizeof(*tile->devs));
+		EXIT(!new_ptr);
+		memset(new_ptr + tile->num_devs * sizeof(*tile->devs),
+			0, DEV_INCREMENT*sizeof(*tile->devs));
+		tile->devs = new_ptr;
+	}
+	new_dev_i = tile->num_devs;
+	tile->num_devs++;
+
+	// init new device
+	tile->devs[new_dev_i].type = type;
+	if (type == DEV_IOB) {
+		rc = init_iob(model, y, x, new_dev_i, subtype);
+		if (rc) FAIL(rc);
+	} else if (type == DEV_LOGIC) {
+		rc = init_logic(model, y, x, new_dev_i, subtype);
+		if (rc) FAIL(rc);
+	}
+	return 0;
+fail:
+	return rc;
+}
+
+static int init_iob(struct fpga_model* model, int y, int x,
+	int idx, int subtype)
+{
+	struct fpga_tile* tile;
+	const char* prefix;
+	int type_idx, rc;
+	char tmp_str[128];
+
+	tile = YX_TILE(model, y, x);
+	tile->devs[idx].iob.subtype = subtype;
+	type_idx = fpga_dev_typecount(model, y, x, DEV_IOB, idx);
+	if (!y)
+		prefix = "TIOB";
+	else if (y == model->y_height - BOT_OUTER_ROW)
+		prefix = "BIOB";
+	else if (x == 0)
+		prefix = "LIOB";
+	else if (x == model->x_width - RIGHT_OUTER_O)
+		prefix = "RIOB";
+	else
+		FAIL(EINVAL);
+
+	snprintf(tmp_str, sizeof(tmp_str), "%s_O%i_PINW", prefix, type_idx);
+	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
+		&tile->devs[idx].iob.pinw_in_O, 0);
+	if (rc) FAIL(rc);
+
+	snprintf(tmp_str, sizeof(tmp_str), "%s_T%i_PINW", prefix, type_idx);
+	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
+		&tile->devs[idx].iob.pinw_in_T, 0);
+	if (rc) FAIL(rc);
+	snprintf(tmp_str, sizeof(tmp_str), "%s_IBUF%i_PINW", prefix, type_idx);
+	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
+		&tile->devs[idx].iob.pinw_out_I, 0);
+	if (rc) FAIL(rc);
+	snprintf(tmp_str, sizeof(tmp_str), "%s_PADOUT%i", prefix, type_idx);
+	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
+		&tile->devs[idx].iob.pinw_out_PADOUT, 0);
+	if (rc) FAIL(rc);
+	snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFI_IN%i", prefix, type_idx);
+	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
+		&tile->devs[idx].iob.pinw_in_DIFFI_IN, 0);
+	if (rc) FAIL(rc);
+	snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFO_IN%i", prefix, type_idx);
+	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
+		&tile->devs[idx].iob.pinw_in_DIFFO_IN, 0);
+	if (rc) FAIL(rc);
+	snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFO_OUT%i", prefix, type_idx);
+	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
+		&tile->devs[idx].iob.pinw_out_DIFFO_OUT, 0);
+	if (rc) FAIL(rc);
+
+	if (!x && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 1)
+		strcpy(tmp_str, "LIOB_TOP_PCI_RDY0");
+	else if (!x && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 0)
+		strcpy(tmp_str, "LIOB_BOT_PCI_RDY0");
+	else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 0)
+		strcpy(tmp_str, "RIOB_BOT_PCI_RDY0");
+	else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 1)
+		strcpy(tmp_str, "RIOB_TOP_PCI_RDY1");
+	else {
+		snprintf(tmp_str, sizeof(tmp_str),
+			"%s_PCI_RDY%i", prefix, type_idx);
+	}
+	rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
+		&tile->devs[idx].iob.pinw_out_PCI_RDY, 0);
+	if (rc) FAIL(rc);
+	return 0;
+fail:
+	return rc;
+}
+
+static int init_logic(struct fpga_model* model, int y, int x,
+	int idx, int subtype)
+{
+	struct fpga_tile* tile;
+	const char* pre;
+	int i, j, rc;
+
+	tile = YX_TILE(model, y, x);
+	tile->devs[idx].logic.subtype = subtype;
+	if (subtype == LOGIC_M)
+		pre = "M_";
+	else if (subtype == LOGIC_L)
+		pre = "L_";
+	else if (subtype == LOGIC_X) {
+		pre = is_atx(X_FABRIC_LOGIC_XL_COL|X_CENTER_LOGIC_COL, model, x)
+			? "XX_" : "X_";
+	} else FAIL(EINVAL);
+
+	for (i = LUT_A; i <= LUT_D; i++) {
+		for (j = LUT_1; j <= LUT_6; j++) {
+			rc = add_connpt_name(model, y, x, pf("%s%c%i", pre, 'A'+i, j+1),
+				/*dup_warn*/ 1,
+				&tile->devs[idx].logic.pinw_in[i][j], 0);
+			if (rc) FAIL(rc);
+		}
+		rc = add_connpt_name(model, y, x, pf("%s%cX", pre, 'A'+i),
+			/*dup_warn*/ 1,
+			&tile->devs[idx].logic.pinw_in_X[i], 0);
+		if (rc) FAIL(rc);
+		if (subtype == LOGIC_M) {
+			rc = add_connpt_name(model, y, x, pf("%s%cI", pre, 'A'+i),
+				/*dup_warn*/ 1,
+				&tile->devs[idx].logic.pinw_in_I[i], 0);
+			if (rc) FAIL(rc);
+		} else
+			tile->devs[idx].logic.pinw_in_I[i] = STRIDX_NO_ENTRY;
+		rc = add_connpt_name(model, y, x, pf("%s%c", pre, 'A'+i),
+			/*dup_warn*/ 1,
+			&tile->devs[idx].logic.pinw_out[i], 0);
+		if (rc) FAIL(rc);
+		rc = add_connpt_name(model, y, x, pf("%s%cMUX", pre, 'A'+i),
+			/*dup_warn*/ 1,
+			&tile->devs[idx].logic.pinw_out_MUX[i], 0);
+		if (rc) FAIL(rc);
+		rc = add_connpt_name(model, y, x, pf("%s%cQ", pre, 'A'+i),
+			/*dup_warn*/ 1,
+			&tile->devs[idx].logic.pinw_out_Q[i], 0);
+		if (rc) FAIL(rc);
+	}
+	rc = add_connpt_name(model, y, x, pf("%sCLK", pre),
+		/*dup_warn*/ 1,
+		&tile->devs[idx].logic.pinw_in_CLK, 0);
+	if (rc) FAIL(rc);
+	rc = add_connpt_name(model, y, x, pf("%sCE", pre),
+		/*dup_warn*/ 1,
+		&tile->devs[idx].logic.pinw_in_CE, 0);
+	if (rc) FAIL(rc);
+	rc = add_connpt_name(model, y, x, pf("%sSR", pre),
+		/*dup_warn*/ 1,
+		&tile->devs[idx].logic.pinw_in_SR, 0);
+	if (rc) FAIL(rc);
+	if (subtype == LOGIC_M) {
+		rc = add_connpt_name(model, y, x, pf("%sWE", pre),
+			/*dup_warn*/ 1,
+			&tile->devs[idx].logic.pinw_in_WE, 0);
+		if (rc) FAIL(rc);
+	} else
+		tile->devs[idx].logic.pinw_in_WE = STRIDX_NO_ENTRY;
+	if (subtype != LOGIC_X
+	    && ((is_atx(X_ROUTING_NO_IO, model, x-1)
+		 && is_aty(Y_INNER_BOTTOM, model, y+1))
+		|| (!is_atx(X_ROUTING_NO_IO, model, x-1)
+		    && is_aty(Y_BOT_INNER_IO, model, y+1)))) {
+		rc = add_connpt_name(model, y, x, pf("%sCIN", pre),
+			/*dup_warn*/ 1,
+			&tile->devs[idx].logic.pinw_in_CIN, 0);
+		if (rc) FAIL(rc);
+	} else
+		tile->devs[idx].logic.pinw_in_CIN = STRIDX_NO_ENTRY;
+	if (subtype == LOGIC_M) {
+		rc = add_connpt_name(model, y, x, "M_COUT",
+			/*dup_warn*/ 1,
+			&tile->devs[idx].logic.pinw_out_COUT, 0);
+		if (rc) FAIL(rc);
+	} else if (subtype == LOGIC_L) {
+		rc = add_connpt_name(model, y, x, "XL_COUT",
+			/*dup_warn*/ 1,
+			&tile->devs[idx].logic.pinw_out_COUT, 0);
+		if (rc) FAIL(rc);
+	} else 
+		tile->devs[idx].logic.pinw_out_COUT = STRIDX_NO_ENTRY;
+	return 0;
+fail:
+	return rc;
+}
diff --git a/model_main.c b/model_main.c
index 81bc028..62a5b0d 100644
--- a/model_main.c
+++ b/model_main.c
@@ -49,7 +49,6 @@ int fpga_build_model(struct fpga_model* model, int fpga_rows,
 
 	rc = init_switches(model, /*routing_sw*/ !s_high_speed_replicate);
 	if (rc) FAIL(rc);
-
 	return 0;
 fail:
 	return rc;
diff --git a/model_ports.c b/model_ports.c
index def212d..eaeaec0 100644
--- a/model_ports.c
+++ b/model_ports.c
@@ -224,6 +224,7 @@ int init_ports(struct fpga_model* model, int dup_warn)
 	}
 
 	for (x = 0; x < model->x_width; x++) {
+		// VCC, GND and fans
 		if (is_atx(X_ROUTING_COL, model, x)) {
 			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
 				if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
@@ -269,6 +270,35 @@ int init_ports(struct fpga_model* model, int dup_warn)
 				}
 			}
 		}
+
+		// logicin
+		if (is_atx(X_FABRIC_LOGIC_XL_ROUTING_COL
+			  |X_CENTER_ROUTING_COL, model, x)) {
+			
+			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
+				static const int n[] = { 36, 44, 53, 61, 62 };
+
+				if (is_aty(Y_TOPBOT_IO_RANGE, model, y)
+				     && !is_atx(X_ROUTING_NO_IO, model, x))
+					continue;
+				if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
+					model, y))
+					continue;
+				if (is_atx(X_CENTER_ROUTING_COL, model, x)
+				    && (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
+						model, y+1)
+				        || is_aty(Y_ROW_HORIZ_AXSYMM, model, y-1)))
+					continue;
+
+				for (i = 0; i < sizeof(n)/sizeof(*n); i++) {
+					rc = add_connpt_name(model, y, x,
+						pf("LOGICIN_B%i", n[i]), dup_warn, 0, 0);
+					if (rc) goto xout;
+				}
+			}
+		}
+
+		// bram
 		if (is_atx(X_FABRIC_BRAM_COL, model, x)) {
 			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
 				if (YX_TILE(model, y, x)->flags & TF_BRAM_DEV) {
@@ -318,6 +348,7 @@ int init_ports(struct fpga_model* model, int dup_warn)
 				}
 			}
 		}
+		// macc
 		if (is_atx(X_FABRIC_MACC_COL, model, x)) {
 			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
 				if (YX_TILE(model, y, x)->flags & TF_MACC_DEV) {
@@ -395,71 +426,6 @@ int init_ports(struct fpga_model* model, int dup_warn)
 				}
 			}
 		}
-		if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)) {
-			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
-				if (YX_TILE(model, y, x)->flags & (TF_LOGIC_XM_DEV|TF_LOGIC_XL_DEV)) {
-					const char* pref[2];
-
-					if (YX_TILE(model, y, x)->flags & TF_LOGIC_XM_DEV) {
-						// The first SLICEM on the bottom has a given C_IN port.
-						if (is_aty(Y_INNER_BOTTOM, model, y+3)) {
-							rc = add_connpt_name(model, y, x, "M_CIN",
-								dup_warn, 0, 0);
-							if (rc) goto xout;
-						}
-						rc = add_connpt_name(model, y, x, "M_COUT",
-							dup_warn, 0, 0);
-						if (rc) goto xout;
-						rc = add_connpt_name(model, y, x, "M_WE",
-							dup_warn, 0, 0);
-						if (rc) goto xout;
-						for (i = 'A'; i <= 'D'; i++) {
-							rc = add_connpt_name(model, y, x, pf("M_%cI", i),
-								dup_warn, 0, 0);
-							if (rc) goto xout;
-						}
-						pref[0] = "M";
-						pref[1] = "X";
-					} else { // LOGIC_XL
-						rc = add_connpt_name(model, y, x, "XL_COUT",
-							dup_warn, 0, 0);
-						if (rc) goto xout;
-						pref[0] = "L";
-						pref[1] = "XX";
-					}
-					for (k = 0; k <= 1; k++) {
-						rc = add_connpt_name(model, y, x, pf("%s_CE", pref[k]),
-							dup_warn, 0, 0);
-						if (rc) goto xout;
-						rc = add_connpt_name(model, y, x, pf("%s_SR", pref[k]),
-							dup_warn, 0, 0);
-						if (rc) goto xout;
-						rc = add_connpt_name(model, y, x, pf("%s_CLK", pref[k]),
-							dup_warn, 0, 0);
-						if (rc) goto xout;
-						for (i = 'A'; i <= 'D'; i++) {
-							for (j = 1; j <= 6; j++) {
-								rc = add_connpt_name(model, y, x, pf("%s_%c%i", pref[k], i, j),
-									dup_warn, 0, 0);
-								if (rc) goto xout;
-							}
-							rc = add_connpt_name(model, y, x, pf("%s_%c", pref[k], i),
-								dup_warn, 0, 0);
-							if (rc) goto xout;
-							rc = add_connpt_name(model, y, x, pf("%s_%cMUX", pref[k], i),
-								dup_warn, 0, 0);
-							if (rc) goto xout;
-							rc = add_connpt_name(model, y, x, pf("%s_%cQ", pref[k], i),
-								dup_warn, 0, 0);
-							if (rc) goto xout;
-							rc = add_connpt_name(model, y, x, pf("%s_%cX", pref[k], i),
-								dup_warn, 0, 0);
-							if (rc) goto xout;
-						}
-					}
-				}
-			}
-		}
 	}
 	return 0;
 xout: