autotester
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127a6fde24
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750bdba173
29
autotest.c
29
autotest.c
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@ -5,25 +5,50 @@
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include <time.h>
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#include "model.h"
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#include "floorplan.h"
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#include "control.h"
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time_t g_start_time;
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#define TIME() (time(0)-g_start_time)
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#define TIMESTAMP() printf("O timestamp %lld\n", (long long) TIME())
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#define MEMUSAGE() printf("O memusage %i\n", get_vm_mb());
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#define TIME_AND_MEM() TIMESTAMP(); MEMUSAGE()
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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int rc;
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printf("\n");
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printf("O fpgatools automatic test suite. Be welcome and be "
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"our guest. namo namaha.\n");
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printf("\n");
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printf("O Time measured in seconds from 0.\n");
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g_start_time = time(0);
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TIMESTAMP();
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printf("O Memory usage reported in megabytes.\n");
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MEMUSAGE();
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printf("O Building memory model...\n");
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if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
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XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING)))
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goto fail;
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// inform about progress over stdout
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printf("O Done\n");
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TIME_AND_MEM();
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// pick 2 input IOBs, one output IOB and configure them
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// pick 1 logic block and configure
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// printf floorplan
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// start routing, step by step
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// after each step, printf floorplan diff (test_diff.sh)
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// popen/fork/pipe
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printf("\n");
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printf("O Test suite completed.\n");
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printf("\n");
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return EXIT_SUCCESS;
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fail:
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return rc;
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17
helper.c
17
helper.c
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@ -827,15 +827,18 @@ int s_stash_at_bin(struct hashed_strarray* array, const char* str, int idx, int
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if (!(array->bin_len[bin]%BIN_INCREMENT)
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|| array->bin_len[bin]%BIN_INCREMENT + BIN_STR_HEADER+str_len+1 > BIN_INCREMENT)
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{
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int new_alloclen =
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((array->bin_len[bin]
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int new_alloclen;
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void* new_ptr;
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new_alloclen = ((array->bin_len[bin]
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+ BIN_STR_HEADER+str_len+1)/BIN_INCREMENT + 1)
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* BIN_INCREMENT;
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void* new_ptr = realloc(array->bin_strings[bin], new_alloclen);
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new_ptr = realloc(array->bin_strings[bin], new_alloclen);
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if (!new_ptr) {
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fprintf(stderr, "Out of memory.\n");
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return -1;
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}
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if (new_alloclen > array->bin_len[bin])
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memset(new_ptr+array->bin_len[bin], 0, new_alloclen-array->bin_len[bin]);
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array->bin_strings[bin] = new_ptr;
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}
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// append new string at end of bin
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@ -873,10 +876,10 @@ int strarray_init(struct hashed_strarray* array, int highest_index)
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array->highest_index = highest_index;
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array->num_bins = highest_index / 64;
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array->bin_strings = malloc(array->num_bins*sizeof(*array->bin_strings));
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array->bin_len = malloc(array->num_bins*sizeof(*array->bin_len));
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array->bin_offsets = malloc(array->highest_index*sizeof(*array->bin_offsets));
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array->index_to_bin = malloc(array->highest_index*sizeof(*array->index_to_bin));
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array->bin_strings = calloc(array->num_bins,sizeof(*array->bin_strings));
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array->bin_len = calloc(array->num_bins,sizeof(*array->bin_len));
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array->bin_offsets = calloc(array->highest_index,sizeof(*array->bin_offsets));
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array->index_to_bin = calloc(array->highest_index,sizeof(*array->index_to_bin));
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if (!array->bin_strings || !array->bin_len
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|| !array->bin_offsets || !array->index_to_bin) {
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3
helper.h
3
helper.h
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@ -16,7 +16,8 @@
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#define PROGRAM_REVISION "2012-06-27"
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#define MACRO_STR(arg) #arg
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#define ABORT(expr) if (expr) { fprintf(stderr, "Internal error in %s:%i\n", __FILE__, __LINE__); exit(1); }
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#define EXIT(expr) if (expr) { fprintf(stderr, \
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"Internal error in %s:%i\n", __FILE__, __LINE__); exit(1); }
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void printf_help(void);
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@ -297,7 +297,7 @@ static int pcice_conn(struct fpga_model* model, int y, int x, int i)
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src_str = to_center ?
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"MACCSITE2_TTERM_PCICE_OUT" : "MACCSITE2_TTERM_PCICE_IN";
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else
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ABORT(1);
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EXIT(1);
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return add_conn_bi(model, y, x, src_str, y, i, "BTERM_CLB_PCICE");
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}
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@ -532,8 +532,8 @@ static int run_term_wires(struct fpga_model* model)
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next_net_o = 0;
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// The leftmost and rightmost columns of the fabric area are exempt.
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for (x = LEFT_SIDE_WIDTH+1; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
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ABORT(next_net_o+2 > sizeof(net.pts)/sizeof(net.pts[0]));
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ABORT(!model->tmp_str[x]);
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EXIT(next_net_o+2 > sizeof(net.pts)/sizeof(net.pts[0]));
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EXIT(!model->tmp_str[x]);
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// left and right half separate only for CEOUT and CLKOUT
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if (i < 2 && is_atx(X_CENTER_CMTPLL_COL, model, x)) {
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@ -650,8 +650,8 @@ static int run_term_wires(struct fpga_model* model)
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next_net_o = 0;
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// The leftmost and rightmost columns of the fabric area are exempt.
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for (x = LEFT_SIDE_WIDTH+1; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
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ABORT(next_net_o+2 > sizeof(net.pts)/sizeof(net.pts[0]));
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ABORT(!model->tmp_str[x]);
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EXIT(next_net_o+2 > sizeof(net.pts)/sizeof(net.pts[0]));
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EXIT(!model->tmp_str[x]);
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// left and right half separate only for CEOUT and CLKOUT
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if (i < 2 && is_atx(X_CENTER_CMTPLL_COL, model, x)) {
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@ -1804,14 +1804,14 @@ static int run_direction_wires(struct fpga_model* model)
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net.pts[j].y = y+j;
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net.pts[j].x = x;
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if (y+j == BOT_TERM(model)) {
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ABORT(!i);
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EXIT(!i);
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net.pts[j].name = pf("SS4%c%%i", s_4wire[i-1]);
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j++;
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break;
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}
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if (IS_CENTER_Y(y+j, model)
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|| pos_in_row(y+j, model) == HCLK_POS) {
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ABORT(!i);
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EXIT(!i);
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net.pts[j].name = pf("SS4%c%%i", s_4wire[i-1]);
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j++;
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net.pts[j].start_count = 0;
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net.pts[j].y = y-j;
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net.pts[j].x = x;
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if (y-j == TOP_INNER_ROW) {
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ABORT(!i);
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EXIT(!i);
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net.pts[j].name = pf("NN4%c%%i", s_4wire[i-1]);
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j++;
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break;
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net.pts[j].name = pf("NN4%c%%i", s_4wire[i]);
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if (IS_CENTER_Y(y-j, model)
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|| pos_in_row(y-j, model) == HCLK_POS) {
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ABORT(!i);
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EXIT(!i);
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i--;
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}
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j++;
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@ -58,7 +58,7 @@ int has_connpt(struct fpga_model* model, int y, int x,
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int i;
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if (strarray_find(&model->str, name, &i))
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ABORT(1);
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EXIT(1);
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if (i == STRIDX_NO_ENTRY)
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return 0;
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name_i = i;
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@ -673,7 +673,7 @@ const char* logicin_str(enum logicin_wire w)
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case M_DI: return "DI";
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case M_WE: return "WE";
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}
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ABORT(1);
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EXIT(1);
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return 0;
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}
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case X_DQ:
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case M_DQ: return "DQ";
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}
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ABORT(1);
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EXIT(1);
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return 0;
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}
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@ -50,7 +50,7 @@ static int init_iologic_ports(struct fpga_model* model, int y, int x, enum which
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case BOTTOM_S: prefix = "BIOI"; break;
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case LEFT_S: prefix = "LIOI"; break;
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case RIGHT_S: prefix = "RIOI"; break;
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default: ABORT(1);
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default: EXIT(1);
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}
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if (side == LEFT_S || side == RIGHT_S) {
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suffix1 = "_M";
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rc = add_connpt_name(model, y, x, pf("%s_KEEP1_STUB", prefix));
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if (rc) goto xout;
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for (i = 0; i <= 4; i++) {
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rc = add_connpt_2(model, y, x, pf("AUXADDR%i_IODELAY", i), suffix1, suffix2);
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rc = add_connpt_2(model, y, x, pf("AUXADDR%i_IODELAY", i), suffix1, suffix2);
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if (rc) goto xout;
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}
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rc = add_connpt_2(model, y, x, "AUXSDOIN_IODELAY", suffix1, suffix2);
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@ -53,7 +53,7 @@ static int init_logic_tile(struct fpga_model* model, int y, int x)
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ml = 'L';
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xp = "XX";
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} else
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ABORT(1);
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EXIT(1);
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if ((rc = add_switch(model, y, x,
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pf("CLEX%c_CLK0", ml), pf("%s_CLK", xp), 0 /* bidir */))) goto xout;
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const char* io_prefix;
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if (x < LEFT_SIDE_WIDTH) {
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ABORT(x != LEFT_IO_DEVS);
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EXIT(x != LEFT_IO_DEVS);
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io_prefix = "IOI_";
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} else if (x >= model->x_width-RIGHT_SIDE_WIDTH) {
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ABORT(x != model->x_width - RIGHT_IO_DEVS_O);
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EXIT(x != model->x_width - RIGHT_IO_DEVS_O);
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io_prefix = "RIOI_";
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} else {
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if (y == TOP_OUTER_IO) {
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} else if (y == model->y_height-BOT_OUTER_IO) {
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io_prefix = "TIOI_";
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} else
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ABORT(1);
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EXIT(1);
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}
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for (i = 0; i <= 23; i++) {
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prefix = "RIOB";
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num_devs = 1;
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} else
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ABORT(1);
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EXIT(1);
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for (i = 0; i < num_devs*2; i++) {
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rc = add_switch(model, y, x,
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@ -693,7 +693,7 @@ static const char* wire_base(enum wire_type w)
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case W_WW4: return "WW4";
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case W_NW4: return "NW4";
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}
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ABORT(1);
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EXIT(1);
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}
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static int rotate_num(int cur, int off, int first, int last)
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return rotate_num(cur, off, FIRST_LEN2, LAST_LEN2);
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if (W_IS_LEN4(cur))
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return rotate_num(cur, off, FIRST_LEN4, LAST_LEN4);
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ABORT(1);
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EXIT(1);
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}
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enum wire_type wire_to_len(enum wire_type w, int first_len)
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return w-FIRST_LEN2 + first_len;
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if (W_IS_LEN4(w))
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return w-FIRST_LEN4 + first_len;
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ABORT(1);
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EXIT(1);
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}
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static enum wire_type wire_to_NESW4(enum wire_type w)
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