autotester

This commit is contained in:
Wolfgang Spraul 2012-08-14 07:31:51 +02:00
parent 127a6fde24
commit 750bdba173
7 changed files with 61 additions and 32 deletions

View File

@ -5,25 +5,50 @@
// For details see the UNLICENSE file at the root of the source tree.
//
#include <time.h>
#include "model.h"
#include "floorplan.h"
#include "control.h"
time_t g_start_time;
#define TIME() (time(0)-g_start_time)
#define TIMESTAMP() printf("O timestamp %lld\n", (long long) TIME())
#define MEMUSAGE() printf("O memusage %i\n", get_vm_mb());
#define TIME_AND_MEM() TIMESTAMP(); MEMUSAGE()
int main(int argc, char** argv)
{
struct fpga_model model;
int rc;
printf("\n");
printf("O fpgatools automatic test suite. Be welcome and be "
"our guest. namo namaha.\n");
printf("\n");
printf("O Time measured in seconds from 0.\n");
g_start_time = time(0);
TIMESTAMP();
printf("O Memory usage reported in megabytes.\n");
MEMUSAGE();
printf("O Building memory model...\n");
if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING)))
goto fail;
// inform about progress over stdout
printf("O Done\n");
TIME_AND_MEM();
// pick 2 input IOBs, one output IOB and configure them
// pick 1 logic block and configure
// printf floorplan
// start routing, step by step
// after each step, printf floorplan diff (test_diff.sh)
// popen/fork/pipe
printf("\n");
printf("O Test suite completed.\n");
printf("\n");
return EXIT_SUCCESS;
fail:
return rc;

View File

@ -827,15 +827,18 @@ int s_stash_at_bin(struct hashed_strarray* array, const char* str, int idx, int
if (!(array->bin_len[bin]%BIN_INCREMENT)
|| array->bin_len[bin]%BIN_INCREMENT + BIN_STR_HEADER+str_len+1 > BIN_INCREMENT)
{
int new_alloclen =
((array->bin_len[bin]
int new_alloclen;
void* new_ptr;
new_alloclen = ((array->bin_len[bin]
+ BIN_STR_HEADER+str_len+1)/BIN_INCREMENT + 1)
* BIN_INCREMENT;
void* new_ptr = realloc(array->bin_strings[bin], new_alloclen);
new_ptr = realloc(array->bin_strings[bin], new_alloclen);
if (!new_ptr) {
fprintf(stderr, "Out of memory.\n");
return -1;
}
if (new_alloclen > array->bin_len[bin])
memset(new_ptr+array->bin_len[bin], 0, new_alloclen-array->bin_len[bin]);
array->bin_strings[bin] = new_ptr;
}
// append new string at end of bin
@ -873,10 +876,10 @@ int strarray_init(struct hashed_strarray* array, int highest_index)
array->highest_index = highest_index;
array->num_bins = highest_index / 64;
array->bin_strings = malloc(array->num_bins*sizeof(*array->bin_strings));
array->bin_len = malloc(array->num_bins*sizeof(*array->bin_len));
array->bin_offsets = malloc(array->highest_index*sizeof(*array->bin_offsets));
array->index_to_bin = malloc(array->highest_index*sizeof(*array->index_to_bin));
array->bin_strings = calloc(array->num_bins,sizeof(*array->bin_strings));
array->bin_len = calloc(array->num_bins,sizeof(*array->bin_len));
array->bin_offsets = calloc(array->highest_index,sizeof(*array->bin_offsets));
array->index_to_bin = calloc(array->highest_index,sizeof(*array->index_to_bin));
if (!array->bin_strings || !array->bin_len
|| !array->bin_offsets || !array->index_to_bin) {

View File

@ -16,7 +16,8 @@
#define PROGRAM_REVISION "2012-06-27"
#define MACRO_STR(arg) #arg
#define ABORT(expr) if (expr) { fprintf(stderr, "Internal error in %s:%i\n", __FILE__, __LINE__); exit(1); }
#define EXIT(expr) if (expr) { fprintf(stderr, \
"Internal error in %s:%i\n", __FILE__, __LINE__); exit(1); }
void printf_help(void);

View File

@ -297,7 +297,7 @@ static int pcice_conn(struct fpga_model* model, int y, int x, int i)
src_str = to_center ?
"MACCSITE2_TTERM_PCICE_OUT" : "MACCSITE2_TTERM_PCICE_IN";
else
ABORT(1);
EXIT(1);
return add_conn_bi(model, y, x, src_str, y, i, "BTERM_CLB_PCICE");
}
@ -532,8 +532,8 @@ static int run_term_wires(struct fpga_model* model)
next_net_o = 0;
// The leftmost and rightmost columns of the fabric area are exempt.
for (x = LEFT_SIDE_WIDTH+1; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
ABORT(next_net_o+2 > sizeof(net.pts)/sizeof(net.pts[0]));
ABORT(!model->tmp_str[x]);
EXIT(next_net_o+2 > sizeof(net.pts)/sizeof(net.pts[0]));
EXIT(!model->tmp_str[x]);
// left and right half separate only for CEOUT and CLKOUT
if (i < 2 && is_atx(X_CENTER_CMTPLL_COL, model, x)) {
@ -650,8 +650,8 @@ static int run_term_wires(struct fpga_model* model)
next_net_o = 0;
// The leftmost and rightmost columns of the fabric area are exempt.
for (x = LEFT_SIDE_WIDTH+1; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
ABORT(next_net_o+2 > sizeof(net.pts)/sizeof(net.pts[0]));
ABORT(!model->tmp_str[x]);
EXIT(next_net_o+2 > sizeof(net.pts)/sizeof(net.pts[0]));
EXIT(!model->tmp_str[x]);
// left and right half separate only for CEOUT and CLKOUT
if (i < 2 && is_atx(X_CENTER_CMTPLL_COL, model, x)) {
@ -1804,14 +1804,14 @@ static int run_direction_wires(struct fpga_model* model)
net.pts[j].y = y+j;
net.pts[j].x = x;
if (y+j == BOT_TERM(model)) {
ABORT(!i);
EXIT(!i);
net.pts[j].name = pf("SS4%c%%i", s_4wire[i-1]);
j++;
break;
}
if (IS_CENTER_Y(y+j, model)
|| pos_in_row(y+j, model) == HCLK_POS) {
ABORT(!i);
EXIT(!i);
net.pts[j].name = pf("SS4%c%%i", s_4wire[i-1]);
j++;
net.pts[j].start_count = 0;
@ -1841,7 +1841,7 @@ static int run_direction_wires(struct fpga_model* model)
net.pts[j].y = y-j;
net.pts[j].x = x;
if (y-j == TOP_INNER_ROW) {
ABORT(!i);
EXIT(!i);
net.pts[j].name = pf("NN4%c%%i", s_4wire[i-1]);
j++;
break;
@ -1849,7 +1849,7 @@ static int run_direction_wires(struct fpga_model* model)
net.pts[j].name = pf("NN4%c%%i", s_4wire[i]);
if (IS_CENTER_Y(y-j, model)
|| pos_in_row(y-j, model) == HCLK_POS) {
ABORT(!i);
EXIT(!i);
i--;
}
j++;

View File

@ -58,7 +58,7 @@ int has_connpt(struct fpga_model* model, int y, int x,
int i;
if (strarray_find(&model->str, name, &i))
ABORT(1);
EXIT(1);
if (i == STRIDX_NO_ENTRY)
return 0;
name_i = i;
@ -673,7 +673,7 @@ const char* logicin_str(enum logicin_wire w)
case M_DI: return "DI";
case M_WE: return "WE";
}
ABORT(1);
EXIT(1);
return 0;
}
@ -705,6 +705,6 @@ const char* logicout_str(enum logicout_wire w)
case X_DQ:
case M_DQ: return "DQ";
}
ABORT(1);
EXIT(1);
return 0;
}

View File

@ -50,7 +50,7 @@ static int init_iologic_ports(struct fpga_model* model, int y, int x, enum which
case BOTTOM_S: prefix = "BIOI"; break;
case LEFT_S: prefix = "LIOI"; break;
case RIGHT_S: prefix = "RIOI"; break;
default: ABORT(1);
default: EXIT(1);
}
if (side == LEFT_S || side == RIGHT_S) {
suffix1 = "_M";
@ -71,7 +71,7 @@ static int init_iologic_ports(struct fpga_model* model, int y, int x, enum which
rc = add_connpt_name(model, y, x, pf("%s_KEEP1_STUB", prefix));
if (rc) goto xout;
for (i = 0; i <= 4; i++) {
rc = add_connpt_2(model, y, x, pf("AUXADDR%i_IODELAY", i), suffix1, suffix2);
rc = add_connpt_2(model, y, x, pf("AUXADDR%i_IODELAY", i), suffix1, suffix2);
if (rc) goto xout;
}
rc = add_connpt_2(model, y, x, "AUXSDOIN_IODELAY", suffix1, suffix2);

View File

@ -53,7 +53,7 @@ static int init_logic_tile(struct fpga_model* model, int y, int x)
ml = 'L';
xp = "XX";
} else
ABORT(1);
EXIT(1);
if ((rc = add_switch(model, y, x,
pf("CLEX%c_CLK0", ml), pf("%s_CLK", xp), 0 /* bidir */))) goto xout;
@ -155,10 +155,10 @@ static int init_iologic_tile(struct fpga_model* model, int y, int x)
const char* io_prefix;
if (x < LEFT_SIDE_WIDTH) {
ABORT(x != LEFT_IO_DEVS);
EXIT(x != LEFT_IO_DEVS);
io_prefix = "IOI_";
} else if (x >= model->x_width-RIGHT_SIDE_WIDTH) {
ABORT(x != model->x_width - RIGHT_IO_DEVS_O);
EXIT(x != model->x_width - RIGHT_IO_DEVS_O);
io_prefix = "RIOI_";
} else {
if (y == TOP_OUTER_IO) {
@ -170,7 +170,7 @@ static int init_iologic_tile(struct fpga_model* model, int y, int x)
} else if (y == model->y_height-BOT_OUTER_IO) {
io_prefix = "TIOI_";
} else
ABORT(1);
EXIT(1);
}
for (i = 0; i <= 23; i++) {
@ -534,7 +534,7 @@ static int init_io_tile(struct fpga_model* model, int y, int x)
prefix = "RIOB";
num_devs = 1;
} else
ABORT(1);
EXIT(1);
for (i = 0; i < num_devs*2; i++) {
rc = add_switch(model, y, x,
@ -693,7 +693,7 @@ static const char* wire_base(enum wire_type w)
case W_WW4: return "WW4";
case W_NW4: return "NW4";
}
ABORT(1);
EXIT(1);
}
static int rotate_num(int cur, int off, int first, int last)
@ -713,7 +713,7 @@ enum wire_type rotate_wire(enum wire_type cur, int off)
return rotate_num(cur, off, FIRST_LEN2, LAST_LEN2);
if (W_IS_LEN4(cur))
return rotate_num(cur, off, FIRST_LEN4, LAST_LEN4);
ABORT(1);
EXIT(1);
}
enum wire_type wire_to_len(enum wire_type w, int first_len)
@ -724,7 +724,7 @@ enum wire_type wire_to_len(enum wire_type w, int first_len)
return w-FIRST_LEN2 + first_len;
if (W_IS_LEN4(w))
return w-FIRST_LEN4 + first_len;
ABORT(1);
EXIT(1);
}
static enum wire_type wire_to_NESW4(enum wire_type w)