modeling wires, about 0.7% of them done
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325c31920b
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7f74817e78
154
model.c
154
model.c
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@ -264,46 +264,74 @@ int add_conn_bi(struct fpga_model* model, int y1, int x1, const char* name1, int
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const char* pf(const char* fmt, ...)
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{
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static char pf_buf[128];
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// safe to call it 4 times in 1 expression (such as function params)
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static char pf_buf[4][128];
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static int last_buf = 0;
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va_list list;
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pf_buf[0] = 0;
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last_buf = (last_buf+1)%4;
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pf_buf[last_buf][0] = 0;
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va_start(list, fmt);
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vsnprintf(pf_buf, sizeof(pf_buf), fmt, list);
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vsnprintf(pf_buf[last_buf], sizeof(pf_buf[0]), fmt, list);
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va_end(list);
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return pf_buf;
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return pf_buf[last_buf];
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}
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int run_wires(struct fpga_model* model)
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{
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struct fpga_tile* tile, *tile_up1, *tile_up2;
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char b_wire[16], m_wire[16], e_wire[16];
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char b_wire[16], m_wire[16], e_wire[16], r1b_wire[16], r1e_wire[16];
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char* wire_fmt;
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int x, y, i, rc;
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rc = -1;
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for (y = 0; y < model->tile_y_range; y++) {
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for (x = 0; x < model->tile_x_range; x++) {
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tile = &model->tiles[y * model->tile_x_range + x];
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if (!(tile->flags & TF_DIRWIRE_START))
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continue;
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tile = &model->tiles[y * model->tile_x_range + x];
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tile_up1 = &model->tiles[(y-1) * model->tile_x_range + x];
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tile_up2 = &model->tiles[(y-2) * model->tile_x_range + x];
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if (!(tile->flags & TF_DIRWIRE_START)) {
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if (tile->flags & TF_VERT_ROUTING) {
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if (tile_up1->flags & (TF_ROW_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM)) {
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if (tile_up1->flags & TF_ROW_HORIZ_AXSYMM)
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wire_fmt = "HCLK_%s";
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else if (tile[3].flags & TF_CHIP_VERT_AXSYMM)
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wire_fmt = "REGC_INT_%s";
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else
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wire_fmt = "REGH_%s";
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for (i = 0; i <= 3; i++) {
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sprintf(r1b_wire, "NR1B%i", i);
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sprintf(r1e_wire, "NR1E%i", i);
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-1, x, pf(wire_fmt, r1e_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-2, x, r1e_wire))) goto xout;
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}
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} else {
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for (i = 0; i <= 3; i++) {
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if ((rc = add_conn_bi(model, y, x, pf("NR1B%i", i), y-1, x, pf("NR1E%i", i)))) goto xout;
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}
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}
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}
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continue;
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}
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for (i = 0; i <= 3; i++) {
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sprintf(b_wire, "NN2B%i", i);
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sprintf(m_wire, "NN2M%i", i);
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sprintf(e_wire, "NN2E%i", i);
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if (tile_up1->flags & TF_SECOND_ROW) {
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rc = add_conn_bi(model, y, x, b_wire, y-1, x, pf("IOI_TTERM_%s", b_wire));
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if (rc) goto xout;
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} else if (tile_up2->flags & TF_SECOND_ROW) {
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rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y, x, b_wire, y-2, x, pf("IOI_TTERM_%s", m_wire));
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if (rc) goto xout;
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rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, pf("IOI_TTERM_%s", m_wire));
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if (rc) goto xout;
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sprintf(r1b_wire, "NR1B%i", i);
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sprintf(r1e_wire, "NR1E%i", i);
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if (tile_up1->flags & TF_UNDER_TOPMOST_TILE) {
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, pf("IOI_TTERM_%s", b_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-1, x, pf("IOI_TTERM_%s", r1b_wire)))) goto xout;
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} else if (tile_up2->flags & TF_UNDER_TOPMOST_TILE) {
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-2, x, pf("IOI_TTERM_%s", m_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, pf("IOI_TTERM_%s", m_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-1, x, r1e_wire))) goto xout;
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} else if (tile_up1->flags & (TF_ROW_HORIZ_AXSYMM|TF_CHIP_HORIZ_AXSYMM)) {
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if (tile_up1->flags & TF_ROW_HORIZ_AXSYMM)
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@ -313,18 +341,15 @@ int run_wires(struct fpga_model* model)
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else
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wire_fmt = "REGH_%s";
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rc = add_conn_bi(model, y, x, b_wire, y-1, x, pf(wire_fmt, m_wire));
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if (rc) goto xout;
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rc = add_conn_bi(model, y, x, b_wire, y-2, x, m_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y, x, b_wire, y-3, x, e_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y-1, x, pf(wire_fmt, m_wire), y-2, x, m_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y-1, x, pf(wire_fmt, m_wire), y-3, x, e_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y-2, x, m_wire, y-3, x, e_wire);
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if (rc) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, pf(wire_fmt, m_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-2, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, pf(wire_fmt, m_wire), y-2, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, pf(wire_fmt, m_wire), y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, m_wire, y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-2, x, r1e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-1, x, pf(wire_fmt, r1e_wire)))) goto xout;
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} else if (tile_up2->flags & (TF_ROW_HORIZ_AXSYMM|TF_CHIP_HORIZ_AXSYMM)) {
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@ -335,32 +360,24 @@ int run_wires(struct fpga_model* model)
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else
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wire_fmt = "REGH_%s";
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rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y, x, b_wire, y-2, x, pf(wire_fmt, e_wire));
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if (rc) goto xout;
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rc = add_conn_bi(model, y, x, b_wire, y-3, x, e_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, pf(wire_fmt, e_wire));
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if (rc) goto xout;
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rc = add_conn_bi(model, y-1, x, m_wire, y-3, x, e_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y-2, x, pf(wire_fmt, e_wire), y-3, x, e_wire);
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if (rc) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-2, x, pf(wire_fmt, e_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, pf(wire_fmt, e_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, m_wire, y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, pf(wire_fmt, e_wire), y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-1, x, r1e_wire))) goto xout;
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} else {
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rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y, x, b_wire, y-2, x, e_wire);
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if (rc) goto xout;
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rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, e_wire);
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if (rc) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-2, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, e_wire))) goto xout;
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if (!i) {
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rc = add_conn_bi(model, y, x, "NN2B0", y-1, x, "NN2E_S0");
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if (rc) goto xout;
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rc = add_conn_bi(model, y-2, x, "NN2E0", y-1, x, "NN2E_S0");
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if (rc) goto xout;
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if ((rc = add_conn_bi(model, y, x, "NN2B0", y-1, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, "NN2E0", y-1, x, "NN2E_S0"))) goto xout;
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}
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-1, x, r1e_wire))) goto xout;
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}
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}
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}
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@ -400,16 +417,17 @@ int init_tiles(struct fpga_model* model)
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// flag horizontal rows
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for (x = 0; x < model->tile_x_range; x++) {
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model->tiles[x].flags |= TF_FIRST_ROW;
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model->tiles[model->tile_x_range + x].flags |= TF_SECOND_ROW;
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model->tiles[x].flags |= TF_TOPMOST_TILE;
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model->tiles[model->tile_x_range + x].flags |= TF_UNDER_TOPMOST_TILE;
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for (i = model->cfg_rows-1; i >= 0; i--) {
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row_top_y = 2 /* top IO tiles */ + (model->cfg_rows-1-i)*(8+1/*middle of row clock*/+8);
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if (i<(model->cfg_rows/2)) row_top_y++; // middle system tiles
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model->tiles[(row_top_y+8)*model->tile_x_range + x].flags |= TF_ROW_HORIZ_AXSYMM;
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model->tiles[(row_top_y+16)*model->tile_x_range + x].flags |= TF_BOTTOM_OF_ROW;
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}
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model->tiles[center_row * model->tile_x_range + x].flags |= TF_CHIP_HORIZ_AXSYMM;
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model->tiles[(model->tile_y_range-2)*model->tile_x_range + x].flags |= TF_SECOND_TO_LAST_ROW;
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model->tiles[(model->tile_y_range-1)*model->tile_x_range + x].flags |= TF_LAST_ROW;
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model->tiles[(model->tile_y_range-2)*model->tile_x_range + x].flags |= TF_ABOVE_BOTTOMMOST_TILE;
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model->tiles[(model->tile_y_range-1)*model->tile_x_range + x].flags |= TF_BOTTOMMOST_TILE;
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}
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//
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@ -420,6 +438,20 @@ int init_tiles(struct fpga_model* model)
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left_side = 1; // turn off (=right side) when reaching the 'R' middle column
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i = 5; // skip left IO columns
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for (j = 0; model->cfg_columns[j]; j++) {
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if (model->cfg_columns[j] == 'L'
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|| model->cfg_columns[j] == 'l'
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|| model->cfg_columns[j] == 'M'
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|| model->cfg_columns[j] == 'm'
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|| model->cfg_columns[j] == 'D'
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|| model->cfg_columns[j] == 'B'
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|| model->cfg_columns[j] == 'R') {
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for (k = model->cfg_rows-1; k >= 0; k--) {
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row_top_y = 2 /* top IO tiles */ + (model->cfg_rows-1-k)*(8+1/*middle of row clock*/+8);
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if (k<(model->cfg_rows/2)) row_top_y++; // middle system tiles (center row)
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for (l = 0; l < 16; l++)
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model->tiles[(row_top_y+(l<8?l:l+1))*model->tile_x_range + i].flags |= TF_VERT_ROUTING;
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}
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}
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switch (model->cfg_columns[j]) {
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case 'L':
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case 'l':
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@ -669,6 +701,16 @@ int init_tiles(struct fpga_model* model)
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}
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}
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// flag left and right vertical routing
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for (k = model->cfg_rows-1; k >= 0; k--) {
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row_top_y = 2 /* top IO tiles */ + (model->cfg_rows-1-k)*(8+1/*middle of row clock*/+8);
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if (k<(model->cfg_rows/2)) row_top_y++; // middle system tiles (center row)
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for (l = 0; l < 16; l++) {
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model->tiles[(row_top_y+(l<8?l:l+1))*model->tile_x_range + 2].flags |= TF_VERT_ROUTING;
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model->tiles[(row_top_y+(l<8?l:l+1))*model->tile_x_range + model->tile_x_range - 5].flags |= TF_VERT_ROUTING;
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}
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}
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//
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// left IO
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//
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14
model.h
14
model.h
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@ -122,13 +122,15 @@ enum fpga_tile_type
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// tile flags
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#define TF_DIRWIRE_START 0x0001
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#define TF_FIRST_ROW 0x0002
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#define TF_SECOND_ROW 0x0004
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#define TF_SECOND_TO_LAST_ROW 0x0008
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#define TF_LAST_ROW 0x0010
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#define TF_TOPMOST_TILE 0x0002
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#define TF_UNDER_TOPMOST_TILE 0x0004
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#define TF_ABOVE_BOTTOMMOST_TILE 0x0008
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#define TF_BOTTOMMOST_TILE 0x0010
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#define TF_ROW_HORIZ_AXSYMM 0x0020
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#define TF_CHIP_HORIZ_AXSYMM 0x0040
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#define TF_CHIP_VERT_AXSYMM 0x0080
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#define TF_BOTTOM_OF_ROW 0x0040
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#define TF_CHIP_HORIZ_AXSYMM 0x0080
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#define TF_CHIP_VERT_AXSYMM 0x0100
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#define TF_VERT_ROUTING 0x0200
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struct fpga_tile
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{
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