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error handling improvement

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This commit is contained in:
Wolfgang Spraul 2012-11-21 05:44:23 +01:00
parent 4671415c87
commit 80eec05b7a
9 changed files with 257 additions and 257 deletions
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33
libs/bit_frames.c
View File

@ -95,6 +95,8 @@ struct extract_state
static int find_es_switch(struct extract_state* es, int y, int x, swidx_t sw)
{
int i;
RC_CHECK(es->model);
if (sw == NO_SWITCH) { HERE(); return 0; }
for (i = 0; i < es->num_yx_pos; i++) {
if (es->yx_pos[i].y == y
@ -112,6 +114,7 @@ static int write_iobs(struct fpga_bits* bits, struct fpga_model* model)
uint64_t u64;
const char* name;
RC_CHECK(model);
first_iob = 0;
for (i = 0; (name = fpga_enum_iob(model, i, &y, &x, &type_idx)); i++) {
dev_idx = fpga_dev_idx(model, y, x, DEV_IOB, type_idx);
@ -274,6 +277,7 @@ static int extract_iobs(struct extract_state* es)
struct fpga_device* dev;
struct fpgadev_iob cfg;
RC_CHECK(es->model);
num_iobs = get_num_iobs(XC6SLX9);
first_iob = 0;
for (i = 0; i < num_iobs; i++) {
@ -617,6 +621,7 @@ static int extract_logic(struct extract_state* es)
char lut5_x[NUM_LUTS][MAX_LUT_LEN];
struct fpga_device* dev_ml;
RC_CHECK(es->model);
for (x = LEFT_SIDE_WIDTH; x < es->model->x_width-RIGHT_SIDE_WIDTH; x++) {
if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, es->model, x))
continue;
@ -1366,11 +1371,12 @@ fail:
return rc;
}
static int bitpos_is_set(struct extract_state* es, int y, int x,
struct xc6_routing_bitpos* swpos, int* is_set)
static int bitpos_is_set(struct extract_state *es, int y, int x,
struct xc6_routing_bitpos *swpos, int *is_set)
{
int row_num, row_pos, start_in_frame, two_bits_val, rc;
RC_CHECK(es->model);
*is_set = 0;
is_in_row(es->model, y, &row_num, &row_pos);
if (row_num == -1 || row_pos == -1
@ -1416,6 +1422,7 @@ static int bitpos_clear_bits(struct extract_state* es, int y, int x,
{
int row_num, row_pos, start_in_frame, rc;
RC_CHECK(es->model);
is_in_row(es->model, y, &row_num, &row_pos);
if (row_num == -1 || row_pos == -1
|| row_pos == HCLK_POS) FAIL(EINVAL);
@ -1449,6 +1456,7 @@ static int bitpos_set_bits(struct fpga_bits* bits, struct fpga_model* model,
{
int row_num, row_pos, start_in_frame, rc;
RC_CHECK(model);
is_in_row(model, y, &row_num, &row_pos);
if (row_num == -1 || row_pos == -1
|| row_pos == HCLK_POS) FAIL(EINVAL);
@ -1522,6 +1530,7 @@ static int extract_logic_switches(struct extract_state* es, int y, int x)
int row, row_pos, byte_off, minor, rc;
uint8_t* u8_p;
RC_CHECK(es->model);
row = which_row(y, es->model);
row_pos = pos_in_row(y, es->model);
if (row == -1 || row_pos == -1 || row_pos == 8) FAIL(EINVAL);
@ -1719,6 +1728,7 @@ static int extract_iologic_switches(struct extract_state* es, int y, int x)
str16_t from_str_i, to_str_i;
swidx_t sw_idx;
RC_CHECK(es->model);
// From y/x coordinate, determine major, row, bit offset
// in frame (v64_i) and pointer to first minor.
is_in_row(es->model, y, &row_num, &row_pos);
@ -1789,6 +1799,7 @@ static int extract_switches(struct extract_state* es)
{
int x, y, rc;
RC_CHECK(es->model);
for (x = 0; x < es->model->x_width; x++) {
for (y = 0; y < es->model->y_height; y++) {
// routing switches
@ -1820,6 +1831,7 @@ fail:
static int construct_extract_state(struct extract_state* es,
struct fpga_model* model)
{
RC_CHECK(model);
memset(es, 0, sizeof(*es));
es->model = model;
return 0;
@ -1894,6 +1906,7 @@ static int find_bitpos(struct fpga_model* model, int y, int x, swidx_t sw)
const char* from_str, *to_str;
int i;
RC_CHECK(model);
from_str = fpga_switch_str(model, y, x, sw, SW_FROM);
to_str = fpga_switch_str(model, y, x, sw, SW_TO);
from_w = fpga_str2wire(from_str);
@ -1925,6 +1938,7 @@ static int write_routing_sw(struct fpga_bits* bits, struct fpga_model* model, in
struct fpga_tile* tile;
int i, bit_pos, rc;
RC_CHECK(model);
// go through enabled switches, lookup in sw_bitpos
// and set bits
tile = YX_TILE(model, y, x);
@ -1957,6 +1971,7 @@ static int get_used_switches(struct fpga_model* model, int y, int x,
int i, num_used, rc;
struct fpga_tile* tile;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
num_used = 0;
for (i = 0; i < tile->num_switches; i++) {
@ -2020,6 +2035,7 @@ static int write_iologic_sw(struct fpga_bits* bits, struct fpga_model* model,
int found_i[MAX_IOLOGIC_SWBLOCK];
int num_sw, num_found;
RC_CHECK(model);
if (x < LEFT_SIDE_WIDTH) {
if (x != LEFT_IO_DEVS) FAIL(EINVAL);
sw_pos = s_left_io_swpos;
@ -2079,6 +2095,7 @@ static int write_switches(struct fpga_bits* bits, struct fpga_model* model)
struct fpga_tile* tile;
int x, y, i, rc;
RC_CHECK(model);
for (x = 0; x < model->x_width; x++) {
for (y = 0; y < model->y_height; y++) {
if (is_atx(X_ROUTING_COL, model, x)
@ -2124,6 +2141,7 @@ static int write_logic(struct fpga_bits* bits, struct fpga_model* model)
uint64_t u64;
uint8_t* u8_p;
RC_CHECK(model);
for (x = LEFT_SIDE_WIDTH; x < model->x_width-RIGHT_SIDE_WIDTH; x++) {
xm_col = is_atx(X_FABRIC_LOGIC_XM_COL, model, x);
if (!xm_col && !is_atx(X_FABRIC_LOGIC_XL_COL, model, x))
@ -2206,18 +2224,15 @@ fail:
int write_model(struct fpga_bits* bits, struct fpga_model* model)
{
int i, rc;
int i;
RC_CHECK(model);
for (i = 0; i < sizeof(s_default_bits)/sizeof(s_default_bits[0]); i++)
set_bitp(bits, &s_default_bits[i]);
rc = write_switches(bits, model);
if (rc) RC_FAIL(model, rc);
rc = write_iobs(bits, model);
if (rc) RC_FAIL(model, rc);
rc = write_logic(bits, model);
if (rc) RC_FAIL(model, rc);
write_switches(bits, model);
write_iobs(bits, model);
write_logic(bits, model);
RC_RETURN(model);
}

2
libs/bit_regs.c
View File

@ -1801,6 +1801,7 @@ static int write_bits(FILE* f, struct fpga_model* model)
int nwritten, i, j, rc;
char padding_frame[FRAME_SIZE];
RC_CHECK(model);
bits.len = IOB_DATA_START + IOB_DATA_LEN;
bits.d = calloc(bits.len, /*elsize*/ 1);
if (!bits.d) FAIL(ENOMEM);
@ -1873,6 +1874,7 @@ int write_bitfile(FILE* f, struct fpga_model* model)
uint32_t u32;
int len_to_eof_pos, eof_pos, nwritten, i, rc;
RC_CHECK(model);
rc = write_header(f, "fpgatools.fp;UserID=0xFFFFFFFF",
"6slx9tqg144", "2010/05/26", "08:00:00");
if (rc) FAIL(rc);

44
libs/control.c
View File

@ -149,6 +149,7 @@ int fpga_find_iob(struct fpga_model* model, const char* sitename,
const char* name;
int i;
RC_CHECK(model);
for (i = 0; (name = fpga_enum_iob(model, i, y, x, idx)); i++) {
if (!strcmp(name, sitename))
return 0;
@ -329,6 +330,7 @@ dev_idx_t fpga_dev_idx(struct fpga_model* model,
dev_type_idx_t type_count;
dev_idx_t i;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_count = 0;
for (i = 0; i < tile->num_devs; i++) {
@ -347,6 +349,7 @@ dev_type_idx_t fdev_typeidx(struct fpga_model* model, int y, int x,
struct fpga_tile* tile;
dev_type_idx_t type_count, i;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_count = 0;
for (i = 0; i < dev_idx; i++) {
@ -431,6 +434,7 @@ str16_t fdev_logic_pinstr_i(struct fpga_model* model, pinw_idx_t idx, int ld1_ty
{
int str_i;
RC_CHECK(model);
str_i = strarray_find(&model->str, fdev_logic_pinstr(idx, ld1_type));
if (OUT_OF_U16(str_i))
{ HERE(); return STRIDX_NO_ENTRY; }
@ -529,6 +533,7 @@ int fdev_logic_setconf(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int lut, rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -591,6 +596,7 @@ int fdev_logic_a2d_out_used(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -610,6 +616,7 @@ int fdev_logic_a2d_lut(struct fpga_model* model, int y, int x, int type_idx,
char** lut_ptr;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -638,6 +645,7 @@ int fdev_logic_a2d_ff(struct fpga_model* model, int y, int x, int type_idx,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -659,6 +667,7 @@ int fdev_logic_a2d_ff5_srinit(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -677,6 +686,7 @@ int fdev_logic_a2d_out_mux(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -695,6 +705,7 @@ int fdev_logic_a2d_cy0(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -713,6 +724,7 @@ int fdev_logic_clk(struct fpga_model* model, int y, int x, int type_idx,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -731,6 +743,7 @@ int fdev_logic_sync(struct fpga_model* model, int y, int x, int type_idx,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -748,6 +761,7 @@ int fdev_logic_ce_used(struct fpga_model* model, int y, int x, int type_idx)
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -765,6 +779,7 @@ int fdev_logic_sr_used(struct fpga_model* model, int y, int x, int type_idx)
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -783,6 +798,7 @@ int fdev_logic_we_mux(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -801,6 +817,7 @@ int fdev_logic_cout_used(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -819,6 +836,7 @@ int fdev_logic_precyinit(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_LOGIC, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -841,6 +859,7 @@ int fdev_iob_input(struct fpga_model* model, int y, int x, int type_idx,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_IOB, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -861,6 +880,7 @@ int fdev_iob_output(struct fpga_model* model, int y, int x, int type_idx,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_IOB, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -893,6 +913,7 @@ int fdev_iob_IMUX(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_IOB, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -911,6 +932,7 @@ int fdev_iob_slew(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_IOB, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -929,6 +951,7 @@ int fdev_iob_drive(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_IOB, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -947,6 +970,7 @@ int fdev_bufgmux(struct fpga_model* model, int y, int x,
struct fpga_device* dev;
int rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, DEV_BUFGMUX, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -985,6 +1009,7 @@ int fdev_set_required_pins(struct fpga_model* model, int y, int x, int type,
int digits[6];
int i, j, rc;
RC_CHECK(model);
dev = fdev_p(model, y, x, type, type_idx);
if (!dev) FAIL(EINVAL);
rc = reset_required_pins(dev);
@ -1094,6 +1119,7 @@ int fpga_connpt_find(struct fpga_model* model, int y, int x,
struct fpga_tile* tile;
int i;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
for (i = 0; i < tile->num_conn_point_names; i++) {
if (tile->conn_point_names[i*2+1] == name_i)
@ -1137,6 +1163,7 @@ int fpga_find_conn(struct fpga_model* model, int search_y, int search_x,
struct fpga_tile* tile;
int i, j, dests_end;
RC_CHECK(model);
tile = YX_TILE(model, search_y, search_x);
for (i = 0; i < tile->num_conn_point_names; i++) {
dests_end = (i < tile->num_conn_point_names-1)
@ -1162,6 +1189,7 @@ swidx_t fpga_switch_first(struct fpga_model* model, int y, int x,
struct fpga_tile* tile;
int i, connpt_o;
RC_CHECK(model);
// Finds the first switch either from or to the name given.
if (name_i == STRIDX_NO_ENTRY) { HERE(); return NO_SWITCH; }
tile = YX_TILE(model, y, x);
@ -1179,6 +1207,7 @@ static swidx_t fpga_switch_search(struct fpga_model* model, int y, int x,
struct fpga_tile* tile;
int connpt_o, name_i, i;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
if (last & FIRST_SW) {
connpt_o = fpga_connpt_find(model, y, x, last & ~FIRST_SW,
@ -1214,6 +1243,7 @@ int fpga_swset_fromto(struct fpga_model* model, int y, int x,
{
swidx_t idx;
RC_CHECK(model);
set->len = 0;
idx = fpga_switch_first(model, y, x, start_switch, from_to);
while (idx != NO_SWITCH) {
@ -1231,6 +1261,7 @@ int fpga_swset_contains(struct fpga_model* model, int y, int x,
struct fpga_tile* tile;
int i;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
for (i = 0; i < set->len; i++) {
if (CONNPT_STR16(tile, SW_I(set->sw[i], from_to)) == connpt)
@ -1298,6 +1329,7 @@ int fpga_swset_level_down(struct fpga_model* model, int y, int x,
{
int i;
RC_CHECK(model);
i = 0;
while (i < set->len) {
set->sw[i] = fpga_switch_first(model, y, x,fpga_switch_str_i(
@ -1340,6 +1372,7 @@ int fpga_switch_same_fromto(struct fpga_model* model, int y, int x,
swidx_t cur_sw;
int max_len, rc;
RC_CHECK(model);
max_len = *same_len;
*same_len = 0;
if (max_len < 1) FAIL(EINVAL);
@ -1787,6 +1820,7 @@ internal_error:
int construct_sw_conns(struct sw_conns* conns, struct fpga_model* model,
int y, int x, str16_t start_switch, int from_to, int max_depth)
{
RC_CHECK(model);
memset(conns, 0, sizeof(*conns));
construct_sw_chain(&conns->chain, model, y, x, start_switch,
from_to, max_depth, /*block_list*/ 0, /*block_list_len*/ 0);
@ -1989,6 +2023,7 @@ static int fnet_useidx(struct fpga_model* model, net_idx_t new_idx)
void* new_ptr;
int new_array_size, rc;
RC_CHECK(model);
if (new_idx <= NO_NET) FAIL(EINVAL);
if (new_idx > model->highest_used_net)
model->highest_used_net = new_idx;
@ -2014,6 +2049,7 @@ int fnet_new(struct fpga_model* model, net_idx_t* new_idx)
{
int rc;
RC_CHECK(model);
// highest_used_net is initialized to NO_NET which becomes 1
rc = fnet_useidx(model, model->highest_used_net+1);
if (rc) return rc;
@ -2045,6 +2081,7 @@ int fnet_enum(struct fpga_model* model, net_idx_t last, net_idx_t* next)
{
int i;
RC_CHECK(model);
// last can be NO_NET which becomes 1 = the first net index
for (i = last+1; i <= model->highest_used_net; i++) {
if (model->nets[i-1].len) {
@ -2074,6 +2111,7 @@ int fnet_add_port(struct fpga_model* model, net_idx_t net_i,
struct fpga_net* net;
int rc;
RC_CHECK(model);
rc = fnet_useidx(model, net_i);
if (rc) FAIL(rc);
@ -2097,6 +2135,7 @@ int fnet_add_sw(struct fpga_model* model, net_idx_t net_i,
struct fpga_net* net;
int i, rc;
RC_CHECK(model);
rc = fnet_useidx(model, net_i);
if (rc) FAIL(rc);
@ -2124,6 +2163,7 @@ int fnet_remove_sw(struct fpga_model* model, net_idx_t net_i,
struct fpga_net* net;
int i, j, rc;
RC_CHECK(model);
if (net_i > model->highest_used_net)
FAIL(EINVAL);
net = &model->nets[net_i-1];
@ -2227,9 +2267,9 @@ int fnet_autoroute(struct fpga_model* model, net_idx_t net_i)
struct switch_to_rel switch_to_rel;
int i, out_i, in_i, rc;
RC_CHECK(model);
// todo: gnd and vcc nets are special and have no outpin
// but lots of inpins
net_p = fnet_get(model, net_i);
if (!net_p) FAIL(EINVAL);
out_i = -1;
@ -2405,6 +2445,7 @@ int fnet_route_to_inpins(struct fpga_model* model, net_idx_t net_i,
struct sw_set start_set, end_set;
int i, rc;
RC_CHECK(model);
net_p = fnet_get(model, net_i);
if (!net_p) FAIL(EINVAL);
from_i = strarray_find(&model->str, from);
@ -2447,6 +2488,7 @@ int froute_direct(struct fpga_model* model, int start_y, int start_x,
struct sw_set end_switches;
int i, rc;
RC_CHECK(model);
rc = fpga_swset_fromto(model, end_y, end_x, end_pt, SW_TO, &end_switches);
if (rc) FAIL(rc);
if (!end_switches.len) FAIL(EINVAL);

31
libs/floorplan.c
View File

@ -24,6 +24,7 @@ int printf_tiles(FILE* f, struct fpga_model* model)
struct fpga_tile* tile;
int x, y;
RC_CHECK(model);
for (x = 0; x < model->x_width; x++) {
fprintf(f, "\n");
for (y = 0; y < model->y_height; y++) {
@ -68,6 +69,7 @@ static int printf_IOB(FILE* f, struct fpga_model* model,
char pref[256];
int type_count, i;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_count = 0;
for (i = 0; i < tile->num_devs; i++) {
@ -295,6 +297,7 @@ static int printf_LOGIC(FILE* f, struct fpga_model* model,
char pref[256];
int type_count, i, j, rc;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_count = 0;
for (i = 0; i < tile->num_devs; i++) {
@ -663,6 +666,7 @@ static int printf_BUFGMUX(FILE* f, struct fpga_model* model,
char pref[256];
int type_count, i, rc;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_count = 0;
for (i = 0; i < tile->num_devs; i++) {
@ -753,6 +757,7 @@ static int printf_BUFIO(FILE* f, struct fpga_model* model,
char pref[256];
int type_count, i, rc;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_count = 0;
for (i = 0; i < tile->num_devs; i++) {
@ -832,6 +837,7 @@ static int printf_BSCAN(FILE* f, struct fpga_model* model,
char pref[256];
int type_count, i, rc;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_count = 0;
for (i = 0; i < tile->num_devs; i++) {
@ -891,6 +897,7 @@ int printf_devices(FILE* f, struct fpga_model* model, int config_only)
int x, y, i, rc;
struct fpga_tile* tile;
RC_CHECK(model);
for (x = 0; x < model->x_width; x++) {
for (y = 0; y < model->y_height; y++) {
rc = printf_IOB(f, model, y, x, config_only);
@ -950,6 +957,7 @@ int printf_ports(FILE* f, struct fpga_model* model)
int x, y, i, conn_point_dests_o, num_dests_for_this_conn_point;
int first_port_printed;
RC_CHECK(model);
for (x = 0; x < model->x_width; x++) {
for (y = 0; y < model->y_height; y++) {
tile = &model->tiles[y*model->x_width + x];
@ -991,6 +999,7 @@ int printf_conns(FILE* f, struct fpga_model* model)
int x, y, i, j, k, conn_point_dests_o, num_dests_for_this_conn_point;
int other_tile_x, other_tile_y, first_conn_printed;
RC_CHECK(model);
for (x = 0; x < model->x_width; x++) {
for (y = 0; y < model->y_height; y++) {
tile = &model->tiles[y*model->x_width + x];
@ -1046,6 +1055,7 @@ int printf_switches(FILE* f, struct fpga_model* model)
struct fpga_tile* tile;
int x, y, i, first_switch_printed;
RC_CHECK(model);
for (x = 0; x < model->x_width; x++) {
for (y = 0; y < model->y_height; y++) {
tile = YX_TILE(model, y, x);
@ -1068,6 +1078,7 @@ int printf_nets(FILE* f, struct fpga_model* model)
net_idx_t net_i;
int rc;
RC_CHECK(model);
net_i = NO_NET;
while (!(rc = fnet_enum(model, net_i, &net_i)) && net_i != NO_NET)
fnet_printf(f, model, net_i);
@ -1300,6 +1311,7 @@ int read_floorplan(struct fpga_model* model, FILE* f)
char line[1024];
int beg, end;
RC_CHECK(model);
while (fgets(line, sizeof(line), f)) {
next_word(line, 0, &beg, &end);
if (end == beg) continue;
@ -1318,22 +1330,15 @@ int read_floorplan(struct fpga_model* model, FILE* f)
int write_floorplan(FILE* f, struct fpga_model* model, int flags)
{
int rc;
if (!(flags & FP_NO_HEADER))
printf_version(f);
if (model->rc) {
if (model->rc)
fprintf(f, "rc %i\n", model->rc);
FAIL(model->rc);
else {
printf_devices(f, model, /*config_only*/ 1);
printf_nets(f, model);
}
rc = printf_devices(f, model, /*config_only*/ 1);
if (rc) FAIL(rc);
rc = printf_nets(f, model);
if (rc) FAIL(rc);
return 0;
fail:
return rc;
RC_RETURN(model);
}

346
libs/model_conns.c
View File

@ -3164,40 +3164,38 @@ static int connect_clk_sr(struct fpga_model* model, const char* clk_sr)
static int run_gfan(struct fpga_model* model)
{
int x, y, i, rc;
int x, y, i;
RC_CHECK(model);
// left and right IO devs
for (y = TOP_IO_TILES; y < model->y_height-BOT_IO_TILES; y++) {
if (is_aty(Y_LEFT_WIRED, model, y)) {
if ((rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
y, LEFT_IO_ROUTING, "INT_IOI_GFAN%i", 0, 1,
y, LEFT_IO_DEVS, "IOI_GFAN%i", 0))) goto xout;
y, LEFT_IO_DEVS, "IOI_GFAN%i", 0);
}
if (is_aty(Y_RIGHT_WIRED, model, y)) {
if ((rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
y, model->x_width-RIGHT_IO_ROUTING_O,
"INT_IOI_GFAN%i", 0, 1,
y, model->x_width-RIGHT_IO_DEVS_O,
"IOI_GFAN%i", 0))) goto xout;
"IOI_GFAN%i", 0);
}
}
// top and bottom IO devs
for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
if (is_atx(X_FABRIC_LOGIC_ROUTING_COL|X_CENTER_ROUTING_COL, model, x)
&& !is_atx(X_ROUTING_NO_IO, model, x)) {
for (i = 0; i < TOPBOT_IO_ROWS; i++) {
if ((rc = add_conn_range(model, NOPREF_BI_F,
TOP_OUTER_IO+i, x,
"INT_IOI_GFAN%i", 0, 1,
TOP_OUTER_IO+i, x+1,
"IOI_GFAN%i", 0))) goto xout;
if ((rc = add_conn_range(model, NOPREF_BI_F,
model->y_height-BOT_OUTER_IO-i, x,
"INT_IOI_GFAN%i", 0, 1,
model->y_height-BOT_OUTER_IO-i, x+1,
"IOI_GFAN%i", 0))) goto xout;
}
if (!is_atx(X_FABRIC_LOGIC_ROUTING_COL|X_CENTER_ROUTING_COL, model, x)
|| is_atx(X_ROUTING_NO_IO, model, x))
continue;
for (i = 0; i < TOPBOT_IO_ROWS; i++) {
add_conn_range(model, NOPREF_BI_F,
TOP_OUTER_IO+i, x, "INT_IOI_GFAN%i", 0, 1,
TOP_OUTER_IO+i, x+1, "IOI_GFAN%i", 0);
add_conn_range(model, NOPREF_BI_F,
model->y_height-BOT_OUTER_IO-i, x,
"INT_IOI_GFAN%i", 0, 1,
model->y_height-BOT_OUTER_IO-i, x+1,
"IOI_GFAN%i", 0);
}
}
// center devs
@ -3209,26 +3207,24 @@ static int run_gfan(struct fpga_model* model)
{{ "INT_IOI_GFAN%i", 0, y-1, model->center_x-CENTER_ROUTING_O },
{ "INT_INTERFACE_GFAN%i", 0, y-1, model->center_x-CENTER_LOGIC_O },
{ "DCM2_GFAN%i", 0, y-1, model->center_x-CENTER_CMTPLL_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
add_conn_net(model, NOPREF_BI_F, &net); }
{ struct w_net net = {
.last_inc = 1, .num_pts = 3, .pt =
{{ "INT_IOI_GFAN%i", 0, y+1, model->center_x-CENTER_ROUTING_O },
{ "INT_INTERFACE_GFAN%i", 0, y+1, model->center_x-CENTER_LOGIC_O },
{ "DCM1_GFAN%i", 0, y-1, model->center_x-CENTER_CMTPLL_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
add_conn_net(model, NOPREF_BI_F, &net); }
} else if (YX_TILE(model, y-1, model->center_x-CENTER_CMTPLL_O)->flags & TF_PLL_DEV) {
struct w_net net = {
.last_inc = 1, .num_pts = 3, .pt =
{{ "INT_IOI_GFAN%i", 0, y-1, model->center_x-CENTER_ROUTING_O },
{ "INT_INTERFACE_GFAN%i", 0, y-1, model->center_x-CENTER_LOGIC_O },
{ "PLL_CLB2_GFAN%i", 0, y-1, model->center_x-CENTER_CMTPLL_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout;
add_conn_net(model, NOPREF_BI_F, &net);
}
}
}
RC_RETURN(model);
xout:
return rc;
}
static int run_io_wires(struct fpga_model* model)
@ -3881,7 +3877,7 @@ static int run_dirwire(struct fpga_model *model, int start_y, int start_x,
enum wire_type wire, char bamce_start, int num_0to3)
{
struct w_net net;
int cur_y, cur_x, outer_term_hit, rc;
int cur_y, cur_x, outer_term_hit;
char cur_bamce;
RC_CHECK(model);
@ -3891,14 +3887,12 @@ static int run_dirwire(struct fpga_model *model, int start_y, int start_x,
cur_x = start_x;
cur_bamce = bamce_start;
while (1) {
rc = set_BAMCE_point(model, &net, wire, cur_bamce, num_0to3, &cur_y, &cur_x);
if (rc) RC_FAIL(model, rc);
set_BAMCE_point(model, &net, wire, cur_bamce, num_0to3, &cur_y, &cur_x);
outer_term_hit = is_atyx(YX_OUTER_TERM, model, cur_y, cur_x);
if (cur_bamce == 'E' || outer_term_hit) {
if (net.num_pts < 2) RC_FAIL(model, EINVAL);
if ((rc = add_conn_net(model, PREF_BI_F, &net))) RC_FAIL(model, rc);
add_conn_net(model, PREF_BI_F, &net);
net.num_pts = 0;
if (outer_term_hit)
break;
@ -3926,7 +3920,7 @@ static int run_dirwire_0to3(struct fpga_model *model, int start_y, int start_x,
static int run_dirwires(struct fpga_model* model)
{
int y, x, i, rc;
int y, x, i;
RC_CHECK(model);
@ -3951,57 +3945,41 @@ static int run_dirwires(struct fpga_model* model)
for (y = TOP_OUTER_IO; y <= model->y_height-BOT_OUTER_IO; y++) {
if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y))
continue;
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE4, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE4, 'C');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE4, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE4, 'A');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE2, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE2, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EL1, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_ER1, 'E');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE4, 'E');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE4, 'C');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE4, 'M');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE4, 'A');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE2, 'E');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EE2, 'M');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_EL1, 'E');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_ER1, 'E');
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW4, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW4, 'C');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW4, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW4, 'A');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW2, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW2, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WL1, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WR1, 'E');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW4, 'E');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW4, 'C');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW4, 'M');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW4, 'A');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW2, 'E');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WW2, 'M');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WL1, 'E');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_WR1, 'E');
}
for (x = LEFT_IO_ROUTING; x <= model->x_width-RIGHT_IO_ROUTING_O; x++) {
if (!is_atx(X_ROUTING_COL, model, x))
continue;
if ((rc = add_conn_bi_pref(model, TOP_INNER_ROW, x, "WW4E_S0",
TOP_FIRST_REGULAR, x, "WW4E_S0"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, TOP_INNER_ROW, x, "EL1E_S0",
TOP_FIRST_REGULAR, x, "EL1E_S0"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, TOP_INNER_ROW, x, "WR1E_S0",
TOP_FIRST_REGULAR, x, "WR1E_S0"))) RC_FAIL(model, rc);
add_conn_bi_pref(model, TOP_INNER_ROW, x, "WW4E_S0",
TOP_FIRST_REGULAR, x, "WW4E_S0");
add_conn_bi_pref(model, TOP_INNER_ROW, x, "EL1E_S0",
TOP_FIRST_REGULAR, x, "EL1E_S0");
add_conn_bi_pref(model, TOP_INNER_ROW, x, "WR1E_S0",
TOP_FIRST_REGULAR, x, "WR1E_S0");
if (!is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) {
if ((rc = add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "WW2E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "WW2E_N3"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "ER1E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "ER1E_N3"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "WL1E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "WL1E_N3"))) RC_FAIL(model, rc);
add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "WW2E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "WW2E_N3");
add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "ER1E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "ER1E_N3");
add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "WL1E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "WL1E_N3");
}
}
@ -4015,74 +3993,52 @@ static int run_dirwires(struct fpga_model* model)
continue;
if (is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) {
for (i = 0; i <= 3; i++) {
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1-i, x, W_NN4, 'B');
if (rc) RC_FAIL(model, rc);
}
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, x, W_NN2, 'B');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-2, x, W_NN2, 'B');
if (rc) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model,
for (i = 0; i <= 3; i++)
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1-i, x, W_NN4, 'B');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, x, W_NN2, 'B');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-2, x, W_NN2, 'B');
add_conn_bi_pref(model,
model->y_height-BOT_INNER_ROW-2, x, "NN2E0",
model->y_height-BOT_INNER_ROW-1, x, "NN2E_S0"))) RC_FAIL(model, rc);
model->y_height-BOT_INNER_ROW-1, x, "NN2E_S0");
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, x, W_NL1, 'B');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, x, W_NR1, 'B');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, x, W_NL1, 'B');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, x, W_NR1, 'B');
} else {
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN4, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN4, 'C');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN4, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN4, 'A');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN2, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN2, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NL1, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NR1, 'E');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN4, 'E');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN4, 'C');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN4, 'M');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN4, 'A');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN2, 'E');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NN2, 'M');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NL1, 'E');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NR1, 'E');
}
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS4, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS4, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS4, 'C');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS4, 'A');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS2, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS2, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SL1, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SR1, 'E');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS4, 'E');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS4, 'M');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS4, 'C');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS4, 'A');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS2, 'E');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SS2, 'M');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SL1, 'E');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SR1, 'E');
}
for (x = LEFT_IO_ROUTING; x <= model->x_width-RIGHT_IO_ROUTING_O; x++) {
if (!is_atx(X_ROUTING_COL, model, x))
continue;
if ((rc = add_conn_bi_pref(model, TOP_INNER_ROW, x, "NN2E_S0",
TOP_FIRST_REGULAR, x, "NN2E_S0"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, TOP_INNER_ROW, x, "NL1E_S0",
TOP_FIRST_REGULAR, x, "NL1E_S0"))) RC_FAIL(model, rc);
add_conn_bi_pref(model, TOP_INNER_ROW, x, "NN2E_S0",
TOP_FIRST_REGULAR, x, "NN2E_S0");
add_conn_bi_pref(model, TOP_INNER_ROW, x, "NL1E_S0",
TOP_FIRST_REGULAR, x, "NL1E_S0");
if (!is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) {
if ((rc = add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SS4E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SS4E_N3"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SS2E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SS2E_N3"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SR1E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SR1E_N3"))) RC_FAIL(model, rc);
add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SS4E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SS4E_N3");
add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SS2E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SS2E_N3");
add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SR1E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SR1E_N3");
}
}
@ -4093,43 +4049,31 @@ static int run_dirwires(struct fpga_model* model)
for (x = LEFT_IO_ROUTING; x <= model->x_width-RIGHT_IO_ROUTING_O; x++) {
if (!is_atx(X_ROUTING_COL, model, x))
continue;
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SE4, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SE4, 'A');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SE2, 'M');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SE4, 'M');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SE4, 'A');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SE2, 'M');
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SW4, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SW4, 'A');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SW2, 'M');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SW4, 'M');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SW4, 'A');
run_dirwire_0to3(model, TOP_INNER_ROW, x, W_SW2, 'M');
if (!is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) {
if ((rc = add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SW4E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SW4E_N3"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SW2E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SW2E_N3"))) RC_FAIL(model, rc);
add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SW4E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SW4E_N3");
add_conn_bi_pref(model, model->y_height-BOT_INNER_ROW, x, "SW2E_N3",
model->y_height-BOT_LAST_REGULAR_O, x, "SW2E_N3");
}
}
for (y = TOP_OUTER_IO; y <= model->y_height-BOT_OUTER_IO; y++) {
if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y))
continue;
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_SE4, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_SE4, 'C');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_SE2, 'E');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_SE4, 'E');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_SE4, 'C');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_SE2, 'E');
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_SW4, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_SW4, 'C');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_SW2, 'E');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_SW4, 'E');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_SW4, 'C');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_SW2, 'E');
}
//
@ -4160,16 +4104,13 @@ static int run_dirwires(struct fpga_model* model)
}
}
if (plus_two_majors != -1) {
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, plus_two_majors, W_NE4, 'B');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-2, plus_two_majors, W_NE4, 'B');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, plus_two_majors, W_NE4, 'B');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-2, plus_two_majors, W_NE4, 'B');
}
if (plus_one_major != -1) {
struct w_net net;
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, plus_one_major, W_NE2, 'B');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, plus_one_major, W_NE2, 'B');
net.last_inc = 2;
net.num_pts = 0;
@ -4180,33 +4121,25 @@ static int run_dirwires(struct fpga_model* model)
net.pt[net.num_pts].name = (i == plus_one_major) ? "NE2E%i" : "NE2M%i";
net.num_pts++;
}
rc = add_conn_net(model, PREF_BI_F, &net);
if (rc) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model,
add_conn_net(model, PREF_BI_F, &net);
add_conn_bi_pref(model,
model->y_height-BOT_INNER_ROW-1, plus_one_major, "NE2E0",
model->y_height-BOT_INNER_ROW, plus_one_major, "NE2E0"))) RC_FAIL(model, rc);
model->y_height-BOT_INNER_ROW, plus_one_major, "NE2E0");
}
} else {
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NE4, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NE4, 'A');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NE2, 'M');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NE4, 'M');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NE4, 'A');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NE2, 'M');
}
if ((rc = add_conn_bi_pref(model, TOP_INNER_ROW, x, "NE2E_S0",
TOP_FIRST_REGULAR, x, "NE2E_S0"))) RC_FAIL(model, rc);
add_conn_bi_pref(model, TOP_INNER_ROW, x, "NE2E_S0",
TOP_FIRST_REGULAR, x, "NE2E_S0");
}
for (y = TOP_OUTER_IO; y <= model->y_height-BOT_OUTER_IO; y++) {
if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y))
continue;
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_NE4, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_NE4, 'C');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, LEFT_INNER_COL, W_NE2, 'E');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_NE4, 'E');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_NE4, 'C');
run_dirwire_0to3(model, y, LEFT_INNER_COL, W_NE2, 'E');
}
//
@ -4237,47 +4170,38 @@ static int run_dirwires(struct fpga_model* model)
}
}
if (minus_two_majors != -1) {
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, minus_two_majors, W_NW4, 'B');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-2, minus_two_majors, W_NW4, 'B');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, minus_two_majors, W_NW4, 'B');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-2, minus_two_majors, W_NW4, 'B');
if ((rc = add_conn_bi_pref(model,
add_conn_bi_pref(model,
model->y_height-BOT_INNER_ROW-2, minus_two_majors, "NW4E0",
model->y_height-BOT_INNER_ROW-1, minus_two_majors, "NW4E_S0"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model,
model->y_height-BOT_INNER_ROW-1, minus_two_majors, "NW4E_S0");
add_conn_bi_pref(model,
model->y_height-BOT_INNER_ROW-1, minus_two_majors, "NW4E0",
model->y_height-BOT_INNER_ROW, minus_two_majors, "NW4E0"))) RC_FAIL(model, rc);
model->y_height-BOT_INNER_ROW, minus_two_majors, "NW4E0");
}
if (minus_one_major != -1) {
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, minus_one_major, W_NW2, 'B');
if (rc) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model,
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW-1, minus_one_major, W_NW2, 'B');
add_conn_bi_pref(model,
model->y_height-BOT_INNER_ROW-1, minus_one_major, "NW2E0",
model->y_height-BOT_INNER_ROW, minus_one_major, "NW2E0"))) RC_FAIL(model, rc);
model->y_height-BOT_INNER_ROW, minus_one_major, "NW2E0");
}
} else {
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NW4, 'M');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NW4, 'A');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NW2, 'M');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NW4, 'M');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NW4, 'A');
run_dirwire_0to3(model, model->y_height-BOT_INNER_ROW, x, W_NW2, 'M');
}
if ((rc = add_conn_bi_pref(model, TOP_INNER_ROW, x, "NW4E_S0",
TOP_FIRST_REGULAR, x, "NW4E_S0"))) RC_FAIL(model, rc);
if ((rc = add_conn_bi_pref(model, TOP_INNER_ROW, x, "NW2E_S0",
TOP_FIRST_REGULAR, x, "NW2E_S0"))) RC_FAIL(model, rc);
add_conn_bi_pref(model, TOP_INNER_ROW, x, "NW4E_S0",
TOP_FIRST_REGULAR, x, "NW4E_S0");
add_conn_bi_pref(model, TOP_INNER_ROW, x, "NW2E_S0",
TOP_FIRST_REGULAR, x, "NW2E_S0");
}
for (y = TOP_OUTER_IO; y <= model->y_height-BOT_OUTER_IO; y++) {
if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y))
continue;
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_NW4, 'E');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_NW4, 'C');
if (rc) RC_FAIL(model, rc);
rc = run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_NW2, 'E');
if (rc) RC_FAIL(model, rc);
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_NW4, 'E');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_NW4, 'C');
run_dirwire_0to3(model, y, model->x_width-RIGHT_INNER_O, W_NW2, 'E');
}
RC_RETURN(model);
}

5
libs/model_devices.c
View File

@ -19,6 +19,7 @@ int init_devices(struct fpga_model* model)
{
int x, y, i, j, rc;
RC_CHECK(model);
// DCM, PLL
for (i = 0; i < model->cfg_rows; i++) {
y = TOP_IO_TILES + HALF_ROW-1 + i*ROW_SIZE;
@ -334,6 +335,7 @@ void free_devices(struct fpga_model* model)
struct fpga_tile* tile;
int x, y, i;
// leave model->rc untouched
for (x = 0; x < model->x_width; x++) {
for (y = 0; y < model->y_height; y++) {
tile = YX_TILE(model, y, x);
@ -363,6 +365,7 @@ static int add_dev(struct fpga_model* model,
int new_dev_i;
int rc;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
if (!(tile->num_devs % DEV_INCREMENT)) {
void* new_ptr = realloc(tile->devs,
@ -397,6 +400,7 @@ static int init_iob(struct fpga_model* model, int y, int x, int idx)
int type_idx, rc;
char tmp_str[128];
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_idx = fdev_typeidx(model, y, x, idx);
if (!y)
@ -472,6 +476,7 @@ static int init_logic(struct fpga_model* model, int y, int x, int idx)
const char* pre;
int i, j, rc;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
if (tile->devs[idx].subtype == LOGIC_M)
pre = "M_";

50
libs/model_helper.c
View File

@ -138,12 +138,13 @@ int add_connpt_name(struct fpga_model* model, int y, int x,
uint16_t _name_i;
int rc, i;
RC_CHECK(model);
tile = &model->tiles[y * model->x_width + x];
rc = strarray_add(&model->str, connpt_name, &i);
if (rc) return rc;
if (i > 0xFFFF) {
fprintf(stderr, "Internal error in %s:%i\n", __FILE__, __LINE__);
return -1;
return EINVAL;
}
_name_i = i;
if (name_i) *name_i = i;
@ -200,6 +201,7 @@ int add_connpt_2(struct fpga_model* model, int y, int x,
char name_buf[64];
int rc;
RC_CHECK(model);
snprintf(name_buf, sizeof(name_buf), "%s%s", connpt_name, suffix1);
rc = add_connpt_name(model, y, x, name_buf, dup_warn,
/*name_i*/ 0, /*connpt_o*/ 0);
@ -223,6 +225,7 @@ int add_conn_uni(struct fpga_model* model, int y1, int x1, const char* name1, in
uint16_t* new_ptr;
int conn_start, num_conn_point_dests_for_this_wire, rc, j, conn_point_o;
RC_CHECK(model);
rc = add_connpt_name(model, y1, x1, name1, 0 /* warn_if_duplicate */,
&name1_i, &conn_point_o);
if (rc) goto xout;
@ -231,7 +234,7 @@ int add_conn_uni(struct fpga_model* model, int y1, int x1, const char* name1, in
if (rc) return rc;
if (j > 0xFFFF) {
fprintf(stderr, "Internal error in %s:%i\n", __FILE__, __LINE__);
return -1;
return EINVAL;
}
name2_i = j;
tile = &model->tiles[y1 * model->x_width + x1];
@ -262,7 +265,7 @@ int add_conn_uni(struct fpga_model* model, int y1, int x1, const char* name1, in
new_ptr = realloc(tile->conn_point_dests, (tile->num_conn_point_dests+CONNS_INCREMENT)*3*sizeof(uint16_t));
if (!new_ptr) {
fprintf(stderr, "Out of memory %s:%i\n", __FILE__, __LINE__);
return 0;
return ENOMEM;
}
tile->conn_point_dests = new_ptr;
}
@ -293,27 +296,27 @@ int add_conn_uni_pref(struct fpga_model* model,
int y1, int x1, const char* name1,
int y2, int x2, const char* name2)
{
return add_conn_uni(model,
y1, x1, wpref(model, y1, x1, name1),
y2, x2, wpref(model, y2, x2, name2));
add_conn_uni(model, y1, x1, wpref(model, y1, x1, name1),
y2, x2, wpref(model, y2, x2, name2));
RC_RETURN(model);
}
int add_conn_bi(struct fpga_model* model,
int y1, int x1, const char* name1,
int y2, int x2, const char* name2)
{
int rc = add_conn_uni(model, y1, x1, name1, y2, x2, name2);
if (rc) return rc;
return add_conn_uni(model, y2, x2, name2, y1, x1, name1);
add_conn_uni(model, y1, x1, name1, y2, x2, name2);
add_conn_uni(model, y2, x2, name2, y1, x1, name1);
RC_RETURN(model);
}
int add_conn_bi_pref(struct fpga_model* model,
int y1, int x1, const char* name1,
int y2, int x2, const char* name2)
{
return add_conn_bi(model,
y1, x1, wpref(model, y1, x1, name1),
y2, x2, wpref(model, y2, x2, name2));
add_conn_bi(model, y1, x1, wpref(model, y1, x1, name1),
y2, x2, wpref(model, y2, x2, name2));
RC_RETURN(model);
}
int add_conn_range(struct fpga_model* model, add_conn_f add_conn_func,
@ -321,25 +324,26 @@ int add_conn_range(struct fpga_model* model, add_conn_f add_conn_func,
int y2, int x2, const char* name2, int start2)
{
char buf1[128], buf2[128];
int rc, i;
int i;
RC_CHECK(model);
for (i = start1; i <= last1; i++) {
snprintf(buf1, sizeof(buf1), name1, i);
if (start2 & COUNT_DOWN)
snprintf(buf2, sizeof(buf2), name2, (start2 & COUNT_MASK)-(i-start1));
else
snprintf(buf2, sizeof(buf2), name2, (start2 & COUNT_MASK)+(i-start1));
rc = (*add_conn_func)(model, y1, x1, buf1, y2, x2, buf2);
if (rc) return rc;
(*add_conn_func)(model, y1, x1, buf1, y2, x2, buf2);
}
return 0;
RC_RETURN(model);
}
int add_conn_net(struct fpga_model* model, add_conn_f add_conn_func, const struct w_net *net)
{
int i, j, rc;
int i, j;
if (net->num_pts < 2) FAIL(EINVAL);
RC_CHECK(model);
if (net->num_pts < 2) RC_FAIL(model, EINVAL);
for (i = 0; i < net->num_pts; i++) {
for (j = i+1; j < net->num_pts; j++) {
// We are buildings nets like a NN2 B-M-E net where
@ -349,7 +353,7 @@ int add_conn_net(struct fpga_model* model, add_conn_f add_conn_func, const struc
if (net->pt[j].y == net->pt[i].y
&& net->pt[j].x == net->pt[i].x)
continue;
rc = add_conn_range(model, add_conn_func,
add_conn_range(model, add_conn_func,
net->pt[i].y, net->pt[i].x,
net->pt[i].name,
net->pt[i].start_count,
@ -357,12 +361,9 @@ int add_conn_net(struct fpga_model* model, add_conn_f add_conn_func, const struc
net->pt[j].y, net->pt[j].x,
net->pt[j].name,
net->pt[j].start_count);
if (rc) FAIL(rc);
}
}
return 0;
fail:
return rc;
RC_RETURN(model);
}
#define SWITCH_ALLOC_INCREMENT 256
@ -380,6 +381,7 @@ int add_switch(struct fpga_model* model, int y, int x, const char* from,
int rc, i, from_idx, to_idx, from_connpt_o, to_connpt_o;
uint32_t new_switch;
RC_CHECK(model);
// later this can be strarray_find() and not strarray_add(), but
// then we need all wires and ports to be present first...
#ifdef DBG_ALLOW_ADDPOINTS
@ -469,6 +471,7 @@ int add_switch_set(struct fpga_model* model, int y, int x, const char* prefix,
int i, j, from_len, to_len, rc;
char from[64], to[64];
RC_CHECK(model);
if (!prefix) prefix = "";
for (i = 0; pairs[i*2][0]; i++) {
snprintf(from, sizeof(from), "%s%s", prefix, pairs[i*2]);
@ -500,6 +503,7 @@ int replicate_switches_and_names(struct fpga_model* model,
struct fpga_tile* from_tile, *to_tile;
int rc;
RC_CHECK(model);
from_tile = YX_TILE(model, y_from, x_from);
to_tile = YX_TILE(model, y_to, x_to);
if (to_tile->num_conn_point_names

2
libs/model_ports.c
View File

@ -19,6 +19,7 @@ static int init_iologic_ports(struct fpga_model* model, int y, int x,
static const char* prefix, *suffix1, *suffix2;
int rc, i;
RC_CHECK(model);
switch (side) {
case TOP_S: prefix = "TIOI"; break;
case BOTTOM_S: prefix = "BIOI"; break;
@ -193,6 +194,7 @@ int init_ports(struct fpga_model* model, int dup_warn)
{
int x, y, i, j, k, row_num, row_pos, rc;
RC_CHECK(model);
// inner and outer IO tiles (ILOGIC/ILOGIC/IODELAY)
for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
if (has_device(model, TOP_OUTER_IO, x, DEV_ILOGIC)) {

1
libs/model_tiles.c
View File

@ -15,6 +15,7 @@ int init_tiles(struct fpga_model* model)
char cur_cfgcol, last_col;
struct fpga_tile* tile_i0;
RC_CHECK(model);
tile_rows = 1 /* middle */ + (8+1+8)*model->cfg_rows + 2+2 /* two extra tiles at top and bottom */;
tile_columns = LEFT_SIDE_WIDTH + RIGHT_SIDE_WIDTH;
for (i = 0; model->cfg_columns[i] != 0; i++) {