suzanne.soy/fpgatools
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

higher-level compiler warnings - thanks to Werner!

Browse Source
This commit is contained in:
Wolfgang Spraul 2012-08-14 03:04:33 +02:00
parent 7017fdbb8a
commit 884c03657a
12 changed files with 119 additions and 117 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
Makefile
View File

@ -8,7 +8,8 @@
.PHONY: all clean
.SECONDARY:
CFLAGS = -Wall -g
CFLAGS = -Wall -Wshadow -Wmissing-prototypes -Wmissing-declarations \
-Wno-format-zero-length -Ofast
LDLIBS = -lxml2
MODEL_OBJ = model_main.o model_tiles.o model_devices.o model_ports.o model_conns.o model_switches.o model_helper.o
@ -106,14 +107,14 @@ clean:
helper.o $(MODEL_OBJ) hstrrep hstrrep.o \
sort_seq sort_seq.o \
merge_seq merge_seq.o \
xc6slx9_empty.fp xc6slx9_empty.conns xc6slx9_empty.ports \
xc6slx9.svg \
compare_other.tiles compare_other.devices compare_other.conns compare_other.ports \
compare_other.sw \
xc6slx9_empty.fp xc6slx9.svg \
xc6slx9_empty.tiles xc6slx9_empty.devices xc6slx9_empty.conns \
xc6slx9_empty.ports xc6slx9_empty.sw \
xc6slx9_empty.ports xc6slx9_empty.sw xc6slx9_empty.nets \
compare_other.tiles compare_other.devices compare_other.conns compare_other.ports \
compare_other.sw compare_other.nets \
compare_tiles_matching.txt compare_tiles_diff.txt compare_tiles_extra.txt \
compare_devices_matching.txt compare_devices_diff.txt compare_devices_extra.txt \
compare_conns_matching.txt compare_conns_diff.txt compare_conns_extra.txt \
compare_ports_matching.txt compare_ports_diff.txt compare_ports_extra.txt \
compare_sw_matching.txt compare_sw_diff.txt compare_sw_extra.txt
compare_sw_matching.txt compare_sw_diff.txt compare_sw_extra.txt \
compare_nets_matching.txt compare_nets_diff.txt compare_nets_extra.txt

10
bit2txt.c
View File

@ -209,7 +209,7 @@ static cfg_atom_t ramb16_atoms[] =
int g_cmd_frames = 0;
int g_cmd_info = 0; // whether to print #I info messages (offsets and others)
void print_ramb16_cfg(ramb16_cfg_t* cfg)
static void print_ramb16_cfg(ramb16_cfg_t* cfg)
{
char bits[512];
uint8_t u8;
@ -293,7 +293,7 @@ void print_ramb16_cfg(ramb16_cfg_t* cfg)
printf("}\n");
}
int FAR_pos(int FAR_row, int FAR_major, int FAR_minor)
static int FAR_pos(int FAR_row, int FAR_major, int FAR_minor)
{
int result, i;
@ -308,7 +308,7 @@ int FAR_pos(int FAR_row, int FAR_major, int FAR_minor)
return result + FAR_minor*130;
}
int full_map(uint8_t* bit_file, int bf_len, int first_FAR_off,
static int full_map(uint8_t* bit_file, int bf_len, int first_FAR_off,
uint8_t** bits, int* bits_len, int idcode, int FLR_len, int* outdelta)
{
int src_off, packet_hdr_type, packet_hdr_opcode;
@ -503,7 +503,7 @@ success:
return 0;
}
void printf_clb(uint8_t* maj_bits, int row, int major)
static void printf_clb(uint8_t* maj_bits, int row, int major)
{
int i, j, start, max_idx, frame_off;
const char* lut_str;
@ -604,7 +604,7 @@ void printf_clb(uint8_t* maj_bits, int row, int major)
}
}
void printf_bits(uint8_t* bits, int bits_len, int idcode)
static void printf_bits(uint8_t* bits, int bits_len, int idcode)
{
int row, major, minor, i, j, off, bram_data_start;
int offset_in_frame, newline;

12
helper.c
View File

@ -7,7 +7,7 @@
#include "helper.h"
void printf_help()
void printf_help(void)
{
printf("\n"
"bit2txt %s - convert FPGA bitstream to text\n"
@ -150,7 +150,7 @@ int printf_header(uint8_t* d, int len, int inpos, int* outdelta)
const int lut_base_vars[6] = {0 /* A1 */, 1, 0 /* A3 - not used */,
0, 0, 1 /* A6 */};
int bool_nextlen(const char* expr, int len)
static int bool_nextlen(const char* expr, int len)
{
int i, depth;
@ -183,7 +183,7 @@ int bool_nextlen(const char* expr, int len)
// + or, * and, @ xor, ~ not
// var must point to array of A1..A6 variables
int bool_eval(const char* expr, int len, const int* var)
static int bool_eval(const char* expr, int len, const int* var)
{
int i, negate, result, oplen;
@ -233,7 +233,7 @@ fail:
return -1;
}
int parse_boolexpr(const char* expr, uint64_t* lut)
static int parse_boolexpr(const char* expr, uint64_t* lut)
{
int i, j, result, vars[6];
@ -640,7 +640,7 @@ uint64_t read_lut64(uint8_t* two_minors, int off_in_frame)
return lut64;
}
int get_vm_mb()
int get_vm_mb(void)
{
FILE* statusf = fopen("/proc/self/status", "r");
char line[1024];
@ -654,7 +654,7 @@ int get_vm_mb()
return (vm_size+1023)/1024;
}
int get_random()
int get_random(void)
{
int random_f, random_num;
random_f = open("/dev/urandom", O_RDONLY);

6
helper.h
View File

@ -18,7 +18,7 @@
#define ABORT(expr) if (expr) { fprintf(stderr, "Internal error in %s:%i\n", __FILE__, __LINE__); exit(1); }
void printf_help();
void printf_help(void);
const char* bitstr(uint32_t value, int digits);
void hexdump(int indent, const uint8_t* data, int len);
@ -73,8 +73,8 @@ void printf_extrabits(uint8_t* maj_bits, int start_minor, int num_minors,
int start_bit, int num_bits, int row, int major);
uint64_t read_lut64(uint8_t* two_minors, int off_in_frame);
int get_vm_mb();
int get_random();
int get_vm_mb(void);
int get_random(void);
int compare_with_number(const char* a, const char* b);
void next_word(const char* s, int start, int* beg, int* end);
int to_i(const char* s, int len);

16
hstrrep.c
View File

@ -17,7 +17,7 @@
int main(int argc, char** argv)
{
char line[1024], search_str[1024], replace_str[1024];
char* next_word, *lasts;
char* next_wrd, *lasts;
const char* replace_ptr;
struct hashed_strarray search_arr, replace_arr;
FILE* fp = 0;
@ -82,16 +82,16 @@ int main(int argc, char** argv)
goto xout;
}
while (fgets(line, sizeof(line), fp)) {
next_word = strtok_r(line, " \n", &lasts);
if (next_word) {
next_wrd = strtok_r(line, " \n", &lasts);
if (next_wrd) {
do {
rc = strarray_find(&search_arr, next_word, &search_idx);
rc = strarray_find(&search_arr, next_wrd, &search_idx);
if (rc) {
fprintf(stderr, "Internal error in %s:%i\n", __FILE__, __LINE__);
goto xout;
}
if (search_idx == STRIDX_NO_ENTRY)
fputs(next_word, stdout);
fputs(next_wrd, stdout);
else {
replace_ptr = strarray_lookup(&replace_arr, search_idx);
if (!replace_ptr) {
@ -100,10 +100,10 @@ int main(int argc, char** argv)
}
fputs(replace_ptr, stdout);
}
next_word = strtok_r(0, " \n", &lasts);
if (next_word)
next_wrd = strtok_r(0, " \n", &lasts);
if (next_wrd)
putchar(' ');
} while ( next_word );
} while ( next_wrd );
putchar('\n');
}
}

6
merge_seq.c
View File

@ -182,8 +182,10 @@ static int merge_line(struct line_buf* first_l, struct line_buf* second_l)
// continuation of the '3'.
if (s_start != first_l->left_digit_start_o)
return 0;
if (second_num != first_l->left_digit_base + first_l->sequence_size + 1)
if (second_num != first_l->left_digit_base
+ first_l->sequence_size + 1)
return 0;
first_num = -1; // to suppress compiler warning
} else {
first_num = to_i(&first_l->buf[f_start], f_end-f_start);
if (second_num != first_num + 1)
@ -305,7 +307,7 @@ int main(int argc, char** argv)
struct line_buf read_ahead[READ_AHEAD_SIZE];
int read_ahead_get, read_ahead_put, second_line, eof_reached, try_count;
FILE* fp = 0;
int last_merge_try, rc;
int last_merge_try, rc = -1;
if (argc < 2) {
fprintf(stderr,

6
model.h
View File

@ -264,9 +264,9 @@ int is_atyx(int check, struct fpga_model* model, int y, int x);
void is_in_row(const struct fpga_model* model, int y,
int* row_num, int* row_pos);
// row_num() and row_pos() return -1 if y is outside of a row
int row_num(int y, struct fpga_model* model);
int row_pos(int y, struct fpga_model* model);
// which_row() and pos_in_row() return -1 if y is outside of a row
int which_row(int y, struct fpga_model* model);
int pos_in_row(int y, struct fpga_model* model);
const char* logicin_s(int wire, int routing_io);

126
model_conns.c
View File

@ -320,41 +320,41 @@ static int run_term_wires(struct fpga_model* model)
y = TOP_INNER_ROW;
if (has_device(model, y+1, x, DEV_ILOGIC)) {
{struct w_net net = {
{struct w_net n = {
3,
{{ "TTERM_CLB_IOCE%i_S", 0, y, x },
{ "TIOI_IOCE%i", 0, y+1, x },
{ "TIOI_INNER_IOCE%i", 0, y+2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
{struct w_net net = {
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
{struct w_net n = {
3,
{{ "TTERM_CLB_IOCLK%i_S", 0, y, x },
{ "TIOI_IOCLK%i", 0, y+1, x },
{ "TIOI_INNER_IOCLK%i", 0, y+2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
{struct w_net net = {
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
{struct w_net n = {
0,
{{ "TTERM_CLB_PCICE_S", 0, y, x },
{ "IOI_PCI_CE", 0, y+1, x },
{ "IOI_PCI_CE", 0, y+2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
{struct w_net net = {
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
{struct w_net n = {
1,
{{ "TTERM_CLB_PLLCE%i_S", 0, y, x },
{ "TIOI_PLLCE%i", 0, y+1, x },
{ "TIOI_INNER_PLLCE%i", 0, y+2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
{struct w_net net = {
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
{struct w_net n = {
1,
{{ "TTERM_CLB_PLLCLK%i_S", 0, y, x },
{ "TIOI_PLLCLK%i", 0, y+1, x },
{ "TIOI_INNER_PLLCLK%i", 0, y+2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
}
//
@ -367,49 +367,49 @@ static int run_term_wires(struct fpga_model* model)
if (has_device(model, y-1, x, DEV_ILOGIC)) {
// IOCE
{struct w_net net = {
{struct w_net n = {
3,
{{ "BTERM_CLB_CEOUT%i_N", 0, y, x },
{ "TIOI_IOCE%i", 0, y-1, x },
{ "BIOI_INNER_IOCE%i", 0, y-2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
// IOCLK
{struct w_net net = {
{struct w_net n = {
3,
{{ "BTERM_CLB_CLKOUT%i_N", 0, y, x },
{ "TIOI_IOCLK%i", 0, y-1, x },
{ "BIOI_INNER_IOCLK%i", 0, y-2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
// PCI_CE
{struct w_net net = {
{struct w_net n = {
0,
{{ "BTERM_CLB_PCICE_N", 0, y, x },
{ "IOI_PCI_CE", 0, y-1, x },
{ "IOI_PCI_CE", 0, y-2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
// PLLCE
{struct w_net net = {
{struct w_net n = {
1,
{{ "BTERM_CLB_PLLCEOUT%i_N", 0, y, x },
{ "TIOI_PLLCE%i", 0, y-1, x },
{ "BIOI_INNER_PLLCE%i", 0, y-2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
// PLLCLK
{struct w_net net = {
{struct w_net n = {
1,
{{ "BTERM_CLB_PLLCLKOUT%i_N", 0, y, x },
{ "TIOI_PLLCLK%i", 0, y-1, x },
{ "BIOI_INNER_PLLCLK%i", 0, y-2, x },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
}
}
@ -425,8 +425,6 @@ static int run_term_wires(struct fpga_model* model)
// top
//
{
int next_net_o;
struct w_net net;
// strings are filled in below - must match offsets
struct seed_data seeds[] = {
/* 0 */ { X_FABRIC_LOGIC_ROUTING_COL | X_CENTER_ROUTING_COL },
@ -575,8 +573,6 @@ static int run_term_wires(struct fpga_model* model)
// bottom
//
{
int next_net_o;
struct w_net net;
// strings are filled in below - must match offsets
struct seed_data seeds[] = {
/* 0 */ { X_FABRIC_ROUTING_COL | X_FABRIC_MACC_COL
@ -975,7 +971,6 @@ static int run_gclk_horiz_regs(struct fpga_model* model)
{
int x, i, rc, left_half;
int gclk_sep_pos, start1, last1, start2;
char* gclk_sep_str;
//
// Run a set of wire strings horizontally through the entire
@ -1216,6 +1211,7 @@ static int run_gclk_horiz_regs(struct fpga_model* model)
{ X_INNER_RIGHT, "REGH_RTERM_CKPIN%i" },
{ X_OUTER_RIGHT, "REGR_CKPIN%i" },
{ 0 }};
char* gclk_sep_str;
left_half = 1;
seed_strx(model, ckpin_seeds);
@ -1428,22 +1424,22 @@ static int run_gclk_vert_regs(struct fpga_model* model)
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout;
// a few local gclk networks at the center top and bottom
{ struct w_net net = {
{ struct w_net n = {
1,
{{ "REGT_GCLK%i", 0, TOP_OUTER_ROW, model->center_x-1 },
{ "REGT_TTERM_GCLK%i", 0, TOP_INNER_ROW, model->center_x-1 },
{ "REGV_TTERM_GCLK%i", 0, TOP_INNER_ROW, model->center_x },
{ "BUFPLL_TOP_GCLK%i", 0, TOP_INNER_ROW, model->center_x+1 },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
{ struct w_net net = {
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
{ struct w_net n = {
1,
{{ "REGB_GCLK%i", 0, model->y_height-1, model->center_x-1 },
{ "REGB_BTERM_GCLK%i", 0, model->y_height-2, model->center_x-1 },
{ "REGV_BTERM_GCLK%i", 0, model->y_height-2, model->center_x },
{ "BUFPLL_BOT_GCLK%i", 0, model->y_height-2, model->center_x+1 },
{ "" }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) goto xout; }
// wire up gclk from tterm down to top 8 rows at center_x+1
for (i = TOP_IO_TILES; i <= TOP_IO_TILES+HALF_ROW; i++) {
@ -1729,7 +1725,7 @@ xout:
static const char* s_4wire = "BAMCE";
int wire_SS4E_N3(struct fpga_model* model, const struct w_net* net)
static int wire_SS4E_N3(struct fpga_model* model, const struct w_net* net)
{
int i, j, rc, e_y, e_x, extra_n3;
@ -1744,7 +1740,7 @@ int wire_SS4E_N3(struct fpga_model* model, const struct w_net* net)
&& !is_atx(X_FABRIC_BRAM_ROUTING_COL, model, e_x))
if ((rc = add_conn_bi_pref(model, e_y, e_x, "SS4E_N3", e_y+1, e_x, "SS4E_N3"))) goto xout;
if ((rc = add_conn_bi_pref(model, e_y, e_x, "SS4E3", e_y-1, e_x, "SS4E_N3"))) goto xout;
if (row_pos(e_y-1, model) == HCLK_POS
if (pos_in_row(e_y-1, model) == HCLK_POS
|| IS_CENTER_Y(e_y-1, model)) {
if ((rc = add_conn_bi_pref(model, e_y, e_x, "SS4E3", e_y-2, e_x, "SS4E_N3"))) goto xout;
if ((rc = add_conn_bi_pref(model, e_y-1, e_x, "SS4E_N3", e_y-2, e_x, "SS4E_N3"))) goto xout;
@ -1814,7 +1810,7 @@ static int run_direction_wires(struct fpga_model* model)
break;
}
if (IS_CENTER_Y(y+j, model)
|| row_pos(y+j, model) == HCLK_POS) {
|| pos_in_row(y+j, model) == HCLK_POS) {
ABORT(!i);
net.pts[j].name = pf("SS4%c%%i", s_4wire[i-1]);
j++;
@ -1852,7 +1848,7 @@ static int run_direction_wires(struct fpga_model* model)
}
net.pts[j].name = pf("NN4%c%%i", s_4wire[i]);
if (IS_CENTER_Y(y-j, model)
|| row_pos(y-j, model) == HCLK_POS) {
|| pos_in_row(y-j, model) == HCLK_POS) {
ABORT(!i);
i--;
}
@ -1886,34 +1882,34 @@ static int run_direction_wires(struct fpga_model* model)
// NR1
if (is_atyx(YX_ROUTING_TILE, model, y, x)) {
if (is_aty(Y_INNER_TOP, model, y-1)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NR1B%i", 0, y, x },
{ "NR1B%i", 0, y-1, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
} else if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y-1)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NR1B%i", 0, y, x },
{ "NR1E%i", 0, y-1, x },
{ "NR1E%i", 0, y-2, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
} else {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NR1B%i", 0, y, x },
{ "NR1E%i", 0, y-1, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if (is_aty(Y_INNER_BOTTOM, model, y+1) && !is_atx(X_ROUTING_TO_BRAM_COL, model, x)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NR1E%i", 0, y, x },
{ "NR1E%i", 0, y+1, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
}
}
}
@ -1921,47 +1917,47 @@ static int run_direction_wires(struct fpga_model* model)
// NN2
if (is_atyx(YX_ROUTING_TILE, model, y, x)) {
if (is_aty(Y_INNER_TOP, model, y-1)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NN2B%i", 0, y, x },
{ "NN2B%i", 0, y-1, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
{ struct w_net net = {
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
{ struct w_net n = {
0,
{{ "NN2E_S0", 0, y, x },
{ "NN2E_S0", 0, y-1, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
} else if (is_aty(Y_INNER_TOP, model, y-2)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NN2B%i", 0, y, x },
{ "NN2M%i", 0, y-1, x },
{ "NN2M%i", 0, y-2, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
} else if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y-1)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NN2B%i", 0, y, x },
{ "NN2M%i", 0, y-1, x },
{ "NN2M%i", 0, y-2, x },
{ "NN2E%i", 0, y-3, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if ((rc = add_conn_bi_pref(model, y-1, x, "NN2M0", y-2, x, "NN2E_S0"))) goto xout;
if ((rc = add_conn_bi_pref(model, y-3, x, "NN2E0", y-2, x, "NN2E_S0"))) goto xout;
if ((rc = add_conn_bi_pref(model, y, x, "NN2B0", y-2, x, "NN2E_S0"))) goto xout;
} else if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y-2)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NN2B%i", 0, y, x },
{ "NN2M%i", 0, y-1, x },
{ "NN2E%i", 0, y-2, x },
{ "NN2E%i", 0, y-3, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if ((rc = add_conn_bi_pref(model, y, x, "NN2B0", y-1, x, "NN2E_S0"))) goto xout;
if ((rc = add_conn_bi_pref(model, y, x, "NN2B0", y-2, x, "NN2E_S0"))) goto xout;
if ((rc = add_conn_bi_pref(model, y-2, x, "NN2E0", y-1, x, "NN2E_S0"))) goto xout;
@ -1970,25 +1966,25 @@ static int run_direction_wires(struct fpga_model* model)
if ((rc = add_conn_bi_pref(model, y-2, x, "NN2E_S0", y-3, x, "NN2E0"))) goto xout;
if ((rc = add_conn_bi_pref(model, y-3, x, "NN2E0", y-1, x, "NN2E_S0"))) goto xout;
} else {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NN2B%i", 0, y, x },
{ "NN2M%i", 0, y-1, x },
{ "NN2E%i", 0, y-2, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if ((rc = add_conn_bi(model, y, x, "NN2B0", y-1, x, "NN2E_S0"))) goto xout;
if ((rc = add_conn_bi(model, y-2, x, "NN2E0", y-1, x, "NN2E_S0"))) goto xout;
if (is_aty(Y_INNER_BOTTOM, model, y+1)) {
if ((rc = add_conn_bi(model, y, x, "NN2E_S0", y-1, x, "NN2E0"))) goto xout;
if (!is_atx(X_ROUTING_TO_BRAM_COL, model, x)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "NN2E%i", 0, y-1, x },
{ "NN2M%i", 0, y, x },
{ "NN2M%i", 0, y+1, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if ((rc = add_conn_range(model, PREF_BI_F, y, x, "NN2E%i", 0, 3, y+1, x, "NN2E%i", 0))) goto xout;
if ((rc = add_conn_bi(model, y, x, "NN2E0", y+1, x, "IOI_BTERM_NN2E_S0"))) goto xout;
if ((rc = add_conn_bi(model, y, x, "NN2E_S0", y+1, x, "IOI_BTERM_NN2M0"))) goto xout;
@ -2000,14 +1996,14 @@ static int run_direction_wires(struct fpga_model* model)
// SS2
if (is_atyx(YX_ROUTING_TILE, model, y, x)) {
if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y+2)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "SS2B%i", 0, y, x },
{ "SS2M%i", 0, y+1, x },
{ "SS2M%i", 0, y+2, x },
{ "SS2E%i", 0, y+3, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if ((rc = add_conn_bi_pref(model, y, x, "SS2B3", y+1, x, "SS2E_N3"))) goto xout;
if ((rc = add_conn_bi_pref(model, y+1, x, "SS2E_N3", y+2, x, "SS2E_N3"))) goto xout;
@ -2019,25 +2015,25 @@ static int run_direction_wires(struct fpga_model* model)
if ((rc = add_conn_bi_pref(model, y+1, x, "SS2M3", y+2, x, "SS2E_N3"))) goto xout;
if ((rc = add_conn_bi_pref(model, y+2, x, "SS2B3", y+3, x, "SS2E_N3"))) goto xout;
} else if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS, model, y+1)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "SS2B%i", 0, y, x },
{ "SS2B%i", 0, y+1, x },
{ "SS2M%i", 0, y+2, x },
{ "SS2E%i", 0, y+3, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if ((rc = add_conn_bi_pref(model, y, x, "SS2B3", y+2, x, "SS2E_N3"))) goto xout;
if ((rc = add_conn_bi_pref(model, y+2, x, "SS2E_N3", y+3, x, "SS2E3"))) goto xout;
} else if (is_aty(Y_INNER_BOTTOM, model, y+2)) {
if (!is_atx(X_ROUTING_TO_BRAM_COL, model, x)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "SS2B%i", 0, y, x },
{ "SS2M%i", 0, y+1, x },
{ "SS2M%i", 0, y+2, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
}
} else if (is_aty(Y_INNER_BOTTOM, model, y+1)) {
if (!is_atx(X_ROUTING_TO_BRAM_COL, model, x)) {
@ -2046,25 +2042,25 @@ static int run_direction_wires(struct fpga_model* model)
}
} else {
if (is_aty(Y_INNER_TOP, model, y-1)) {
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "SS2M%i", 0, y-1, x },
{ "SS2M%i", 0, y, x },
{ "SS2E%i", 0, y+1, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if ((rc = add_conn_range(model, PREF_BI_F, y, x, "SS2E%i", 0, 3, y-1, x, "SS2E%i", 0))) goto xout;
if ((rc = add_conn_bi_pref(model, y, x, "SS2E3", y-1, x, "SS2E_N3"))) goto xout;
if ((rc = add_conn_bi_pref(model, y, x, "SS2E_N3", y-1, x, "SS2M3"))) goto xout;
if ((rc = add_conn_bi_pref(model, y, x, "SS2E_N3", y+1, x, "SS2E3"))) goto xout;
}
{ struct w_net net = {
{ struct w_net n = {
3,
{{ "SS2B%i", 0, y, x },
{ "SS2M%i", 0, y+1, x },
{ "SS2E%i", 0, y+2, x },
{ "" }}};
if ((rc = add_conn_net(model, PREF_BI_F, &net))) goto xout; }
if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; }
if ((rc = add_conn_bi_pref(model, y, x, "SS2B3", y+1, x, "SS2E_N3"))) goto xout;
if ((rc = add_conn_bi_pref(model, y+1, x, "SS2E_N3", y+2, x, "SS2E3"))) goto xout;
}

4
model_helper.c
View File

@ -584,14 +584,14 @@ void is_in_row(const struct fpga_model* model, int y,
if (row_pos) *row_pos = y%(8+1+8);
}
int row_num(int y, struct fpga_model* model)
int which_row(int y, struct fpga_model* model)
{
int result;
is_in_row(model, y, &result, 0 /* row_pos */);
return result;
}
int row_pos(int y, struct fpga_model* model)
int pos_in_row(int y, struct fpga_model* model)
{
int result;
is_in_row(model, y, 0 /* row_num */, &result);

6
model_ports.c
View File

@ -413,11 +413,11 @@ int init_ports(struct fpga_model* model)
pref[1] = "XX";
}
for (k = 0; k <= 1; k++) {
rc = add_connpt_name(model, y, x, pf("%s_CE", pref[k], i));
rc = add_connpt_name(model, y, x, pf("%s_CE", pref[k]));
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_SR", pref[k], i));
rc = add_connpt_name(model, y, x, pf("%s_SR", pref[k]));
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_CLK", pref[k], i));
rc = add_connpt_name(model, y, x, pf("%s_CLK", pref[k]));
if (rc) goto xout;
for (i = 'A'; i <= 'D'; i++) {
for (j = 1; j <= 6; j++) {

19
model_switches.c
View File

@ -21,7 +21,6 @@ int init_switches(struct fpga_model* model)
rc = init_logic_switches(model);
if (rc) goto xout;
return 0;
rc = init_iologic_switches(model);
if (rc) goto xout;
@ -728,7 +727,7 @@ enum wire_type wire_to_len(enum wire_type w, int first_len)
ABORT(1);
}
enum wire_type wire_to_NESW4(enum wire_type w)
static enum wire_type wire_to_NESW4(enum wire_type w)
{
// normalizes any of the 8 directions to just N/E/S/W
// by going back to an even number.
@ -751,7 +750,7 @@ struct set_of_switches
struct one_switch s[64];
};
void add_switch_range(struct set_of_switches* dest,
static void add_switch_range(struct set_of_switches* dest,
enum wire_type end_wire, int end_from, int end_to,
enum wire_type beg_wire, int beg_from)
{
@ -763,7 +762,7 @@ void add_switch_range(struct set_of_switches* dest,
}
}
void add_switch_E3toB0(struct set_of_switches* dest,
static void add_switch_E3toB0(struct set_of_switches* dest,
enum wire_type end_wire, enum wire_type beg_wire)
{
const char* end_wire_s = wire_base(end_wire);
@ -775,7 +774,7 @@ void add_switch_E3toB0(struct set_of_switches* dest,
add_switch_range(dest, end_wire, 0, 2, beg_wire, 1);
}
void add_switch_E0toB3(struct set_of_switches* dest,
static void add_switch_E0toB3(struct set_of_switches* dest,
enum wire_type end_wire, enum wire_type beg_wire)
{
const char* end_wire_s = wire_base(end_wire);
@ -787,7 +786,7 @@ void add_switch_E0toB3(struct set_of_switches* dest,
add_switch_range(dest, end_wire, 1, 3, beg_wire, 0);
}
int add_switches(struct set_of_switches* dest,
static int add_switches(struct set_of_switches* dest,
enum wire_type end_wire, enum wire_type beg_wire)
{
const char* end_wire_s, *beg_wire_s;
@ -1066,7 +1065,8 @@ xout:
return rc;
}
int add_logicio_extra(struct fpga_model* model, int y, int x, int routing_io)
static int add_logicio_extra(struct fpga_model* model,
int y, int x, int routing_io)
{
// 16 groups of 4. The order inside the group does not matter,
// but the order of the groups must match the order in src_w.
@ -1163,7 +1163,8 @@ xout:
return rc;
}
int add_logicout_switches(struct fpga_model* model, int y, int x, int routing_io)
static int add_logicout_switches(struct fpga_model* model,
int y, int x, int routing_io)
{
// 8 groups of 3. The order inside the group does not matter,
// but the order of the groups does.
@ -1355,7 +1356,7 @@ xout:
return rc;
}
int add_logicin_switches(struct fpga_model* model, int y, int x)
static int add_logicin_switches(struct fpga_model* model, int y, int x)
{
int rc;
{ static int decrement_at_NN[] =

10
sort_seq.c
View File

@ -17,7 +17,8 @@ static int s_numlines;
static char s_lines[1000][LINE_LENGTH];
// returns 0 if no number found
int find_rightmost_num(const char* s, int s_len, int* dig_start, int* dig_end)
static int find_rightmost_num(const char* s, int s_len,
int* dig_start, int* dig_end)
{
int i;
@ -105,7 +106,7 @@ static void find_number(const char* s, int s_len, int* num_start, int* num_end)
}
}
int str_cmp(const char* a, int a_len, const char* b, int b_len)
static int str_cmp(const char* a, int a_len, const char* b, int b_len)
{
int i = 0;
@ -203,7 +204,8 @@ static int is_known_suffix(const char* str, int str_len)
return 0;
}
void next_unequal_word(const char* a, int a_start, int* a_beg, int* a_end,
static void next_unequal_word(
const char* a, int a_start, int* a_beg, int* a_end,
const char* b, int b_start, int* b_beg, int* b_end)
{
*a_beg = a_start;
@ -227,7 +229,7 @@ void next_unequal_word(const char* a, int a_start, int* a_beg, int* a_end,
}
}
int sort_lines(const void* a, const void* b)
static int sort_lines(const void* a, const void* b)
{
const char* _a, *_b;
int a_word_beg, a_word_end, b_word_beg, b_word_end;