From 8ffb4e21437772ba1750f932445745fd1b54f9ec Mon Sep 17 00:00:00 2001 From: Wolfgang Spraul Date: Tue, 7 Aug 2012 15:11:19 +0200 Subject: [PATCH] finished logicin switches --- model.c | 106 +++++++++++++++++++++++++++++++++++++------------------- 1 file changed, 71 insertions(+), 35 deletions(-) diff --git a/model.c b/model.c index 903d73f..adc5e09 100644 --- a/model.c +++ b/model.c @@ -585,10 +585,6 @@ enum logic_wire { M_WE }; -// This function adds the switches for all dirwires in the -// quarter belonging to dirwire. So dirwire should only be -// one of W_NN2, W_EE2, W_SS2 or W_WW2 - the rest is handled -// inside the function. int add_logicin_switch(struct fpga_model* model, int y, int x, enum wire_type dirwire, int dirwire_num, int logicin_num) @@ -596,8 +592,6 @@ int add_logicin_switch(struct fpga_model* model, int y, int x, char from_str[16], to_str[16]; int rc; - if ((logicin_num & LWF_WIRE_MASK) == LWF_UNDEF) return 0; - if (dirwire_num == 0 && logicin_num & LWF_SOUTH0) snprintf(from_str, sizeof(from_str), "%sE_S0", wire_base(dirwire)); @@ -616,6 +610,49 @@ xout: return rc; } +// This function adds the switches for all dirwires in the +// quarter belonging to dirwire. So dirwire should only be +// one of W_NN2, W_EE2, W_SS2 or W_WW2 - the rest is handled +// inside the function. +int add_logicin_switch_quart(struct fpga_model* model, int y, int x, + enum wire_type dirwire, int dirwire_num, + int logicin_num) +{ + enum wire_type len1; + int rc; + + rc = add_logicin_switch(model, y, x, dirwire, dirwire_num, + logicin_num); + if (rc) goto xout; + len1 = W_COUNTER_CLOCKWISE(W_TO_LEN1(dirwire)); + rc = add_logicin_switch(model, y, x, len1, + dirwire_num, logicin_num); + if (rc) goto xout; + + if (dirwire == W_WW2) { + int nw_num = dirwire_num+1; + if (nw_num > 3) + nw_num = 0; + rc = add_logicin_switch(model, y, x, W_NW2, nw_num, + logicin_num); + if (rc) goto xout; + rc = add_logicin_switch(model, y, x, W_NL1, nw_num, + logicin_num); + if (rc) goto xout; + } else { + rc = add_logicin_switch(model, y, x, W_CLOCKWISE(dirwire), + dirwire_num, logicin_num); + if (rc) goto xout; + len1 = rotate_wire(len1, 3); + rc = add_logicin_switch(model, y, x, len1, + dirwire_num, logicin_num); + if (rc) goto xout; + } + return 0; +xout: + return rc; +} + static int loop_and_rotate_over_wires(struct fpga_model* model, int y, int x, int* wires, int num_wires, int early_decrement) { @@ -631,7 +668,9 @@ static int loop_and_rotate_over_wires(struct fpga_model* model, int y, int x, // for (i = 0; i < num_wires*4; i++) { - rc = add_logicin_switch(model, y, x, FIRST_LEN2+(i%4)*2, + if ((wires[i/4] & LWF_WIRE_MASK) == LWF_UNDEF) + continue; + rc = add_logicin_switch_quart(model, y, x, FIRST_LEN2+(i%4)*2, 3-((i+early_decrement)/4)%4, wires[i/4]); if (rc) goto xout; } @@ -642,52 +681,50 @@ xout: int add_logicin_switches(struct fpga_model* model, int y, int x) { - static int decrement_at_NN[] = - { M_DI, M_CI, X_CE, M_WE, + int rc; + { static int decrement_at_NN[] = + { M_DI | LWF_SOUTH0, M_CI, X_CE, M_WE, M_B1 | LWF_SOUTH0, X_A2, X_A1, M_B2, - M_C6, M_C5, M_C4, M_C3, - X_D6, X_D5, X_D4, X_D3 }; + M_C6 | LWF_SOUTH0, M_C5, M_C4, M_C3, + X_D6 | LWF_SOUTH0, X_D5, X_D4, X_D3 }; - static int decrement_at_EE[] = + rc = loop_and_rotate_over_wires(model, y, x, decrement_at_NN, + sizeof(decrement_at_NN)/sizeof(decrement_at_NN[0]), + 0 /* early_decrement */); + if (rc) goto xout; } + + { static int decrement_at_EE[] = { M_CX, X_BX, M_AX, X_DX | LWF_SOUTH0, M_D2, M_D1, X_C2, X_C1 | LWF_SOUTH0, M_A4, M_A5, M_A6, M_A3 | LWF_SOUTH0, X_B4, X_B5, X_B6, X_B3 | LWF_SOUTH0 }; - static int decrement_at_SS[] = + rc = loop_and_rotate_over_wires(model, y, x, decrement_at_EE, + sizeof(decrement_at_EE)/sizeof(decrement_at_EE[0]), + 3 /* early_decrement */); + if (rc) goto xout; } + + { static int decrement_at_SS[] = { LWF_UNDEF, M_CE, M_BI, M_AI | LWF_NORTH3, X_B2, M_A1, M_A2, X_B1 | LWF_NORTH3, X_C6, X_C5, X_C4, X_C3 | LWF_NORTH3, M_D6, M_D5, M_D4, M_D3 | LWF_NORTH3 }; - static int decrement_at_WW[] = + rc = loop_and_rotate_over_wires(model, y, x, decrement_at_SS, + sizeof(decrement_at_SS)/sizeof(decrement_at_SS[0]), + 2 /* early_decrement */); + if (rc) goto xout; } + + { static int decrement_at_WW[] = { M_DX, X_CX, M_BX, X_AX | LWF_NORTH3, M_C2, X_D1, X_D2, M_C1 | LWF_NORTH3, X_A3, X_A4, X_A5, X_A6 | LWF_NORTH3, M_B3, M_B4, M_B5, M_B6 | LWF_NORTH3 }; - int rc; - - rc = loop_and_rotate_over_wires(model, y, x, decrement_at_NN, - sizeof(decrement_at_NN)/sizeof(decrement_at_NN[0]), - 0 /* early_decrement */); - if (rc) goto xout; - - rc = loop_and_rotate_over_wires(model, y, x, decrement_at_EE, - sizeof(decrement_at_EE)/sizeof(decrement_at_EE[0]), - 3 /* early_decrement */); - if (rc) goto xout; - - rc = loop_and_rotate_over_wires(model, y, x, decrement_at_SS, - sizeof(decrement_at_SS)/sizeof(decrement_at_SS[0]), - 2 /* early_decrement */); - if (rc) goto xout; - rc = loop_and_rotate_over_wires(model, y, x, decrement_at_WW, sizeof(decrement_at_WW)/sizeof(decrement_at_WW[0]), 1 /* early_decrement */); - if (rc) goto xout; - + if (rc) goto xout; } return 0; xout: return rc; @@ -715,10 +752,10 @@ static int init_switches(struct fpga_model* model) if (y != 68 || x != 12) continue; rc = add_switch(model, y, x, "LOGICOUT0", "NN2B0", 0 /* bidir */); if (rc) goto xout; + rc = add_logicin_switches(model, y, x); if (rc) goto xout; -#if 0 wire = W_NN2; do { rc = build_dirwire_switches(&dir_EB_switches, W_TO_LEN1(wire)); @@ -750,7 +787,6 @@ static int init_switches(struct fpga_model* model) wire = W_CLOCKWISE(wire); } while (wire != W_NN2); // one full turn -#endif } } return 0;