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some work on horizontal wiring

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This commit is contained in:
Wolfgang Spraul 2012-10-29 06:44:01 +01:00
parent 2546288627
commit 97f03a312c
6 changed files with 522 additions and 403 deletions
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23
LINKS
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@ -4,6 +4,7 @@ knowledge
http://www.hottconsultants.com/techtips/pcb-stack-up-3.html
http://smithsonianchips.si.edu/ice/s4.htm
http://www.texample.net/tikz/examples/timing-diagram/
http://www.siliconpr0n.org/
software
http://en.wikipedia.org/wiki/Wikipedia:WikiProject_Electronics/Programs
@ -47,21 +48,25 @@ physical goods
Wacker (EU)
- foundry equipment
www.asml.com lithography systems
www.kns.com assembly equipment
www.asml.com lithography systems
www.kns.com assembly equipment
- materials
www.injectorall.com photoresist
www.dudadiesel.com NaOH, KOH
www.mtixtl.com individual 6'' wafers
www.sciencecompany.com ACS grade solvents
www.injectorall.com photoresist
www.dudadiesel.com NaOH, KOH
www.mtixtl.com individual 6'' wafers
www.unitednuclear.com
www.tedpella.com/gold_html/Nanotubes.htm
Carbon Nanotubes
Carbon Nanotubes
www.tubedevices.com/alek/pwl/pwl_e.htm
Private Tube Manufacture-PWL vacuum tubes
Private Tube Manufacture-PWL vacuum tubes
services
- foundry
http://cmp.imag.fr/products/ic/?p=prices
CMP
www.lfoundry.com analog and mixed signal
CMP
www.lfoundry.com analog and mixed signal
- pcb
http://www.oshpark.com used for 2 and 4-layers
http://www.pcbcart.com Chinese corp in Hangzhou

9
libs/model.h
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@ -322,7 +322,7 @@ enum fpgadev_type
DEV_BUFGMUX, DEV_BSCAN, DEV_DCM, DEV_PLL, DEV_ICAP,
DEV_POST_CRC_INTERNAL, DEV_STARTUP, DEV_SLAVE_SPI,
DEV_SUSPEND_SYNC, DEV_OCT_CALIBRATE, DEV_SPI_ACCESS,
DEV_DNA, DEV_PMV, DEV_PCILOGIC_SE };
DEV_DNA, DEV_PMV, DEV_PCILOGIC_SE, DEV_MCB };
#define FPGA_DEV_STR \
{ 0, \
"LOGIC", "TIEOFF", "MACC", "IOB", \
@ -331,7 +331,7 @@ enum fpgadev_type
"BUFGMUX", "BSCAN", "DCM", "PLL", "ICAP", \
"POST_CRC_INTERNAL", "STARTUP", "SLAVE_SPI", \
"SUSPEND_SYNC", "OCT_CALIBRATE", "SPI_ACCESS", \
"DNA", "PMV", "PCILOGIC_SE" }
"DNA", "PMV", "PCILOGIC_SE", "MCB" }
// We use two types of device indices, one is a flat index
// into the tile->devs array (dev_idx_t), the other
@ -847,10 +847,11 @@ struct w_net
// the %i in the name from 0:last_inc, for a total
// of last_inc+1 wires.
int last_inc;
struct w_point pts[40];
int num_pts;
struct w_point pt[40];
};
int add_conn_net(struct fpga_model* model, add_conn_f add_conn_func, struct w_net* net);
int add_conn_net(struct fpga_model* model, add_conn_f add_conn_func, const struct w_net *net);
int add_switch(struct fpga_model* model, int y, int x, const char* from,
const char* to, int is_bidirectional);

805
libs/model_conns.c
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File diff suppressed because it is too large Load Diff

5
libs/model_devices.c
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@ -8,6 +8,7 @@
#include <stdarg.h>
#include "model.h"
#include "control.h"
#include "parts.h"
static int add_dev(struct fpga_model* model,
int y, int x, int type, int subtype);
@ -58,6 +59,10 @@ int init_devices(struct fpga_model* model)
if ((rc = add_dev(model, y, x, DEV_SLAVE_SPI, 0))) goto fail;
if ((rc = add_dev(model, y, x, DEV_SUSPEND_SYNC, 0))) goto fail;
// MCB
if ((rc = add_dev(model, XC6_MCB_YPOS, LEFT_MCB_COL, DEV_MCB, 0))) goto fail;
if ((rc = add_dev(model, XC6_MCB_YPOS, model->x_width-RIGHT_MCB_O, DEV_MCB, 0))) goto fail;
// OCT_CALIBRATE
x = LEFT_IO_DEVS;
if ((rc = add_dev(model, TOP_IO_TILES, x, DEV_OCT_CALIBRATE, 0)))

81
libs/model_helper.c
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@ -7,6 +7,7 @@
#include <stdarg.h>
#include "model.h"
#include "parts.h"
#define NUM_PF_BUFS 16
@ -29,8 +30,10 @@ const char* wpref(struct fpga_model* model, int y, int x, const char* wire_name)
{
static char buf[8][128];
static int last_buf = 0;
char* prefix;
const char *prefix;
int i;
prefix = "";
if (is_aty(Y_CHIP_HORIZ_REGS, model, y)) {
prefix = is_atx(X_CENTER_REGS_COL, model, x+3)
? "REGC_INT_" : "REGH_";
@ -40,13 +43,54 @@ const char* wpref(struct fpga_model* model, int y, int x, const char* wire_name)
prefix = "IOI_TTERM_";
else if (is_aty(Y_INNER_BOTTOM, model, y))
prefix = "IOI_BTERM_";
else
prefix = "";
else {
if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL
|X_RIGHT_IO_DEVS_COL|X_LEFT_IO_DEVS_COL
|X_FABRIC_BRAM_VIA_COL|X_FABRIC_MACC_VIA_COL,
model, x)) {
if (has_device_type(model, y, x, DEV_LOGIC, LOGIC_M))
prefix = "CLEXM_";
else if (has_device_type(model, y, x, DEV_LOGIC, LOGIC_L))
prefix = "CLEXL_";
else if (has_device(model, y, x, DEV_ILOGIC))
prefix = "IOI_";
else if (is_atx(X_CENTER_LOGIC_COL, model, x)
&& is_aty(Y_CHIP_HORIZ_REGS, model, y+1))
prefix = "INT_INTERFACE_REGC_";
else
prefix = "INT_INTERFACE_";
}
else if (is_atx(X_CENTER_CMTPLL_COL, model, x))
prefix = "CMT_PLL_";
else if (is_atx(X_RIGHT_MCB|X_LEFT_MCB, model, x)) {
if (y == XC6_MCB_YPOS)
prefix = "MCB_";
else {
const int mui_pos[] = {41, 44, 48, 51, 54, 57, 60, 64};
for (i = 0; i < sizeof(mui_pos)/sizeof(*mui_pos); i++) {
if (y == mui_pos[i]) {
prefix = "MCB_MUI_";
break;
}
}
if (i >= sizeof(mui_pos)/sizeof(*mui_pos))
prefix = "MCB_INT_";
}
} else if (is_atx(X_INNER_RIGHT, model, x))
prefix = "RTERM_";
else if (is_atx(X_INNER_LEFT, model, x))
prefix = "LTERM_";
else if (is_atx(X_CENTER_REGS_COL, model, x))
prefix = "CLKV_";
else if (is_atx(X_FABRIC_BRAM_COL, model, x))
prefix = "BRAMSITE_";
else if (is_atx(X_FABRIC_MACC_COL, model, x))
prefix = "MACCSITE_";
}
last_buf = (last_buf+1)%8;
buf[last_buf][0] = 0;
strcpy(buf[last_buf], prefix);
strcat(buf[last_buf], wire_name);
snprintf(buf[last_buf], sizeof(*buf), "%s%s", prefix, wire_name);
return buf[last_buf];
}
@ -286,25 +330,26 @@ int add_conn_range(struct fpga_model* model, add_conn_f add_conn_func, int y1, i
return 0;
}
int add_conn_net(struct fpga_model* model, add_conn_f add_conn_func, struct w_net* net)
int add_conn_net(struct fpga_model* model, add_conn_f add_conn_func, const struct w_net *net)
{
int i, j, rc;
for (i = 0; net->pts[i].name[0] && i < sizeof(net->pts)/sizeof(net->pts[0]); i++) {
for (j = i+1; net->pts[j].name[0] && j < sizeof(net->pts)/sizeof(net->pts[0]); j++) {
if (net->num_pts < 2) FAIL(EINVAL);
for (i = 0; i < net->num_pts; i++) {
for (j = i+1; j < net->num_pts; j++) {
rc = add_conn_range(model, add_conn_func,
net->pts[i].y, net->pts[i].x,
net->pts[i].name,
net->pts[i].start_count,
net->pts[i].start_count + net->last_inc,
net->pts[j].y, net->pts[j].x,
net->pts[j].name,
net->pts[j].start_count);
if (rc) goto xout;
net->pt[i].y, net->pt[i].x,
net->pt[i].name,
net->pt[i].start_count,
net->pt[i].start_count + net->last_inc,
net->pt[j].y, net->pt[j].x,
net->pt[j].name,
net->pt[j].start_count);
if (rc) FAIL(rc);
}
}
return 0;
xout:
fail:
return rc;
}

2
libs/parts.h
View File

@ -85,6 +85,8 @@ const struct xc_info* xc_info(int idcode);
#define XC6_HCLK_BYTES 2
#define XC6_HCLK_BITS (XC6_HCLK_BYTES*8)
#define XC6_MCB_YPOS 20
#define XC6_IOB_MASK_IO 0x00FF00FFFF000000
#define XC6_IOB_MASK_IN_TYPE 0x000000000000F000
#define XC6_IOB_MASK_SLEW 0x0000000000FF0000