finished first round in tile modeling - next back to semiconductor
devices and routing
This commit is contained in:
Wolfgang Spraul
parent
f69912f094
commit
9d0a00856b
270
draw_fpga.c
270
draw_fpga.c
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@ -116,18 +116,66 @@ enum fpga_tile_type
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ROUTING_VIA_IO_DCM,
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ROUTING_VIA_CARRY,
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CORNER_TERM_L,
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CORNER_TERM_R,
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IO_TERM_L_UPPER_TOP,
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IO_TERM_L_UPPER_BOT,
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IO_TERM_L_LOWER_TOP,
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IO_TERM_L_LOWER_BOT,
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IO_TERM_R_UPPER_TOP,
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IO_TERM_R_UPPER_BOT,
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IO_TERM_R_LOWER_TOP,
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IO_TERM_R_LOWER_BOT,
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IO_TERM_L,
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IO_TERM_R,
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HCLK_TERM_L,
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HCLK_TERM_R,
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REGH_IO_TERM_L,
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REGH_IO_TERM_R,
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REG_L,
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REG_R,
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IO_PCI_L,
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IO_PCI_R,
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IO_RDY_L,
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IO_RDY_R,
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IO_L,
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IO_R,
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IO_PCI_CONN_L,
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IO_PCI_CONN_R,
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CORNER_TERM_T,
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CORNER_TERM_B,
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ROUTING_IO_L,
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HCLK_ROUTING_IO_L,
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HCLK_ROUTING_IO_R,
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REGH_ROUTING_IO_L,
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REGH_ROUTING_IO_R,
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ROUTING_IO_L_BRK,
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ROUTING_GCLK,
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REGH_IO_L,
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REGH_IO_R,
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REGH_MCB,
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HCLK_MCB,
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ROUTING_IO_VIA_L,
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ROUTING_IO_VIA_R,
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ROUTING_IO_PCI_CE_L,
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ROUTING_IO_PCI_CE_R,
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CORNER_TL,
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CORNER_BL,
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CORNER_TR_UPPER,
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CORNER_TR_LOWER,
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CORNER_BR_UPPER,
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CORNER_BR_LOWER,
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HCLK_IO_TOP_UP_L,
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HCLK_IO_TOP_UP_R,
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HCLK_IO_TOP_SPLIT_L,
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HCLK_IO_TOP_SPLIT_R,
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HCLK_IO_TOP_DN_L,
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HCLK_IO_TOP_DN_R,
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HCLK_IO_BOT_UP_L,
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HCLK_IO_BOT_UP_R,
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HCLK_IO_BOT_SPLIT_L,
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HCLK_IO_BOT_SPLIT_R,
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HCLK_IO_BOT_DN_L,
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HCLK_IO_BOT_DN_R,
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};
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const char* fpga_ttstr[] = // tile type strings
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@ -223,18 +271,66 @@ const char* fpga_ttstr[] = // tile type strings
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[ROUTING_VIA_IO_DCM] = "ROUTING_VIA_IO_DCM",
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[ROUTING_VIA_CARRY] = "ROUTING_VIA_CARRY",
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[CORNER_TERM_L] = "CORNER_TERM_L",
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[CORNER_TERM_R] = "CORNER_TERM_R",
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[IO_TERM_L_UPPER_TOP] = "IO_TERM_L_UPPER_TOP",
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[IO_TERM_L_UPPER_BOT] = "IO_TERM_L_UPPER_BOT",
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[IO_TERM_L_LOWER_TOP] = "IO_TERM_L_LOWER_TOP",
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[IO_TERM_L_LOWER_BOT] = "IO_TERM_L_LOWER_BOT",
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[IO_TERM_R_UPPER_TOP] = "IO_TERM_R_UPPER_TOP",
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[IO_TERM_R_UPPER_BOT] = "IO_TERM_R_UPPER_BOT",
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[IO_TERM_R_LOWER_TOP] = "IO_TERM_R_LOWER_TOP",
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[IO_TERM_R_LOWER_BOT] = "IO_TERM_R_LOWER_BOT",
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[IO_TERM_L] = "IO_TERM_L",
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[IO_TERM_R] = "IO_TERM_R",
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[HCLK_TERM_L] = "HCLK_TERM_L",
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[HCLK_TERM_R] = "HCLK_TERM_R",
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[REGH_IO_TERM_L] = "REGH_IO_TERM_L",
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[REGH_IO_TERM_R] = "REGH_IO_TERM_R",
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[REG_L] = "REG_L",
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[REG_R] = "REG_R",
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[IO_PCI_L] = "IO_PCI_L",
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[IO_PCI_R] = "IO_PCI_R",
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[IO_RDY_L] = "IO_RDY_L",
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[IO_RDY_R] = "IO_RDY_R",
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[IO_L] = "IO_L",
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[IO_R] = "IO_R",
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[IO_PCI_CONN_L] = "IO_PCI_CONN_L",
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[IO_PCI_CONN_R] = "IO_PCI_CONN_R",
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[CORNER_TERM_T] = "CORNER_TERM_T",
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[CORNER_TERM_B] = "CORNER_TERM_B",
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[ROUTING_IO_L] = "ROUTING_IO_L",
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[HCLK_ROUTING_IO_L] = "HCLK_ROUTING_IO_L",
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[HCLK_ROUTING_IO_R] = "HCLK_ROUTING_IO_R",
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[REGH_ROUTING_IO_L] = "REGH_ROUTING_IO_L",
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[REGH_ROUTING_IO_R] = "REGH_ROUTING_IO_R",
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[ROUTING_IO_L_BRK] = "ROUTING_IO_L_BRK",
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[ROUTING_GCLK] = "ROUTING_GCLK",
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[REGH_IO_L] = "REGH_IO_L",
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[REGH_IO_R] = "REGH_IO_R",
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[REGH_MCB] = "REGH_MCB",
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[HCLK_MCB] = "HCLK_MCB",
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[ROUTING_IO_VIA_L] = "ROUTING_IO_VIA_L",
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[ROUTING_IO_VIA_R] = "ROUTING_IO_VIA_R",
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[ROUTING_IO_PCI_CE_L] = "ROUTING_IO_PCI_CE_L",
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[ROUTING_IO_PCI_CE_R] = "ROUTING_IO_PCI_CE_R",
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[CORNER_TL] = "CORNER_TL",
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[CORNER_BL] = "CORNER_BL",
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[CORNER_TR_UPPER] = "CORNER_TR_UPPER",
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[CORNER_TR_LOWER] = "CORNER_TR_LOWER",
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[CORNER_BR_UPPER] = "CORNER_BR_UPPER",
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[CORNER_BR_LOWER] = "CORNER_BR_LOWER",
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[HCLK_IO_TOP_UP_L] = "HCLK_IO_TOP_UP_L",
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[HCLK_IO_TOP_UP_R] = "HCLK_IO_TOP_UP_R",
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[HCLK_IO_TOP_SPLIT_L] = "HCLK_IO_TOP_SPLIT_L",
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[HCLK_IO_TOP_SPLIT_R] = "HCLK_IO_TOP_SPLIT_R",
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[HCLK_IO_TOP_DN_L] = "HCLK_IO_TOP_DN_L",
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[HCLK_IO_TOP_DN_R] = "HCLK_IO_TOP_DN_R",
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[HCLK_IO_BOT_UP_L] = "HCLK_IO_BOT_UP_L",
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[HCLK_IO_BOT_UP_R] = "HCLK_IO_BOT_UP_R",
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[HCLK_IO_BOT_SPLIT_L] = "HCLK_IO_BOT_SPLIT_L",
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[HCLK_IO_BOT_SPLIT_R] = "HCLK_IO_BOT_SPLIT_R",
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[HCLK_IO_BOT_DN_L] = "HCLK_IO_BOT_DN_L",
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[HCLK_IO_BOT_DN_R] = "HCLK_IO_BOT_DN_R",
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};
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struct fpga_tile
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@ -602,8 +698,14 @@ struct fpga_model* build_model(int fpga_rows, const char* columns,
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if (k<(fpga_rows/2)) row_top_y++; // middle system tiles
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for (l = 0; l < 16; l++) {
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//
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// +0
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//
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if (left_wiring[(fpga_rows-1-k)*16+l] == 'W')
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns].type = IO_L;
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//
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// +1
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//
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if ((k == fpga_rows-1 && !l) || (!k && l==15))
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + 1].type = CORNER_TERM_L;
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else if (k == fpga_rows/2 && l == 12)
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@ -616,20 +718,182 @@ struct fpga_model* build_model(int fpga_rows, const char* columns,
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model->tiles[(row_top_y+l)*tile_columns + 1].type = IO_TERM_L_LOWER_BOT;
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else
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + 1].type = IO_TERM_L;
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//
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// +2
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//
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if (left_wiring[(fpga_rows-1-k)*16+l] == 'W') {
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if (l == 15 && k && k != fpga_rows/2)
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model->tiles[(row_top_y+l+1)*tile_columns + 2].type = ROUTING_IO_L_BRK;
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else
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + 2].type = ROUTING_IO_L;
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} else { // unwired
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if (k && k != fpga_rows/2 && l == 15)
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model->tiles[(row_top_y+l+1)*tile_columns + 2].type = ROUTING_BRK;
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else if (k == fpga_rows/2 && l == 14)
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model->tiles[(row_top_y+l+1)*tile_columns + 2].type = ROUTING_GCLK;
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else
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + 2].type = ROUTING;
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}
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//
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// +3
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//
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if (left_wiring[(fpga_rows-1-k)*16+l] == 'W') {
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + 3].type = ROUTING_IO_VIA_L;
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} else { // unwired
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if (k == fpga_rows-1 && !l) {
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model->tiles[(row_top_y+l)*tile_columns + 3].type = CORNER_TL;
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} else if (!k && l == 15) {
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model->tiles[(row_top_y+l+1)*tile_columns + 3].type = CORNER_BL;
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} else {
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if (k && k != fpga_rows/2 && l == 15)
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model->tiles[(row_top_y+l+1)*tile_columns + 3].type = ROUTING_VIA_CARRY;
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else
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + 3].type = ROUTING_VIA;
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}
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}
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}
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model->tiles[(row_top_y+8)*tile_columns + 1].type = HCLK_TERM_L;
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model->tiles[(row_top_y+8)*tile_columns + 2].type = HCLK_ROUTING_IO_L;
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if (k >= fpga_rows/2) { // top half
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if (k > (fpga_rows*3)/4)
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model->tiles[(row_top_y+8)*tile_columns + 3].type = HCLK_IO_TOP_UP_L;
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else if (k == (fpga_rows*3)/4)
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model->tiles[(row_top_y+8)*tile_columns + 3].type = HCLK_IO_TOP_SPLIT_L;
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else
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model->tiles[(row_top_y+8)*tile_columns + 3].type = HCLK_IO_TOP_DN_L;
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} else { // bottom half
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if (k < fpga_rows/4 - 1)
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model->tiles[(row_top_y+8)*tile_columns + 3].type = HCLK_IO_BOT_DN_L;
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else if (k == fpga_rows/4 - 1)
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model->tiles[(row_top_y+8)*tile_columns + 3].type = HCLK_IO_BOT_SPLIT_L;
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else
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model->tiles[(row_top_y+8)*tile_columns + 3].type = HCLK_IO_BOT_UP_L;
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}
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model->tiles[(row_top_y+8)*tile_columns + 4].type = HCLK_MCB;
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}
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model->tiles[(center_row-3)*tile_columns].type = IO_PCI_L;
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model->tiles[(center_row-2)*tile_columns].type = IO_PCI_CONN_L;
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model->tiles[(center_row-1)*tile_columns].type = IO_PCI_CONN_L;
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model->tiles[center_row*tile_columns].type = REG_L;
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model->tiles[center_row*tile_columns + 1].type = REGH_IO_TERM_L;
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model->tiles[(center_row+1)*tile_columns].type = IO_RDY_L;
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model->tiles[center_row*tile_columns + 1].type = REGH_IO_TERM_L;
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model->tiles[tile_columns + 2].type = CORNER_TERM_T;
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model->tiles[(tile_rows-2)*tile_columns + 2].type = CORNER_TERM_B;
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model->tiles[center_row*tile_columns + 2].type = REGH_ROUTING_IO_L;
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model->tiles[tile_columns + 3].type = ROUTING_IO_PCI_CE_L;
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model->tiles[(tile_rows-2)*tile_columns + 3].type = ROUTING_IO_PCI_CE_L;
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model->tiles[center_row*tile_columns + 3].type = REGH_IO_L;
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model->tiles[center_row*tile_columns + 4].type = REGH_MCB;
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//
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// right IO
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//
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for (k = fpga_rows-1; k >= 0; k--) {
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row_top_y = 2 /* top IO tiles */ + (fpga_rows-1-k)*(8+1/*middle of row clock*/+8);
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if (k<(fpga_rows/2)) row_top_y++; // middle system tiles
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for (l = 0; l < 16; l++) {
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//
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// -1
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//
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if (k == fpga_rows/2 && l == 13)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 1].type = IO_RDY_R;
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else if (k == fpga_rows/2 && l == 14)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 1].type = IO_PCI_CONN_R;
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else if (k == fpga_rows/2 && l == 15)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 1].type = IO_PCI_CONN_R;
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else if (k == fpga_rows/2-1 && !l)
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model->tiles[(row_top_y+l)*tile_columns + tile_columns - 1].type = IO_PCI_R;
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else {
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if (right_wiring[(fpga_rows-1-k)*16+l] == 'W')
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + tile_columns - 1].type = IO_R;
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}
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//
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// -2
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//
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if ((k == fpga_rows-1 && (!l || l == 1)) || (!k && (l==15 || l==14)))
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + tile_columns - 2].type = CORNER_TERM_R;
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else if (k == fpga_rows/2 && l == 12)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 2].type = IO_TERM_R_UPPER_TOP;
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else if (k == fpga_rows/2 && l == 13)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 2].type = IO_TERM_R_UPPER_BOT;
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else if (k == (fpga_rows/2)-1 && !l)
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model->tiles[(row_top_y+l)*tile_columns + tile_columns - 2].type = IO_TERM_R_LOWER_TOP;
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else if (k == (fpga_rows/2)-1 && l == 1)
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model->tiles[(row_top_y+l)*tile_columns + tile_columns - 2].type = IO_TERM_R_LOWER_BOT;
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else
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + tile_columns - 2].type = IO_TERM_R;
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//
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// -3
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//
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//
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// -4
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//
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if (right_wiring[(fpga_rows-1-k)*16+l] == 'W')
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + tile_columns - 4].type = ROUTING_IO_VIA_R;
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else {
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if (k == fpga_rows-1 && l == 0)
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model->tiles[(row_top_y+l)*tile_columns + tile_columns - 4].type = CORNER_TR_UPPER;
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else if (k == fpga_rows-1 && l == 1)
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model->tiles[(row_top_y+l)*tile_columns + tile_columns - 4].type = CORNER_TR_LOWER;
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else if (k && k != fpga_rows/2 && l == 15)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 4].type = ROUTING_VIA_CARRY;
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else if (!k && l == 14)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 4].type = CORNER_BR_UPPER;
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else if (!k && l == 15)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 4].type = CORNER_BR_LOWER;
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else
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + tile_columns - 4].type = ROUTING_VIA;
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}
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//
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// -5
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//
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if (right_wiring[(fpga_rows-1-k)*16+l] == 'W')
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + tile_columns - 5].type = IO_ROUTING;
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else {
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if (k && k != fpga_rows/2 && l == 15)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 5].type = ROUTING_BRK;
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else if (k == fpga_rows/2 && l == 14)
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model->tiles[(row_top_y+l+1)*tile_columns + tile_columns - 5].type = ROUTING_GCLK;
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else
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + tile_columns - 5].type = ROUTING;
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}
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}
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 2].type = HCLK_TERM_R;
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 3].type = HCLK_MCB;
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 5].type = HCLK_ROUTING_IO_R;
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if (k >= fpga_rows/2) { // top half
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if (k > (fpga_rows*3)/4)
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 4].type = HCLK_IO_TOP_UP_R;
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else if (k == (fpga_rows*3)/4)
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 4].type = HCLK_IO_TOP_SPLIT_R;
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else
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 4].type = HCLK_IO_TOP_DN_R;
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} else { // bottom half
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if (k < fpga_rows/4 - 1)
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 4].type = HCLK_IO_BOT_DN_R;
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else if (k == fpga_rows/4 - 1)
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 4].type = HCLK_IO_BOT_SPLIT_R;
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else
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model->tiles[(row_top_y+8)*tile_columns + tile_columns - 4].type = HCLK_IO_BOT_UP_R;
|
||||
}
|
||||
}
|
||||
model->tiles[tile_columns + tile_columns - 5].type = CORNER_TERM_T;
|
||||
model->tiles[(tile_rows-2)*tile_columns + tile_columns - 5].type = CORNER_TERM_B;
|
||||
model->tiles[tile_columns + tile_columns - 4].type = ROUTING_IO_PCI_CE_R;
|
||||
model->tiles[(tile_rows-2)*tile_columns + tile_columns - 4].type = ROUTING_IO_PCI_CE_R;
|
||||
model->tiles[center_row*tile_columns + tile_columns - 1].type = REG_R;
|
||||
model->tiles[center_row*tile_columns + tile_columns - 2].type = REGH_IO_TERM_R;
|
||||
model->tiles[center_row*tile_columns + tile_columns - 3].type = REGH_MCB;
|
||||
model->tiles[center_row*tile_columns + tile_columns - 4].type = REGH_IO_R;
|
||||
model->tiles[center_row*tile_columns + tile_columns - 5].type = REGH_ROUTING_IO_R;
|
||||
|
||||
return model;
|
||||
}
|
||||
|
||||
|
|
@ -686,13 +950,13 @@ void print_svg_tiles(struct fpga_model* model)
|
|||
strcpy(str, fpga_ttstr[model->tiles[i*model->tile_x_range+j].type]);
|
||||
new_node = xmlNewChild(xpathObj->nodesetval->nodeTab[0], 0 /* xmlNsPtr */, BAD_CAST "text", BAD_CAST str);
|
||||
xmlSetProp(new_node, BAD_CAST "x", xmlXPathCastNumberToString(130 + j*130));
|
||||
xmlSetProp(new_node, BAD_CAST "y", xmlXPathCastNumberToString(40 + i*20));
|
||||
xmlSetProp(new_node, BAD_CAST "y", xmlXPathCastNumberToString(40 + i*14));
|
||||
xmlSetProp(new_node, BAD_CAST "fpga:tile_y", BAD_CAST xmlXPathCastNumberToString(i));
|
||||
xmlSetProp(new_node, BAD_CAST "fpga:tile_x", BAD_CAST xmlXPathCastNumberToString(j));
|
||||
}
|
||||
}
|
||||
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "width", BAD_CAST xmlXPathCastNumberToString(model->tile_x_range * 130 + 65));
|
||||
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "height", BAD_CAST xmlXPathCastNumberToString(model->tile_y_range * 20 + 60));
|
||||
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "height", BAD_CAST xmlXPathCastNumberToString(model->tile_y_range * 14 + 60));
|
||||
|
||||
xmlDocFormatDump(stdout, doc, 1 /* format */);
|
||||
xmlXPathFreeObject(xpathObj);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user