diff --git a/model.c b/model.c
index 97c3bfb..22b81ff 100644
--- a/model.c
+++ b/model.c
@@ -401,6 +401,7 @@ xout:
 int run_wires(struct fpga_model* model)
 {
 	struct fpga_tile* tile, *tile_up1, *tile_up2, *tile_dn1, *tile_dn2;
+	char buf[128];
 	int x, y, i, rc;
 
 	rc = -1;
@@ -449,6 +450,27 @@ int run_wires(struct fpga_model* model)
 						if ((rc = add_conn_bi_pref(model,   y, x, pf("LOGICIN%i", south_p[i]), y+1, x, pf("LOGICIN_S%i", south_p[i])))) goto xout;
 					}
 				}
+
+				if (tile->flags & TF_BRAM_COL) {
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICIN_B%i", 0, 63, y, x+1, "INT_INTERFACE_LOGICBIN%i", 0))) goto xout;
+					if (tile[2].flags & TF_BRAM_DEVICE) {
+						for (i = 0; i < 4; i++) {
+							sprintf(buf, "BRAM_LOGICINB%%i_INT%i", 3-i);
+							if ((rc = add_conn_range(model, NOPREF_BI_F, y-(3-i), x, "LOGICIN_B%i", 0, 63, y, x+2, buf, 0))) goto xout;
+							if ((rc = add_conn_range(model, NOPREF_BI_F, y-(3-i), x+1, "INT_INTERFACE_LOGICBIN%i", 0, 63, y, x+2, buf, 0))) goto xout;
+						}
+					}
+				}
+				if (tile->flags & TF_MACC_COL) {
+					if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICIN_B%i", 0, 63, y, x+1, "INT_INTERFACE_LOGICBIN%i", 0))) goto xout;
+					if (tile[2].flags & TF_MACC_DEVICE) {
+						for (i = 0; i < 4; i++) {
+							sprintf(buf, "MACC_LOGICINB%%i_INT%i", 3-i);
+							if ((rc = add_conn_range(model, NOPREF_BI_F, y-(3-i), x, "LOGICIN_B%i", 0, 63, y, x+2, buf, 0))) goto xout;
+							if ((rc = add_conn_range(model, NOPREF_BI_F, y-(3-i), x+1, "INT_INTERFACE_LOGICBIN%i", 0, 63, y, x+2, buf, 0))) goto xout;
+						}
+					}
+				}
 			}
 
 			// NR1
@@ -711,8 +733,7 @@ int init_tiles(struct fpga_model* model)
 					if (k<(model->cfg_rows/2)) row_top_y++; // middle system tiles (center row)
 					for (l = 0; l < 16; l++) {
 						tile_i0 = &model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i];
-						tile_i0->flags |= TF_LOGIC_COL;
-						tile_i0[1].flags |= TF_LOGIC_COL;
+						tile_i0->flags |= (model->cfg_columns[j] == 'L' || model->cfg_columns[j] == 'l') ? TF_LOGIC_XL : TF_LOGIC_XM;
 					}
 					start = ((k == model->cfg_rows-1 && (model->cfg_columns[j] == 'L' || model->cfg_columns[j] == 'M')) ? 2 : 0);
 					end = ((k == 0 && (model->cfg_columns[j] == 'L' || model->cfg_columns[j] == 'M')) ? 14 : 16);
@@ -793,8 +814,10 @@ int init_tiles(struct fpga_model* model)
 						else
 							tile_i0->type = BRAM_ROUTING_BRK;
 						model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i + 1].type = ROUTING_VIA;
-						if (!(l%4))
+						if (!(l%4)) {
 							model->tiles[(row_top_y+3+(l<8?l:l+1))*tile_columns + i + 2].type = BRAM;
+							model->tiles[(row_top_y+3+(l<8?l:l+1))*tile_columns + i + 2].flags |= TF_BRAM_DEVICE;
+						}
 					}
 					model->tiles[(row_top_y+8)*tile_columns + i].type = HCLK_BRAM_ROUTING;
 					model->tiles[(row_top_y+8)*tile_columns + i + 1].type = HCLK_BRAM_ROUTING_VIA;
@@ -827,8 +850,10 @@ int init_tiles(struct fpga_model* model)
 						else
 							tile_i0->type = ROUTING_BRK;
 						tile_i0[1].type = ROUTING_VIA;
-						if (!(l%4))
+						if (!(l%4)) {
 							model->tiles[(row_top_y+3+(l<8?l:l+1))*tile_columns + i + 2].type = MACC;
+							model->tiles[(row_top_y+3+(l<8?l:l+1))*tile_columns + i + 2].flags |= TF_MACC_DEVICE;
+						}
 					}
 					model->tiles[(row_top_y+8)*tile_columns + i].type = HCLK_MACC_ROUTING;
 					model->tiles[(row_top_y+8)*tile_columns + i + 1].type = HCLK_MACC_ROUTING_VIA;
@@ -865,8 +890,7 @@ int init_tiles(struct fpga_model* model)
 
 					for (l = 0; l < 16; l++) {
 						tile_i0 = &model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i];
-						tile_i0->flags |= TF_LOGIC_COL;
-						tile_i0[1].flags |= TF_LOGIC_COL;
+						tile_i0->flags |= TF_CENTER;
 
 						if ((k < model->cfg_rows-1 || l >= 2) && (k || l<14)) {
 							if (l < 15)
@@ -959,8 +983,8 @@ int init_tiles(struct fpga_model* model)
 		row_top_y = 2 /* top IO tiles */ + (model->cfg_rows-1-k)*(8+1/*middle of row clock*/+8);
 		if (k<(model->cfg_rows/2)) row_top_y++; // middle system tiles (center row)
 		for (l = 0; l < 16; l++) {
-			model->tiles[(row_top_y+(l<8?l:l+1))*model->tile_x_range + 2].flags |= TF_VERT_ROUTING;
-			model->tiles[(row_top_y+(l<8?l:l+1))*model->tile_x_range + model->tile_x_range - 5].flags |= TF_VERT_ROUTING;
+			model->tiles[(row_top_y+(l<8?l:l+1))*model->tile_x_range + 2].flags |= TF_VERT_ROUTING | TF_LEFT_IO;
+			model->tiles[(row_top_y+(l<8?l:l+1))*model->tile_x_range + model->tile_x_range - 5].flags |= TF_VERT_ROUTING | TF_RIGHT_IO;
 		}
 	}
 
diff --git a/model.h b/model.h
index 2acc1da..2cc2e5d 100644
--- a/model.h
+++ b/model.h
@@ -122,19 +122,25 @@ enum fpga_tile_type
 
 // tile flags
 
-#define TF_TOPMOST_TILE			0x0001
-#define TF_BELOW_TOPMOST_TILE		0x0002
-#define TF_ABOVE_BOTTOMMOST_TILE	0x0004
-#define TF_BOTTOMMOST_TILE		0x0008
-#define TF_ROW_HORIZ_AXSYMM		0x0010
-#define TF_BOTTOM_OF_ROW		0x0020
-#define TF_CHIP_HORIZ_AXSYMM		0x0040
-#define TF_CHIP_HORIZ_AXSYMM_CENTER	0x0080
-#define TF_CHIP_VERT_AXSYMM		0x0100
-#define TF_VERT_ROUTING			0x0200
-#define TF_LOGIC_COL			0x0400
-#define TF_MACC_COL			0x0800
-#define TF_BRAM_COL			0x1000
+#define TF_TOPMOST_TILE			0x00000001
+#define TF_BELOW_TOPMOST_TILE		0x00000002
+#define TF_ABOVE_BOTTOMMOST_TILE	0x00000004
+#define TF_BOTTOMMOST_TILE		0x00000008
+#define TF_ROW_HORIZ_AXSYMM		0x00000010
+#define TF_BOTTOM_OF_ROW		0x00000020
+#define TF_CHIP_HORIZ_AXSYMM		0x00000040
+#define TF_CHIP_HORIZ_AXSYMM_CENTER	0x00000080
+#define TF_CHIP_VERT_AXSYMM		0x00000100
+#define TF_VERT_ROUTING			0x00000200
+#define TF_LOGIC_XL			0x00000400
+#define TF_LOGIC_XM			0x00000800
+#define TF_CENTER			0x00001000
+#define TF_LEFT_IO			0x00002000
+#define TF_RIGHT_IO			0x00004000
+#define TF_MACC_COL			0x00008000
+#define TF_BRAM_COL			0x00010000
+#define TF_BRAM_DEVICE			0x00020000
+#define TF_MACC_DEVICE			0x00040000
 
 struct fpga_tile
 {