diff --git a/README b/README
index b3ef2dd..5248ab4 100644
--- a/README
+++ b/README
@@ -1,15 +1,22 @@
+**** NOTE - JUNE 2013 ****
+ I would L O V E to do continue with fpgatools but each day is
+ short so I have to postpone fpgatools development probably
+ until 2014. Maybe I can switch directly to Artix then :-)
+ If you want to contact me please email wspraul@q-ag.de
+****
+ 
 Introduction
  fpgatools is a toolchain to program field-programmable gate arrays
  (FPGAs). The only supported chip at this time is the xc6slx9, a
- 7 USD 45nm-generation fpga with 5720 6-input LUTs, block ram and
+ 45nm-generation fpga with 5720 6-input LUTs, block ram and
  multiply-accumulate devices.
 
  *) maximize chip performance
  *) fast development cycles
- *) independent toolchain that only depends on other free software
+ *) independent toolchain that only depends on free software
  *) reconfigure on-chip
  *) include get-started tools such as jtag, debugging, parts data
-    and designs for prototyping hardware
+    and hardware designs
  *) design flow that includes asic manufacturing
  *) lightweight C implementation without GUI
  *) supported platform: Linux
@@ -63,22 +70,21 @@ Design Principles
 TODO (as of February, 2013)
 
 short-term (1 month):
-* finish dist_mem test
 * support block memory
+  -> develop structure of dev_bram16/8
+  -> write block_mem autotest
 * example: counter (including clock, jtag)
 
 mid-term (6 months):
 * example: j1 soc
-* llvm backend
+* hls: llvm backend
 * maybe fp2bit should natively write ieee1532 and separate tools convert
   from ieee1532 to .bit and other formats
 * macc
 * more cases in logic block configuration
 * autotest: fix bugs in lut_encoding, logic_cfg, routing_sw, io_sw tests
 * autotest: protect stderr of diff executable in autotest log
-* 3 Debian packages: libfpga, libfpga-doc, fpgatools
-* support chips other than xc6slx9, maybe an ftg256 or fgg484-packaged
-  xc6 or the xc7a100
+* support chips other than xc6slx9, maybe xc7a20
 * write standard design elements for libfpga-stdlib library
 * several places might benefit from a bison parser:
   - switchbox description into bit parser/generator (bit_frames.c)
diff --git a/libs/helper.c b/libs/helper.c
index c0a7d5e..4ba9044 100644
--- a/libs/helper.c
+++ b/libs/helper.c
@@ -471,7 +471,7 @@ void printf_type2(uint8_t *d, int len, int inpos, int num_entries)
 	}
 }
 
-static int ramb_words_to_bram16(uint16_t (*init_data)[64][16], uint16_t (*init_parity)[8][16], int (*ramb_words)[1024])
+static int ramb_words_to_bram16(int (*init_data)[64][16], int (*init_parity)[8][16], int (*ramb_words)[1024])
 {
 	int init_i, i, j, bits_set;
 
@@ -499,8 +499,8 @@ static int ramb_words_to_bram16(uint16_t (*init_data)[64][16], uint16_t (*init_p
 	// prepare data words for string printf
 	for (init_i = 0; init_i < 64; init_i++) {
 		for (i = 0; i < 8; i++) {
-			(*init_data)[init_i][i*2] = (*ramb_words)[init_i*8 + i];
-			(*init_data)[init_i][i*2+1] = (*ramb_words)[512 + init_i*8 + i];
+			(*init_data)[init_i][i*2] = (*ramb_words)[init_i*8 + i] & 0xFFFF;
+			(*init_data)[init_i][i*2+1] = (*ramb_words)[512 + init_i*8 + i] & 0xFFFF;
 
 			if ((*init_data)[init_i][i*2]
 			    || (*init_data)[init_i][i*2+1])
@@ -510,7 +510,7 @@ static int ramb_words_to_bram16(uint16_t (*init_data)[64][16], uint16_t (*init_p
 	return bits_set;
 }
 
-static int ramb_words_to_bram8(uint16_t (*init_data)[64][16], uint16_t (*init_parity)[8][16], int (*ramb_words)[1024])
+static int ramb_words_to_bram8(int (*init_data)[64][16], int (*init_parity)[8][16], int (*ramb_words)[1024])
 {
 	int init_i, i, j, devs_used;
 
@@ -534,7 +534,7 @@ static int ramb_words_to_bram8(uint16_t (*init_data)[64][16], uint16_t (*init_pa
 	// prepare data words (0:31 are for the first bram8 device, 32:63 for the second one)
 	for (init_i = 0; init_i < 64; init_i++) {
 		for (i = 0; i < 16; i++) {
-			(*init_data)[init_i][i] = (*ramb_words)[init_i*16 + i];
+			(*init_data)[init_i][i] = (*ramb_words)[init_i*16 + i] & 0xFFFF;
 			if ((*init_data)[init_i][i])
 				devs_used |= (init_i < 32) ? 0x01 : 0x02;
 		}
@@ -545,7 +545,7 @@ static int ramb_words_to_bram8(uint16_t (*init_data)[64][16], uint16_t (*init_pa
 void printf_ramb_data(const uint8_t *bits, int row, int bram_idx)
 {
 	int nonzero_head, nonzero_tail, ramb_words[1024];
-	uint16_t init_data[64][16], init_parity[8][16];
+	int init_data[64][16], init_parity[8][16];
 	int i, j, devs_used;
 
 	// check head and tail
diff --git a/libs/model.h b/libs/model.h
index b6c5ad8..b351ef9 100644
--- a/libs/model.h
+++ b/libs/model.h
@@ -663,9 +663,16 @@ enum {
 	BO_LAST = BO_DOPB3
 };
 
-struct fpgadev_bram
+// requirements for valid bram
+//  rstram and rst_priority must be set for A and B.
+// todo: haven't decided whether dev_bram should be one structure
+//       for 8+16 or two separate structures
+struct fpgadev_bram16
+{
+};
+
+struct fpgadev_bram8
 {
-	// rstram and rst_priority must be set for A and B.
 };
 
 //
@@ -754,7 +761,8 @@ struct fpga_device
 		struct fpgadev_bufgmux bufgmux;
 		struct fpgadev_bufio bufio;
 		struct fpgadev_bscan bscan;
-		struct fpgadev_bram bram;
+		struct fpgadev_bram16 bram16;
+		struct fpgadev_bram8 bram8;
 	} u;
 };
 
@@ -1191,3 +1199,55 @@ struct w_net
 #define ADD_PREF 1
 
 int add_conn_net(struct fpga_model* model, int add_pref, const struct w_net *net);
+
+#if 0
+bram16:
+int *data; // points to 1024 words (each 16+2=18 bits)
+int clka_inv; // DEVCFG_INV_Y, DEVCFG_INV_N
+int clkb_inv;
+int data_width_a; // 0,1,2,4,9,18,36
+int data_width_b; // 0,1,2,4,9,18,36
+int doa_reg; // BRAM_OUTREG_ON, BRAM_OUTREG_OFF
+int dob_reg;
+int ena_inv;
+int enb_inv; // BRAM_ENB_INV_Y, BRAM_ENB_INV_N
+int reg_cea_inv;
+int reg_ceb_inv;
+int rsta_inv;
+int rstb_inv;
+int wea_inv[4];
+int web_inv[4];
+int rst_type; // BRAM_RST_SYNC, BRAM_RST_ASYNC
+int write_mode_a; // BRAM_WRITE_FIRST, BRAM_READ_FIRST, BRAM_NO_CHANGE
+int write_mode_b;
+int ram_mode; // BRAM_TDP, BRAM_SDP, BRAM_SP
+int rst_priority_a; // BRAM_RST_PRIORITY_SR, BRAM_RST_PRIORITY_CE
+int rst_priority_b; // BRAM_RST_PRIORITY_SR, BRAM_RST_PRIORITY_CE
+int en_rstram_a; // DEVCFG_FALSE, DEVCFG_TRUE
+int en_rstram_b; // DEVCFG_FALSE, DEVCFG_TRUE
+
+bram8:
+int *data; // points to 512 words (each 16+2=18 bits)
+int clk_awr_inv; // DEVCFG_INV_Y, DEVCFG_INV_N
+int clk_brd_inv;
+int data_width_a; // 0,1,2,4,9,18,36
+int data_width_b; // 0,1,2,4,9,18,36
+int doa_reg; // BRAM_OUTREG_ON, BRAM_OUTREG_OFF
+int dob_reg;
+int en_awr_inv;
+int en_brd_inv; // BRAM_ENB_INV_Y, BRAM_ENB_INV_N
+int reg_cea_inv;
+int reg_ceb_reg_ce_inv;
+int rsta_inv;
+int rstb_rst_inv;
+int wea_wel_inv[2];
+int web_weu_inv[2];
+int rst_type; // BRAM_RST_SYNC, BRAM_RST_ASYNC
+int write_mode_a; // BRAM_WRITE_FIRST, BRAM_READ_FIRST, BRAM_NO_CHANGE
+int write_mode_b;
+int ram_mode; // BRAM_TDP, BRAM_SDP, BRAM_SP
+int rst_priority_a; // BRAM_RST_PRIORITY_SR, BRAM_RST_PRIORITY_CE
+int rst_priority_b; // BRAM_RST_PRIORITY_SR, BRAM_RST_PRIORITY_CE
+int en_rstram_a; // DEVCFG_FALSE, DEVCFG_TRUE
+int en_rstram_b; // DEVCFG_FALSE, DEVCFG_TRUE
+#endif