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worked on wires of all kinds

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This commit is contained in:
Wolfgang Spraul 2012-11-20 06:35:42 +01:00
parent 93e7d1a969
commit a5afb20547
7 changed files with 1654 additions and 665 deletions
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22
libs/control.c
View File

@ -227,13 +227,13 @@ int fdev_enum(struct fpga_model* model, enum fpgadev_type type, int enum_i,
int *y, int *x, int *type_idx)
{
struct fpga_tile* tile;
int i, j, type_count, rc;
int i, j, type_count;
CHECK_RC(model);
RC_CHECK(model);
switch (type) {
case DEV_BUFGMUX:
tile = YX_TILE(model, model->center_y, model->center_x);
if (!tile) FAIL(EINVAL);
if (!tile) RC_FAIL(model, EINVAL);
type_count = 0;
for (i = 0; i < tile->num_devs; i++) {
if (tile->devs[i].type != DEV_BUFGMUX)
@ -242,12 +242,12 @@ int fdev_enum(struct fpga_model* model, enum fpgadev_type type, int enum_i,
*y = model->center_y;
*x = model->center_x;
*type_idx = type_count;
return 0;
RC_RETURN(model);
}
type_count++;
}
*y = -1;
return 0;
RC_RETURN(model);
case DEV_BUFIO: {
int yx_pairs[] = {
TOP_OUTER_ROW, model->center_x-CENTER_CMTPLL_O,
@ -265,30 +265,28 @@ int fdev_enum(struct fpga_model* model, enum fpgadev_type type, int enum_i,
*y = yx_pairs[i*2];
*x = yx_pairs[i*2+1];
*type_idx = type_count;
return 0;
RC_RETURN(model);
}
type_count++;
}
}
*y = -1;
return 0;
RC_RETURN(model);
}
case DEV_PLL:
case DEV_DCM:
enum_x(model, type, enum_i, y, model->center_x
- CENTER_CMTPLL_O, type_idx);
return 0;
RC_RETURN(model);
case DEV_BSCAN:
enum_x(model, type, enum_i, y, model->x_width
- RIGHT_IO_DEVS_O, type_idx);
return 0;
RC_RETURN(model);
default: break;
}
HERE();
*y = -1;
return 0;
fail:
return rc;
RC_RETURN(model);
}
static const char* dev_str[] = FPGA_DEV_STR;

6
libs/helper.h
View File

@ -25,9 +25,13 @@
__FILE__, __LINE__)
#define FAIL(code) do { HERE(); rc = (code); goto fail; } while (0)
#define XOUT() do { HERE(); goto xout; } while (0)
#define CHECK_RC(m) do { if ((m)->rc) return (m)->rc; } while (0)
#define ASSERT(what) do { if (!(what)) FAIL(EINVAL); } while (0)
#define RC_CHECK(model) do { if ((model)->rc) RC_RETURN(model); } while (0)
#define RC_ASSERT(model, what) do { if (!(what)) RC_FAIL(model, EINVAL); } while (0)
#define RC_FAIL(model, code) do { HERE(); if (!(model)->rc) (model)->rc = (code); RC_RETURN(model); } while (0)
#define RC_RETURN(model) return (model)->rc
#define OUT_OF_U16(val) ((val) < 0 || (val) > 0xFFFF)
const char* bitstr(uint32_t value, int digits);

34
libs/model.h
View File

@ -1000,6 +1000,9 @@ enum wire_type wire_to_len(enum wire_type w, int first_len);
enum { DIR_NORTH = 0, DIR_EAST, DIR_SOUTH, DIR_WEST };
#define LOGICOUT_HIGHEST 23
#define LOGICIN_HIGHEST 62
// The extra wires must not overlap with logicin_wire or logicout_wire
// namespaces so that they can be combined with either of them.
enum extra_wires {
@ -1036,12 +1039,37 @@ enum extra_wires {
CLK_FEEDBACK,
CLK_INDIRECT,
CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7,
CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15,
CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15,
DFB0, DFB1, DFB2, DFB3, DFB4, DFB5, DFB6, DFB7,
CLKPIN0, CLKPIN1, CLKPIN2, CLKPIN3, CLKPIN4, CLKPIN5, CLKPIN6, CLKPIN7,
DQSN0, DQSN1, DQSN2, DQSN3,
DQSP0, DQSP1, DQSP2, DQSP3,
VCC_WIRE,
GND_WIRE,
GCLK0 = 200, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7,
GCLK8, GCLK9, GCLK10, GCLK11, GCLK12, GCLK13, GCLK14, GCLK15,
GCLK0, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7,
GCLK8, GCLK9, GCLK10, GCLK11, GCLK12, GCLK13, GCLK14, GCLK15,
LOGICOUT_B0, LOGICOUT_B1, LOGICOUT_B2, LOGICOUT_B3,
LOGICOUT_B4, LOGICOUT_B5, LOGICOUT_B6, LOGICOUT_B7,
LOGICOUT_B8, LOGICOUT_B9, LOGICOUT_B10, LOGICOUT_B11,
LOGICOUT_B12, LOGICOUT_B13, LOGICOUT_B14, LOGICOUT_B15,
LOGICOUT_B16, LOGICOUT_B17, LOGICOUT_B18, LOGICOUT_B19,
LOGICOUT_B20, LOGICOUT_B21, LOGICOUT_B22, LOGICOUT_B23,
LOGICIN_B0, LOGICIN_B1, LOGICIN_B2, LOGICIN_B3,
LOGICIN_B4, LOGICIN_B5, LOGICIN_B6, LOGICIN_B7,
LOGICIN_B8, LOGICIN_B9, LOGICIN_B10, LOGICIN_B11,
LOGICIN_B12, LOGICIN_B13, LOGICIN_B14, LOGICIN_B15,
LOGICIN_B16, LOGICIN_B17, LOGICIN_B18, LOGICIN_B19,
LOGICIN_B20, LOGICIN_B21, LOGICIN_B22, LOGICIN_B23,
LOGICIN_B24, LOGICIN_B25, LOGICIN_B26, LOGICIN_B27,
LOGICIN_B28, LOGICIN_B29, LOGICIN_B30, LOGICIN_B31,
LOGICIN_B32, LOGICIN_B33, LOGICIN_B34, LOGICIN_B35,
LOGICIN_B36, LOGICIN_B37, LOGICIN_B38, LOGICIN_B39,
LOGICIN_B40, LOGICIN_B41, LOGICIN_B42, LOGICIN_B43,
LOGICIN_B44, LOGICIN_B45, LOGICIN_B46, LOGICIN_B47,
LOGICIN_B48, LOGICIN_B49, LOGICIN_B50, LOGICIN_B51,
LOGICIN_B52, LOGICIN_B53, LOGICIN_B54, LOGICIN_B55,
LOGICIN_B56, LOGICIN_B57, LOGICIN_B58, LOGICIN_B59,
LOGICIN_B60, LOGICIN_B61, LOGICIN_B62,
// direction wires
DW = 500,

1685
libs/model_conns.c
View File

File diff suppressed because it is too large Load Diff

566
libs/model_helper.c
View File

@ -843,11 +843,120 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
enum { NUM_BUFS = 8, BUF_SIZE = MAX_WIRENAME_LEN };
static char buf[NUM_BUFS][BUF_SIZE];
static int last_buf = 0;
const char *wstr;
int i, wnum, wchar;
last_buf = (last_buf+1)%NUM_BUFS;
buf[last_buf][0] = 0;
if (wire >= CFB0 && wire <= CFB15) {
if (wire == CLK0 || wire == CLK1
|| wire == SR0 || wire == SR1) {
if (is_atx(X_LEFT_IO_DEVS_COL|X_FABRIC_LOGIC_COL|X_FABRIC_MACC_VIA_COL
|X_FABRIC_BRAM_VIA_COL|X_CENTER_LOGIC_COL|X_RIGHT_IO_DEVS_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"INT_INTERFACE_%s", fpga_wire2str(wire));
else if (is_atx(X_LEFT_MCB|X_RIGHT_MCB, model, x)) {
for (i = 0; i < model->xci->num_mui; i++) {
if (y == model->xci->mui_pos[i]+1) {
if (y-dest_y < 0 || y-dest_y > 1) HERE();
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"MUI_%s_INT%i", fpga_wire2str(wire), y-dest_y);
break;
}
}
if (i >= model->xci->num_mui)
strcpy(buf[last_buf], fpga_wire2str(wire));
} else if (is_atx(X_FABRIC_MACC_COL, model, x)) {
if (has_device(model, y, x, DEV_MACC)) {
if (y-dest_y < 0 || y-dest_y >= 4) HERE();
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"MACC_%s_INT%i", fpga_wire2str(wire), y-dest_y);
} else
strcpy(buf[last_buf], fpga_wire2str(wire));
} else
strcpy(buf[last_buf], fpga_wire2str(wire));
} else if (wire >= LOGICOUT_B0 && wire <= LOGICOUT_B0 + LOGICOUT_HIGHEST) {
wnum = wire - LOGICOUT_B0;
if (is_atx(X_ROUTING_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"LOGICOUT%i", wnum);
} else if (is_atx(X_LEFT_IO_DEVS_COL|X_RIGHT_IO_DEVS_COL, model, x)) {
if (is_atx(X_LEFT_MCB|X_RIGHT_MCB, model, dest_x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"INT_INTERFACE_LOGICOUT_%i", wnum);
else
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"INT_INTERFACE_LOGICOUT%i", wnum);
} else if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"INT_INTERFACE_LOGICOUT%i", wnum);
} else if (is_atx(X_FABRIC_MACC_VIA_COL|X_FABRIC_BRAM_VIA_COL, model, x)) {
if (is_atx(X_FABRIC_MACC_COL, model, dest_x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"INT_INTERFACE_LOGICOUT_%i", wnum);
else
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"INT_INTERFACE_LOGICOUT%i", wnum);
} else if (is_atx(X_LEFT_MCB|X_RIGHT_MCB, model, x)) {
for (i = 0; i < model->xci->num_mui; i++) {
if (y == model->xci->mui_pos[i]+1) {
if (y-dest_y < 0 || y-dest_y > 1) HERE();
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"MUI_LOGICOUT%i_INT%i", wnum, y-dest_y);
break;
}
}
if (i >= model->xci->num_mui)
strcpy(buf[last_buf], fpga_wire2str(wire));
} else if (is_atx(X_FABRIC_MACC_COL, model, x)) {
if (has_device(model, y, x, DEV_MACC)) {
if (y-dest_y < 0 || y-dest_y >= 4) HERE();
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"MACC_LOGICOUT%i_INT%i", wnum, y-dest_y);
} else
strcpy(buf[last_buf], fpga_wire2str(wire));
} else
strcpy(buf[last_buf], fpga_wire2str(wire));
} else if (wire >= LOGICIN_B0 && wire <= LOGICIN_B0 + LOGICIN_HIGHEST) {
wnum = wire - LOGICIN_B0;
if (is_atx(X_ROUTING_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"LOGICIN_B%i", wnum);
} else if (is_atx(X_LEFT_IO_DEVS_COL|X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL
|X_RIGHT_IO_DEVS_COL|X_FABRIC_MACC_VIA_COL
|X_FABRIC_BRAM_VIA_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"INT_INTERFACE_LOGICBIN%i", wnum);
} else if (is_atx(X_LEFT_MCB|X_RIGHT_MCB, model, x)) {
for (i = 0; i < model->xci->num_mui; i++) {
if (y == model->xci->mui_pos[i]+1) {
if (y-dest_y < 0 || y-dest_y > 1) HERE();
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"MUI_LOGICINB%i_INT%i", wnum, y-dest_y);
break;
}
}
if (i >= model->xci->num_mui)
strcpy(buf[last_buf], fpga_wire2str(wire));
} else if (is_atx(X_FABRIC_MACC_COL, model, x)) {
if (has_device(model, y, x, DEV_MACC)) {
if (y-dest_y < 0 || y-dest_y >= 4) HERE();
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"MACC_LOGICINB%i_INT%i", wnum, y-dest_y);
} else
strcpy(buf[last_buf], fpga_wire2str(wire));
} else
strcpy(buf[last_buf], fpga_wire2str(wire));
} else if ((wire >= CFB0 && wire <= CFB15)
|| (wire >= DFB0 && wire <= DFB7)) {
if (wire >= CFB0 && wire <= CFB15) {
wstr = "CFB";
wnum = wire-CFB0;
} else if (wire >= DFB0 && wire <= DFB7) {
wstr = "DFB";
wnum = wire-DFB0;
} else HERE();
if (is_aty(Y_OUTER_TOP, model, y)) {
if (is_atx(X_CENTER_CMTPLL_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
@ -855,13 +964,13 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
else HERE();
} else if (is_aty(Y_INNER_TOP, model, y)) {
if (is_atx(X_CENTER_LOGIC_COL, model, x)) {
if ((wire >= CFB0 && wire <= CFB3)
|| (wire >= CFB8 && wire <= CFB11)) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_REGT_CFB%s_%c%i",
wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M',
((wire-CFB0)%4)/2+1);
"IOI_REGT_%s%s_%c%i",
wstr,
wnum >= 8 ? "1" : "",
wnum%2 ? 'S' : 'M',
(wnum%4)/2+1);
if (is_atyx(YX_DEV_ILOGIC, model, dest_y, dest_x))
strcat(buf[last_buf], "_S");
} else HERE();
@ -875,49 +984,50 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_TTERM_%s", fpga_wire2str(wire));
else if (x == model->center_x + CENTER_X_PLUS_2) {
if ((wire >= CFB4 && wire <= CFB7)
|| (wire >= CFB12 && wire <= CFB15)) {
if (wnum%8 >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_REGT_CFB%s_%c%i",
wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M',
((wire-CFB0)%4)/2+1);
"IOI_REGT_%s%s_%c%i",
wstr,
wnum >= 8 ? "1" : "",
wnum % 2 ? 'S' : 'M',
(wnum%4)/2+1);
if (is_atyx(YX_DEV_ILOGIC, model, dest_y, dest_x))
strcat(buf[last_buf], "_S");
} else HERE();
} else HERE();
} else if (is_aty(Y_TOP_OUTER_IO, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"TIOI_%s_CFB%s_%c%s",
(wire-CFB0)%4 < 2 ? "OUTER" : "INNER",
wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M',
((wire-CFB0)%4)/2 ? "_EXT" : "");
"TIOI_%s_%s%s_%c%s",
wnum%4 < 2 ? "OUTER" : "INNER",
wstr,
wnum >= 8 ? "1" : "",
wnum % 2 ? 'S' : 'M',
(wnum%4)/2 ? "_EXT" : "");
} else if (is_aty(Y_TOP_INNER_IO, model, y)) {
if ((wire-CFB0)%4 >= 2) {
if (wnum%4 >= 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"TIOI_INNER_CFB%s_%c",
wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M');
"TIOI_INNER_%s%s_%c", wstr,
wnum >= 8 ? "1" : "",
wnum%2 ? 'S' : 'M');
} else HERE();
} else if (is_aty(Y_BOT_INNER_IO, model, y)) {
if ((wire-CFB0)%4 >= 2) {
if (wnum%4 >= 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BIOI_INNER_CFB%s_%c",
wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M');
"BIOI_INNER_%s%s_%c", wstr,
wnum >= 8 ? "1" : "",
wnum%2 ? 'S' : 'M');
} else HERE();
} else if (is_aty(Y_BOT_OUTER_IO, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BIOI_%s_CFB%s_%c%s",
(wire-CFB0)%4 < 2 ? "OUTER" : "INNER",
wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M',
((wire-CFB0)%4)/2 ? "_EXT" : "");
"BIOI_%s_%s%s_%c%s",
wnum%4 < 2 ? "OUTER" : "INNER",
wstr,
wnum >= 8 ? "1" : "",
wnum%2 ? 'S' : 'M',
(wnum%4)/2 ? "_EXT" : "");
} else if (is_aty(Y_INNER_BOTTOM, model, y)) {
if (is_atx(X_CENTER_LOGIC_COL, model, x)) {
if ((wire >= CFB4 && wire <= CFB7)
|| (wire >= CFB12 && wire <= CFB15)) {
if (wnum%8 >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BTERM_CLB_%s", fpga_wire2str(wire));
if (is_atyx(YX_DEV_ILOGIC, model, dest_y, dest_x))
@ -927,22 +1037,20 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGB_BTERM_%s", fpga_wire2str(wire));
} else if (is_atx(X_CENTER_REGS_COL, model, x)) {
if ((wire >= CFB0 && wire <= CFB3)
|| (wire >= CFB8 && wire <= CFB11)) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGV_BTERM_%s", fpga_wire2str(wire+4));
} else HERE();
} else if (x == model->center_x + CENTER_X_PLUS_1) {
if (wire >= CFB0 && wire <= CFB3)
if (wnum < 4)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_BTERM_%s", fpga_wire2str(wire+4));
else if (wire >= CFB8 && wire <= CFB11)
else if (wnum >= 8 && wnum <= 11)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_BTERM_BUFPLL_%s", fpga_wire2str(wire+4));
else HERE();
} else if (x == model->center_x + CENTER_X_PLUS_2) {
if ((wire >= CFB0 && wire <= CFB3)
|| (wire >= CFB8 && wire <= CFB11)) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BTERM_CLB_%s", fpga_wire2str(wire+4));
if (is_atyx(YX_DEV_ILOGIC, model, dest_y, dest_x))
@ -964,14 +1072,14 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGH_LTERM_%s", fpga_wire2str(wire));
} else if (y == model->center_y + CENTER_Y_PLUS_1) {
if ((wire-CFB0)%8 < 4) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_TOP_%s", fpga_wire2str(wire));
if (is_atx(X_LEFT_IO_ROUTING_COL|X_LEFT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_E");
} else HERE();
} else if (y == model->center_y + CENTER_Y_PLUS_2) {
if ((wire-CFB0)%8 < 2) {
if (wnum%8 < 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_BOT_%s", fpga_wire2str(wire));
if (is_atx(X_LEFT_IO_ROUTING_COL|X_LEFT_IO_DEVS_COL, model, dest_x))
@ -979,19 +1087,19 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_1
|| y == model->center_y - CENTER_Y_MINUS_2) {
if ((wire-CFB0)%8 >= 4)
if (wnum%8 >= 4)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_%s_EXT", fpga_wire2str(wire-4));
else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_3) {
if ((wire-CFB0)%8 >= 4) {
if (wnum%8 >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_BOT_%s", fpga_wire2str(wire-4));
if (is_atx(X_LEFT_IO_ROUTING_COL|X_LEFT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_E");
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_4) {
if ((wire-CFB0)%8 >= 4) {
if (wnum%8 >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_TOP_%s", fpga_wire2str(wire-4));
if (is_atx(X_LEFT_IO_ROUTING_COL|X_LEFT_IO_DEVS_COL, model, dest_x))
@ -1000,29 +1108,29 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
} else HERE();
} else if (is_atx(X_LEFT_IO_ROUTING_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"INT_CFB%s_%c", wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M');
"INT_%s%s_%c", wstr, wnum >= 8 ? "1" : "",
wnum%2 ? 'S' : 'M');
} else if (is_atx(X_LEFT_IO_DEVS_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"LIOI_CFB%s_%c_ILOGIC", wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M');
"LIOI_%s%s_%c_ILOGIC", wstr, wnum >= 8 ? "1" : "",
wnum%2 ? 'S' : 'M');
} else if (is_atx(X_RIGHT_IO_DEVS_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"RIOI_CFB%s_%c_ILOGIC", wire >= CFB8 ? "1" : "",
(wire-CFB0) % 2 ? 'S' : 'M');
"RIOI_%s%s_%c_ILOGIC", wstr, wnum >= 8 ? "1" : "",
wnum%2 ? 'S' : 'M');
} else if (is_atx(X_INNER_RIGHT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGH_RTERM_%s", fpga_wire2str(wire));
} else if (y == model->center_y + CENTER_Y_PLUS_1) {
if ((wire-CFB0)%8 >= 4) {
if (wnum%8 >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_TOP_%s", fpga_wire2str(wire-4));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_W");
} else HERE();
} else if (y == model->center_y + CENTER_Y_PLUS_2) {
if ((wire-CFB0)%8 >= 6) {
if (wnum%8 >= 6) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_BOT_%s", fpga_wire2str(wire-4));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
@ -1030,20 +1138,342 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_1
|| y == model->center_y - CENTER_Y_MINUS_2) {
if ((wire-CFB0)%8 < 4)
if (wnum%8 < 4)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_%s%s", fpga_wire2str(wire),
wire < CFB8 ? "_EXT" : "");
wnum < 8 ? "_EXT" : "");
else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_3) {
if ((wire-CFB0)%8 < 4) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_BOT_%s", fpga_wire2str(wire));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_W");
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_4) {
if ((wire-CFB0)%8 < 4) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_TOP_%s", fpga_wire2str(wire));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_W");
} else HERE();
} else HERE();
} else if (is_atx(X_OUTER_RIGHT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGR_%s", fpga_wire2str(wire));
else HERE();
} else HERE();
} else if (wire >= CLKPIN0 && wire <= CLKPIN7) {
wstr = "CLKPIN";
wnum = wire-CLKPIN0;
if (is_aty(Y_OUTER_TOP, model, y)) {
if (is_atx(X_CENTER_CMTPLL_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGT_%s", fpga_wire2str(wire));
else HERE();
} else if (is_aty(Y_INNER_TOP, model, y)) {
if (is_atx(X_CENTER_LOGIC_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_REGT_%s", fpga_wire2str(wire));
else if (is_atx(X_CENTER_CMTPLL_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGT_TTERM_%s", fpga_wire2str(wire));
else if (is_atx(X_CENTER_REGS_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGV_TTERM_%s", fpga_wire2str(wire));
else if (x == model->center_x + CENTER_X_PLUS_1)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_TTERM_%s", fpga_wire2str(wire));
else if (x == model->center_x + CENTER_X_PLUS_2) {
if (wnum >= 4)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_REGT_%s", fpga_wire2str(wire-4));
else
HERE();
} else HERE();
} else if (is_aty(Y_INNER_BOTTOM, model, y)) {
if (is_atx(X_CENTER_LOGIC_COL, model, x)) {
if (wnum >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BTERM_CLB_%s", fpga_wire2str(wire));
} else HERE();
} else if (is_atx(X_CENTER_CMTPLL_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGB_BTERM_%s", fpga_wire2str(wire));
} else if (is_atx(X_CENTER_REGS_COL, model, x)) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGV_BTERM_%s", fpga_wire2str(wire+4));
} else HERE();
} else if (x == model->center_x + CENTER_X_PLUS_1) {
if (wnum < 4)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_BTERM_%s", fpga_wire2str(wire+4));
else HERE();
} else if (x == model->center_x + CENTER_X_PLUS_2) {
if (wnum < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BTERM_CLB_%s", fpga_wire2str(wire+4));
} else HERE();
} else HERE();
} else if (is_aty(Y_OUTER_BOTTOM, model, y)) {
if (is_atx(X_CENTER_CMTPLL_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGB_%s", fpga_wire2str(wire));
else HERE();
} else if (is_atx(X_OUTER_LEFT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGL_%s", fpga_wire2str(wire));
else HERE();
} else if (is_atx(X_INNER_LEFT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGH_LTERM_%s", fpga_wire2str(wire));
} else if (y == model->center_y + CENTER_Y_PLUS_1) {
if (wnum < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_%s", fpga_wire2str(wire));
} else HERE();
} else if (y == model->center_y + CENTER_Y_PLUS_2) {
if (wnum < 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_%s", fpga_wire2str(wire));
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_1
|| y == model->center_y - CENTER_Y_MINUS_2) {
if (wnum >= 4)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_%s_EXT", fpga_wire2str(wire-4));
else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_3) {
if (wnum >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_%s", fpga_wire2str(wire-4));
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_4) {
if (wnum >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_%s", fpga_wire2str(wire-4));
} else HERE();
} else HERE();
} else if (is_atx(X_INNER_RIGHT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGH_RTERM_%s", fpga_wire2str(wire));
} else if (y == model->center_y + CENTER_Y_PLUS_1) {
if (wnum >= 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_%s", fpga_wire2str(wire-4));
} else HERE();
} else if (y == model->center_y + CENTER_Y_PLUS_2) {
if (wnum >= 6) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_%s", fpga_wire2str(wire-4));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_W");
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_1
|| y == model->center_y - CENTER_Y_MINUS_2) {
if (wnum < 4)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_%s%s", fpga_wire2str(wire),
wnum < 8 ? "_EXT" : "");
else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_3) {
if (wnum < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_%s", fpga_wire2str(wire));
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_4) {
if (wnum < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_%s", fpga_wire2str(wire));
} else HERE();
} else HERE();
} else if (is_atx(X_OUTER_RIGHT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGR_%s", fpga_wire2str(wire));
else HERE();
} else HERE();
} else if ((wire >= DQSN0 && wire <= DQSN3)
|| (wire >= DQSP0 && wire <= DQSP3)) {
if (wire >= DQSN0 && wire <= DQSN3) {
wchar = 'N';
wnum = wire - DQSN0;
} else if (wire >= DQSP0 && wire <= DQSP3) {
wchar = 'P';
wnum = wire - DQSP0;
} else HERE();
if (is_aty(Y_OUTER_TOP, model, y)) {
if (is_atx(X_CENTER_CMTPLL_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGT_%s", fpga_wire2str(wire));
else HERE();
} else if (is_aty(Y_INNER_TOP, model, y)) {
if (is_atx(X_CENTER_LOGIC_COL, model, x)) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_REGT_%s", fpga_wire2str(wire));
if (is_atyx(YX_DEV_ILOGIC, model, dest_y, dest_x))
strcat(buf[last_buf], "_S");
} else HERE();
} else if (is_atx(X_CENTER_CMTPLL_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGT_TTERM_%s", fpga_wire2str(wire));
else if (is_atx(X_CENTER_REGS_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGV_TTERM_%s", fpga_wire2str(wire));
else if (x == model->center_x + CENTER_X_PLUS_1)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_TTERM_%s", fpga_wire2str(wire));
else if (x == model->center_x + CENTER_X_PLUS_2) {
if (wnum%8 >= 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_REGT_%s", fpga_wire2str(wire-2));
if (is_atyx(YX_DEV_ILOGIC, model, dest_y, dest_x))
strcat(buf[last_buf], "_S");
} else HERE();
} else HERE();
} else if (is_aty(Y_TOP_OUTER_IO, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"TIOI_%s_OUT%c%s",
wnum%2 ? "INNER" : "UPPER", wchar,
wnum%2 ? "_EXT" : "");
} else if (is_aty(Y_TOP_INNER_IO, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"TIOI_INNER_OUT%c", wchar);
} else if (is_aty(Y_BOT_INNER_IO, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BIOI_INNER_OUT%c", wchar);
} else if (is_aty(Y_BOT_OUTER_IO, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BIOI_%s_OUT%c%s",
wnum%2 ? "INNER" : "OUTER", wchar,
wnum%2 ? "_EXT" : "");
} else if (is_aty(Y_INNER_BOTTOM, model, y)) {
if (is_atx(X_CENTER_LOGIC_COL, model, x)) {
if (wnum >= 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BTERM_CLB_%s", fpga_wire2str(wire));
if (is_atyx(YX_DEV_ILOGIC, model, dest_y, dest_x))
strcat(buf[last_buf], "_N");
} else HERE();
} else if (is_atx(X_CENTER_CMTPLL_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGB_BTERM_%s", fpga_wire2str(wire));
} else if (is_atx(X_CENTER_REGS_COL, model, x)) {
if (wnum < 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGV_BTERM_%s", fpga_wire2str(wire+2));
} else HERE();
} else if (x == model->center_x + CENTER_X_PLUS_1) {
if (wnum < 2)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_BTERM_%s", fpga_wire2str(wire+2));
else HERE();
} else if (x == model->center_x + CENTER_X_PLUS_2) {
if (wnum < 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"BTERM_CLB_%s", fpga_wire2str(wire+2));
if (is_atyx(YX_DEV_ILOGIC, model, dest_y, dest_x))
strcat(buf[last_buf], "_N");
} else HERE();
} else HERE();
} else if (is_aty(Y_OUTER_BOTTOM, model, y)) {
if (is_atx(X_CENTER_CMTPLL_COL, model, x))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGB_%s", fpga_wire2str(wire));
else HERE();
} else if (is_atx(X_OUTER_LEFT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y))
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGL_%s", fpga_wire2str(wire));
else HERE();
} else if (is_atx(X_INNER_LEFT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGH_LTERM_%s", fpga_wire2str(wire));
} else if (y == model->center_y + CENTER_Y_PLUS_1) {
if (wnum%8 < 4) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_TOP_%s", fpga_wire2str(wire));
if (is_atx(X_LEFT_IO_ROUTING_COL|X_LEFT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_E");
} else HERE();
} else if (y == model->center_y + CENTER_Y_PLUS_2) {
if (wnum%8 < 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_BOT_%s", fpga_wire2str(wire));
if (is_atx(X_LEFT_IO_ROUTING_COL|X_LEFT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_E");
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_1
|| y == model->center_y - CENTER_Y_MINUS_2) {
if (wnum >= 2)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_%s_EXT", fpga_wire2str(wire-2));
else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_3) {
if (wnum >= 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_BOT_%s", fpga_wire2str(wire-2));
if (is_atx(X_LEFT_IO_ROUTING_COL|X_LEFT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_E");
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_4) {
if (wnum >= 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_LTERM_TOP_%s", fpga_wire2str(wire-2));
if (is_atx(X_LEFT_IO_ROUTING_COL|X_LEFT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_E");
} else HERE();
} else HERE();
} else if (is_atx(X_LEFT_IO_ROUTING_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]), "INT_OUT%c", wchar);
} else if (is_atx(X_LEFT_IO_DEVS_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]), "LIOI_OUT%c", wchar);
} else if (is_atx(X_RIGHT_IO_DEVS_COL, model, x)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]), "RIOI_OUT%c", wchar);
} else if (is_atx(X_INNER_RIGHT, model, x)) {
if (is_aty(Y_CHIP_HORIZ_REGS, model, y)) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"REGH_RTERM_%s", fpga_wire2str(wire));
} else if (y == model->center_y + CENTER_Y_PLUS_1) {
if (wnum >= 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_TOP_%s", fpga_wire2str(wire-2));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_W");
} else HERE();
} else if (y == model->center_y + CENTER_Y_PLUS_2) {
if (wnum >= 3) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_BOT_%s", fpga_wire2str(wire-2));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_W");
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_1
|| y == model->center_y - CENTER_Y_MINUS_2) {
if (wnum < 2)
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_%s%s", fpga_wire2str(wire),
wnum < 8 ? "_EXT" : "");
else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_3) {
if (wnum < 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_BOT_%s", fpga_wire2str(wire));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
strcat(buf[last_buf], "_W");
} else HERE();
} else if (y == model->center_y - CENTER_Y_MINUS_4) {
if (wnum < 2) {
snprintf(buf[last_buf], sizeof(buf[last_buf]),
"IOI_RTERM_TOP_%s", fpga_wire2str(wire));
if (is_atx(X_RIGHT_IO_DEVS_COL, model, dest_x))
@ -1120,12 +1550,32 @@ const char* fpga_wire2str(enum extra_wires wire)
case DFB5: return "DFB5";
case DFB6: return "DFB6";
case DFB7: return "DFB7";
case CLKPIN0: return "CLKPIN0";
case CLKPIN1: return "CLKPIN1";
case CLKPIN2: return "CLKPIN2";
case CLKPIN3: return "CLKPIN3";
case CLKPIN4: return "CLKPIN4";
case CLKPIN5: return "CLKPIN5";
case CLKPIN6: return "CLKPIN6";
case CLKPIN7: return "CLKPIN7";
case DQSN0: return "DQSN0";
case DQSN1: return "DQSN1";
case DQSN2: return "DQSN2";
case DQSN3: return "DQSN3";
case DQSP0: return "DQSP0";
case DQSP1: return "DQSP1";
case DQSP2: return "DQSP2";
case DQSP3: return "DQSP3";
default: ;
}
last_buf = (last_buf+1)%NUM_BUFS;
buf[last_buf][0] = 0;
if (wire >= GCLK0 && wire <= GCLK15)
if (wire >= LOGICOUT_B0 && wire <= LOGICOUT_B0+LOGICOUT_HIGHEST)
snprintf(buf[last_buf], sizeof(buf[0]), "LOGICOUT%i", wire-LOGICOUT_B0);
else if (wire >= LOGICIN_B0 && wire <= LOGICIN_B0+LOGICIN_HIGHEST)
snprintf(buf[last_buf], sizeof(buf[0]), "LOGICIN%i", wire-LOGICIN_B0);
else if (wire >= GCLK0 && wire <= GCLK15)
snprintf(buf[last_buf], sizeof(buf[0]), "GCLK%i", wire-GCLK0);
else if (wire >= DW && wire <= DW_LAST) {
char beg_end;
@ -1235,7 +1685,7 @@ const char* fpga_wire2str(enum extra_wires wire)
else if (macc_w == MO_CARRYOUT)
snprintf(buf[last_buf], sizeof(buf[0]), "CARRYOUTF_DSP48A1_SITE");
else HERE();
} else HERE();
} else fprintf(stderr, "#E %s:%i unsupported wire %i\n", __FILE__, __LINE__, wire);
return buf[last_buf];
}

5
libs/parts.c
View File

@ -365,7 +365,10 @@ const struct xc_info* xc_info(int idcode)
[223] = { XC_T2_IOB_PAD, 74 }},
.mcb_ypos = 20,
.num_mui = 8,
.mui_pos = { 40, 43, 47, 50, 53, 56, 59, 63 }};
.mui_pos = { 40, 43, 47, 50, 53, 56, 59, 63 },
.sel_logicin = {
24, 15, 7, 42, 5, 12, 62, 16,
47, 20, 38, 23, 48, 57, 44, 4 }};
switch (idcode & IDCODE_MASK) {
case XC6SLX9: return &xc6slx9_info;
}

1
libs/parts.h
View File

@ -68,6 +68,7 @@ struct xc_info
int mcb_ypos;
int num_mui;
int mui_pos[XC_MAX_MUI_POS];
int sel_logicin[16];
};
const struct xc_info* xc_info(int idcode);