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minor model cleanup

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This commit is contained in:
Wolfgang Spraul 2012-07-21 06:04:08 +02:00
parent 970eb4eee9
commit b4ad7801b0
5 changed files with 44 additions and 21 deletions
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20
draw_svg_tiles.c
View File

@ -35,7 +35,7 @@ int main(int argc, char** argv)
xmlXPathContextPtr xpathCtx = 0;
xmlXPathObjectPtr xpathObj = 0;
xmlNodePtr new_node;
struct fpga_model* model = 0;
struct fpga_model model = {0};
char str[128];
int i, j;
@ -43,9 +43,9 @@ int main(int argc, char** argv)
// on the output for now
xmlInitParser();
model = fpga_build_model(XC6SLX9_ROWS, XC6SLX9_COLUMNS,
XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING);
if (!model) goto fail;
if (fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING))
goto fail;
doc = xmlParseDoc(empty_svg);
if (!doc) {
@ -72,9 +72,9 @@ int main(int argc, char** argv)
goto fail;
}
for (i = 0; i < model->tile_y_range; i++) {
for (j = 0; j < model->tile_x_range; j++) {
strcpy(str, fpga_tiletype_str(model->tiles[i*model->tile_x_range+j].type));
for (i = 0; i < model.tile_y_range; i++) {
for (j = 0; j < model.tile_x_range; j++) {
strcpy(str, fpga_tiletype_str(model.tiles[i*model.tile_x_range+j].type));
new_node = xmlNewChild(xpathObj->nodesetval->nodeTab[0], 0 /* xmlNsPtr */, BAD_CAST "text", BAD_CAST str);
xmlSetProp(new_node, BAD_CAST "x", xmlXPathCastNumberToString(130 + j*130));
xmlSetProp(new_node, BAD_CAST "y", xmlXPathCastNumberToString(40 + i*14));
@ -82,14 +82,15 @@ int main(int argc, char** argv)
xmlSetProp(new_node, BAD_CAST "fpga:tile_x", BAD_CAST xmlXPathCastNumberToString(j));
}
}
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "width", BAD_CAST xmlXPathCastNumberToString(model->tile_x_range * 130 + 65));
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "height", BAD_CAST xmlXPathCastNumberToString(model->tile_y_range * 14 + 60));
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "width", BAD_CAST xmlXPathCastNumberToString(model.tile_x_range * 130 + 65));
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "height", BAD_CAST xmlXPathCastNumberToString(model.tile_y_range * 14 + 60));
xmlDocFormatDump(stdout, doc, 1 /* format */);
xmlXPathFreeObject(xpathObj);
xmlXPathFreeContext(xpathCtx);
xmlFreeDoc(doc);
xmlCleanupParser();
fpga_free_model(&model);
return EXIT_SUCCESS;
fail:
@ -97,5 +98,6 @@ fail:
if (xpathCtx) xmlXPathFreeContext(xpathCtx);
if (doc) xmlFreeDoc(doc);
xmlCleanupParser();
fpga_free_model(&model);
return EXIT_FAILURE;
}

14
helper.c
View File

@ -639,3 +639,17 @@ uint64_t read_lut64(uint8_t* two_minors, int off_in_frame)
}
return lut64;
}
int get_vm_mb()
{
FILE* statusf = fopen("/proc/self/status", "r");
char line[1024];
int vm_size = 0;
while (fgets(line, sizeof(line), statusf)) {
if (sscanf(line, "VmSize: %i kB", &vm_size) == 1)
break;
}
fclose(statusf);
if (!vm_size) return 0;
return (vm_size+1023)/1024;
}

2
helper.h
View File

@ -67,3 +67,5 @@ int clb_empty(uint8_t* maj_bits, int idx);
void printf_extrabits(uint8_t* maj_bits, int start_minor, int num_minors,
int start_bit, int num_bits, int row, int major);
uint64_t read_lut64(uint8_t* two_minors, int off_in_frame);
int get_vm_mb();

20
model.c
View File

@ -162,12 +162,11 @@ static const char* fpga_ttstr[] = // tile type strings
[HCLK_IO_BOT_DN_R] = "HCLK_IO_BOT_DN_R",
};
struct fpga_model* fpga_build_model(int fpga_rows, const char* columns,
int fpga_build_model(struct fpga_model* model, int fpga_rows, const char* columns,
const char* left_wiring, const char* right_wiring)
{
int tile_rows, tile_columns, i, j, k, l, row_top_y, center_row, left_side;
int start, end;
struct fpga_model* model;
tile_rows = 1 /* middle */ + (8+1+8)*fpga_rows + 2+2 /* two extra tiles at top and bottom */;
tile_columns = 5 /* left */ + 5 /* right */;
@ -178,18 +177,12 @@ struct fpga_model* fpga_build_model(int fpga_rows, const char* columns,
else if (columns[i] == 'R')
tile_columns+=2; // 2+2 for middle IO+logic+PLL/DCM
}
model = calloc(1 /* nelem */, sizeof(struct fpga_model));
if (!model) {
fprintf(stderr, "%i: Out of memory.\n", __LINE__);
return 0;
}
model->tile_x_range = tile_columns;
model->tile_y_range = tile_rows;
model->tiles = calloc(tile_columns * tile_rows, sizeof(struct fpga_tile));
if (!model->tiles) {
fprintf(stderr, "%i: Out of memory.\n", __LINE__);
free(model);
return 0;
return -1;
}
for (i = 0; i < tile_rows * tile_columns; i++)
model->tiles[i].type = NA;
@ -627,7 +620,14 @@ struct fpga_model* fpga_build_model(int fpga_rows, const char* columns,
model->tiles[center_row*tile_columns + tile_columns - 4].type = REGH_IO_R;
model->tiles[center_row*tile_columns + tile_columns - 5].type = REGH_ROUTING_IO_R;
return model;
return 0;
}
void fpga_free_model(struct fpga_model* model)
{
if (!model) return;
free(model->tiles);
memset(model, 0, sizeof(*model));
}
const char* fpga_tiletype_str(enum fpga_tile_type type)

9
model.h
View File

@ -46,7 +46,7 @@ struct fpga_model
enum fpga_tile_type
{
NA,
NA = 0,
ROUTING, ROUTING_BRK, ROUTING_VIA,
HCLK_ROUTING_XM, HCLK_ROUTING_XL, HCLK_LOGIC_XM, HCLK_LOGIC_XL,
LOGIC_XM, LOGIC_XL,
@ -125,6 +125,9 @@ struct fpga_tile
// the first endpoint0 is at index num_endpoints, the second one
// at num_endpoints+1, and so on.
int num_endpoints0;
// If != 0, endpoint_names will have
// num_endpoints + num_endpoints0 entries.
uint16_t* endpoint_names;
// expect up to 4k connection pairs per tile
// 32bit: 31 off: not in use on: used
@ -135,8 +138,10 @@ struct fpga_tile
uint32_t* connect_pairs;
};
struct fpga_model* fpga_build_model(int fpga_rows, const char* columns,
int fpga_build_model(struct fpga_model* model,
int fpga_rows, const char* columns,
const char* left_wiring, const char* right_wiring);
void fpga_free_model(struct fpga_model* model);
const char* fpga_tiletype_str(enum fpga_tile_type type);