diff --git a/autotest.c b/autotest.c index b16d8c5..4cf29a7 100644 --- a/autotest.c +++ b/autotest.c @@ -103,6 +103,16 @@ fail: return rc; } +void printf_swchain(struct fpga_model* model, int y, int x, str16_t sw) +{ + struct sw_chain chain = + { .model = model, .y = y, .x = x, .start_switch = sw, .from_to = SW_FROM }; + while (fpga_switch_chain(&chain) != NO_CONN) { + printf("sw %s\n", fmt_swchain(model, y, x, + chain.chain, chain.chain_size)); + } +} + int main(int argc, char** argv) { struct fpga_model model; @@ -197,7 +207,26 @@ int main(int argc, char** argv) if (rc) FAIL(rc); printf("%s\n", fmt_swchain(&model, switch_to.y, switch_to.x, switch_to.chain, switch_to.chain_size)); - // next: YX_DEV_LOGIC +#if 0 +// todo: max_depth param for _chain _conns +printf("y %i x %i %s\n", switch_to.dest_y, switch_to.dest_x, strarray_lookup(&model.str, switch_to.dest_connpt)); + printf_swconns(&model, switch_to.dest_y, switch_to.dest_x, switch_to.dest_connpt); +#endif + + switch_to.yx_req = YX_DEV_LOGIC; + switch_to.flags = SWTO_YX_DEF; + switch_to.y = switch_to.dest_y; + switch_to.x = switch_to.dest_x; + switch_to.start_switch = switch_to.dest_connpt; + rc = fpga_switch_to_yx(&switch_to); + if (rc) FAIL(rc); + printf("%s\n", fmt_swchain(&model, switch_to.y, switch_to.x, switch_to.chain, switch_to.chain_size)); + +printf("1\n"); +printf("y %i x %i %s\n", switch_to.dest_y, switch_to.dest_x, strarray_lookup(&model.str, switch_to.dest_connpt)); +printf("2\n"); + printf_swchain(&model, switch_to.dest_y, switch_to.dest_x, switch_to.dest_connpt); +printf("3\n"); printf("P48 O pinw %s\n", strarray_lookup(&model.str, P48_dev->iob.pinw_in_O)); diff --git a/bit_frames.c b/bit_frames.c index b2ef864..4bed89a 100644 --- a/bit_frames.c +++ b/bit_frames.c @@ -129,7 +129,7 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits) // logic for (x = LEFT_SIDE_WIDTH; x < model->x_width-RIGHT_SIDE_WIDTH; x++) { - if (!is_atx(X_LOGIC_COL, model, x)) + if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)) continue; for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) { if (!has_device_type(model, y, x, DEV_LOGIC, LOGIC_M)) diff --git a/control.h b/control.h index 8e15ef6..3d082d3 100644 --- a/control.h +++ b/control.h @@ -41,7 +41,7 @@ void fpga_conn_dest(struct fpga_model* model, int y, int x, int connpt_dest_idx, int* dest_y, int* dest_x, str16_t* str_i); typedef int swidx_t; // swidx_t is an index into the uint32_t switches array -#define MAX_SW_CHAIN_SIZE 32 // largest seen so far was 10 +#define MAX_SW_CHAIN_SIZE 64 // largest seen so far was 20 // returns a switch index, or -1 (NO_SWITCH) if no switch was found swidx_t fpga_switch_first(struct fpga_model* model, int y, int x, diff --git a/floorplan.c b/floorplan.c index 7a0ab0c..ae59c0c 100644 --- a/floorplan.c +++ b/floorplan.c @@ -37,7 +37,8 @@ int printf_tiles(FILE* f, struct fpga_model* model) fprintf(f, "tile y%02i x%02i flags", y, x); PRINT_FLAG(f, TF_FABRIC_ROUTING_COL); - PRINT_FLAG(f, TF_FABRIC_LOGIC_COL); + PRINT_FLAG(f, TF_FABRIC_LOGIC_XM_COL); + PRINT_FLAG(f, TF_FABRIC_LOGIC_XL_COL); PRINT_FLAG(f, TF_FABRIC_BRAM_VIA_COL); PRINT_FLAG(f, TF_FABRIC_MACC_VIA_COL); PRINT_FLAG(f, TF_FABRIC_BRAM_COL); diff --git a/model.h b/model.h index 6c97d96..70d6369 100644 --- a/model.h +++ b/model.h @@ -185,25 +185,26 @@ enum fpga_tile_type // tile flags #define TF_FABRIC_ROUTING_COL 0x00000001 // only set in y==0, not for left and right IO routing or center -#define TF_FABRIC_LOGIC_COL 0x00000002 // only set in y==0 -#define TF_FABRIC_BRAM_VIA_COL 0x00000004 // only set in y==0 -#define TF_FABRIC_MACC_VIA_COL 0x00000008 // only set in y==0 -#define TF_FABRIC_BRAM_COL 0x00000010 // only set in y==0 -#define TF_FABRIC_MACC_COL 0x00000020 // only set in y==0 +#define TF_FABRIC_LOGIC_XM_COL 0x00000002 // only set in y==0 +#define TF_FABRIC_LOGIC_XL_COL 0x00000004 // only set in y==0 +#define TF_FABRIC_BRAM_VIA_COL 0x00000008 // only set in y==0 +#define TF_FABRIC_MACC_VIA_COL 0x00000010 // only set in y==0 +#define TF_FABRIC_BRAM_COL 0x00000020 // only set in y==0 +#define TF_FABRIC_MACC_COL 0x00000040 // only set in y==0 // TF_ROUTING_NO_IO is only set in y==0 - automatically for BRAM and MACC // routing, and manually for logic routing with the noio flag in the column // configuration string -#define TF_ROUTING_NO_IO 0x00000040 -#define TF_BRAM_DEV 0x00000080 -#define TF_MACC_DEV 0x00000100 -#define TF_LOGIC_XL_DEV 0x00000200 -#define TF_LOGIC_XM_DEV 0x00000400 -#define TF_IOLOGIC_DELAY_DEV 0x00000800 -#define TF_DCM_DEV 0x00001000 -#define TF_PLL_DEV 0x00002000 +#define TF_ROUTING_NO_IO 0x00000080 +#define TF_BRAM_DEV 0x00000100 +#define TF_MACC_DEV 0x00000200 +#define TF_LOGIC_XL_DEV 0x00000400 +#define TF_LOGIC_XM_DEV 0x00000800 +#define TF_IOLOGIC_DELAY_DEV 0x00001000 +#define TF_DCM_DEV 0x00002000 +#define TF_PLL_DEV 0x00004000 // TF_WIRED is only set for x==0 on the left side or x==x_width-1 // on the right side. -#define TF_WIRED 0x00004000 +#define TF_WIRED 0x00008000 #define Y_INNER_TOP 0x0001 #define Y_INNER_BOTTOM 0x0002 @@ -223,40 +224,45 @@ enum fpga_tile_type // multiple checks are combined with OR logic int is_aty(int check, struct fpga_model* model, int y); +#define X_FABRIC_LOGIC_COL (X_FABRIC_LOGIC_XM_COL \ + |X_FABRIC_LOGIC_XL_COL) +#define X_FABRIC_LOGIC_ROUTING_COL (X_FABRIC_LOGIC_XM_ROUTING_COL \ + |X_FABRIC_LOGIC_XL_ROUTING_COL) +#define X_FABRIC_ROUTING_COL (X_FABRIC_LOGIC_XM_ROUTING_COL \ + |X_FABRIC_LOGIC_XL_ROUTING_COL \ + |X_FABRIC_BRAM_ROUTING_COL \ + |X_FABRIC_MACC_ROUTING_COL) +#define X_ROUTING_COL (X_FABRIC_ROUTING_COL \ + |X_CENTER_ROUTING_COL \ + |X_LEFT_IO_ROUTING_COL \ + |X_RIGHT_IO_ROUTING_COL) + #define X_OUTER_LEFT 0x00000001 #define X_INNER_LEFT 0x00000002 #define X_INNER_RIGHT 0x00000004 #define X_OUTER_RIGHT 0x00000008 -#define X_ROUTING_COL 0x00000010 // includes routing col in left and right IO and center -#define X_ROUTING_TO_BRAM_COL 0x00000020 -#define X_ROUTING_TO_MACC_COL 0x00000040 -#define X_ROUTING_NO_IO 0x00000080 -#define X_ROUTING_HAS_IO 0x00000100 -#define X_LOGIC_COL 0x00000200 // includes the center logic col -// todo: maybe X_FABRIC_ROUTING_COL could be logic+bram+macc? -#define X_FABRIC_ROUTING_COL 0x00000400 // logic+BRAM+MACC -#define X_FABRIC_LOGIC_ROUTING_COL 0x00000800 // logic only -#define X_FABRIC_LOGIC_COL 0x00001000 -// X_FABRIC_LOGIC_IO_COL is like X_FABRIC_LOGIC_COL but -// excluding those that have the no-io flag set. -#define X_FABRIC_LOGIC_IO_COL 0x00002000 -#define X_FABRIC_BRAM_ROUTING_COL 0x00004000 // BRAM only -#define X_FABRIC_MACC_ROUTING_COL 0x00008000 // MACC only -#define X_FABRIC_BRAM_VIA_COL 0x00010000 // second routing col for BRAM -#define X_FABRIC_MACC_VIA_COL 0x00020000 // second routing col for MACC -#define X_FABRIC_BRAM_COL 0x00040000 -#define X_FABRIC_MACC_COL 0x00080000 -#define X_CENTER_ROUTING_COL 0x00100000 -#define X_CENTER_LOGIC_COL 0x00200000 -#define X_CENTER_CMTPLL_COL 0x00400000 -#define X_CENTER_REGS_COL 0x00800000 -#define X_LEFT_IO_ROUTING_COL 0x01000000 -#define X_LEFT_IO_DEVS_COL 0x02000000 -#define X_RIGHT_IO_ROUTING_COL 0x04000000 -#define X_RIGHT_IO_DEVS_COL 0x08000000 -#define X_LEFT_SIDE 0x10000000 // true for anything left of the center (not including center) -#define X_LEFT_MCB 0x20000000 -#define X_RIGHT_MCB 0x40000000 +#define X_ROUTING_NO_IO 0x00000010 +#define X_FABRIC_LOGIC_XM_ROUTING_COL 0x00000020 // logic-xm only +#define X_FABRIC_LOGIC_XL_ROUTING_COL 0x00000040 // logic-xl only +#define X_FABRIC_LOGIC_XM_COL 0x00000080 +#define X_FABRIC_LOGIC_XL_COL 0x00000100 +#define X_FABRIC_BRAM_ROUTING_COL 0x00000200 // BRAM only +#define X_FABRIC_MACC_ROUTING_COL 0x00000400 // MACC only +#define X_FABRIC_BRAM_VIA_COL 0x00000800 // second routing col for BRAM +#define X_FABRIC_MACC_VIA_COL 0x00001000 // second routing col for MACC +#define X_FABRIC_BRAM_COL 0x00002000 +#define X_FABRIC_MACC_COL 0x00004000 +#define X_CENTER_ROUTING_COL 0x00008000 +#define X_CENTER_LOGIC_COL 0x00010000 +#define X_CENTER_CMTPLL_COL 0x00020000 +#define X_CENTER_REGS_COL 0x00040000 +#define X_LEFT_IO_ROUTING_COL 0x00080000 +#define X_LEFT_IO_DEVS_COL 0x00100000 +#define X_RIGHT_IO_ROUTING_COL 0x00200000 +#define X_RIGHT_IO_DEVS_COL 0x00400000 +#define X_LEFT_SIDE 0x00800000 // true for anything left of the center (not including center) +#define X_LEFT_MCB 0x01000000 +#define X_RIGHT_MCB 0x02000000 #define IS_TOP_ROW(row, model) ((row) == (model)->cfg_rows-1) #define IS_BOTTOM_ROW(row, model) ((row) == 0) @@ -334,6 +340,32 @@ enum { LOGIC_M = 1, LOGIC_L, LOGIC_X }; struct fpgadev_logic { +// M_A1..A6, M_AX +// X_A1 or XX_A1 for L + // for X, L and M: + str16_t pinw_in_A1, pinw_in_A2, pinw_in_A3, pinw_in_A4, pinw_in_A5, + pinw_in_A6, pinw_in_AX; + str16_t pinw_in_B1, pinw_in_B2, pinw_in_B3, pinw_in_B4, pinw_in_B5, + pinw_in_B6, pinw_in_BX; + str16_t pinw_in_C1, pinw_in_C2, pinw_in_C3, pinw_in_C4, pinw_in_C5, + pinw_in_C6, pinw_in_CX; + str16_t pinw_in_D1, pinw_in_D2, pinw_in_D3, pinw_in_D4, pinw_in_D5, + pinw_in_D6, pinw_in_DX; +// M_CLK, M_CE, M_SR + str16_t pinw_in_CLK, pinw_in_CE, pinw_in_SR; +// M_A, M_AMUX, M_AQ + str16_t pinw_out_A, pinw_out_AMUX, pinw_out_AQ; + str16_t pinw_out_B, pinw_out_BMUX, pinw_out_BQ; + str16_t pinw_out_C, pinw_out_CMUX, pinw_out_CQ; + str16_t pinw_out_D, pinw_out_DMUX, pinw_out_DQ; + // only for L and M: +// M_CIN, M_COUT +// L_CIN, XL_COUT + str16_t pinw_in_CIN, pinw_out_COUT; + // only for M: +// M_WE, M_AI-DI + str16_t pinw_in_WE, pinw_in_AI, pinw_in_BI, pinw_in_CI, pinw_in_DI; + int subtype; // LOGIC_M, LOGIC_L or LOGIC_X int A_used, B_used, C_used, D_used; char* A6_lut, *B6_lut, *C6_lut, *D6_lut; diff --git a/model_conns.c b/model_conns.c index 329afe2..bce9fa4 100644 --- a/model_conns.c +++ b/model_conns.c @@ -59,7 +59,7 @@ static int connect_logic_carry(struct fpga_model* model) int x, y, rc; for (x = 0; x < model->x_width; x++) { - if (is_atx(X_LOGIC_COL, model, x)) { + if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)) { for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) { if (has_device_type(model, y, x, DEV_LOGIC, LOGIC_M)) { if (is_aty(Y_CHIP_HORIZ_REGS, model, y-1) @@ -235,7 +235,7 @@ static int run_gfan(struct fpga_model* model) // top and bottom IO devs for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) { if (is_atx(X_FABRIC_LOGIC_ROUTING_COL|X_CENTER_ROUTING_COL, model, x) - && is_atx(X_ROUTING_HAS_IO, model, x)) { + && !is_atx(X_ROUTING_NO_IO, model, x)) { for (i = 0; i < TOPBOT_IO_ROWS; i++) { if ((rc = add_conn_range(model, NOPREF_BI_F, TOP_OUTER_IO+i, x, @@ -871,7 +871,7 @@ static int run_gclk(struct fpga_model* model) gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_INT"; } else if (is_atx(X_LEFT_MCB, model, x)) { gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_MCB"; - } else if (is_atx(X_LOGIC_COL|X_LEFT_IO_DEVS_COL, model, x)) { + } else if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL|X_LEFT_IO_DEVS_COL, model, x)) { gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_CLB"; } else if (is_atx(X_FABRIC_BRAM_VIA_COL|X_FABRIC_MACC_VIA_COL, model, x)) { gclk_net.pts[next_net_o++].name = "HCLK_GCLK%i_BRAM_INTER"; @@ -923,7 +923,7 @@ static int run_gclk(struct fpga_model* model) } else { if (row) is_break = 1; - else if (is_atx(X_ROUTING_TO_BRAM_COL|X_ROUTING_TO_MACC_COL, model, x)) + else if (is_atx(X_FABRIC_BRAM_ROUTING_COL|X_FABRIC_MACC_ROUTING_COL, model, x)) is_break = 1; } @@ -1625,7 +1625,7 @@ static int run_logic_inout(struct fpga_model* model) if ((rc = add_conn_bi_pref(model, y, x, pf("LOGICIN%i", north_p[i]), y-2, x, pf("LOGICIN_N%i", north_p[i])))) goto xout; if ((rc = add_conn_bi_pref(model, y-1, x, pf("LOGICIN_N%i", north_p[i]), y-2, x, pf("LOGICIN_N%i", north_p[i])))) goto xout; } - if (is_aty(Y_INNER_BOTTOM, model, y+1) && !is_atx(X_ROUTING_TO_BRAM_COL, model, x)) { + if (is_aty(Y_INNER_BOTTOM, model, y+1) && !is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) { if ((rc = add_conn_bi_pref(model, y, x, pf("LOGICIN_N%i", north_p[i]), y+1, x, pf("LOGICIN_N%i", north_p[i])))) goto xout; } } @@ -1638,7 +1638,7 @@ static int run_logic_inout(struct fpga_model* model) if ((rc = add_conn_bi_pref(model, y, x, pf("LOGICIN%i", south_p[i]), y+2, x, pf("LOGICIN_S%i", south_p[i])))) goto xout; if ((rc = add_conn_bi_pref(model, y+1, x, pf("LOGICIN%i", south_p[i]), y+2, x, pf("LOGICIN_S%i", south_p[i])))) goto xout; } else if (is_aty(Y_INNER_BOTTOM, model, y+1)) { - if (!is_atx(X_ROUTING_TO_BRAM_COL, model, x)) + if (!is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) if ((rc = add_conn_bi_pref(model, y, x, pf("LOGICIN%i", south_p[i]), y+1, x, pf("LOGICIN%i", south_p[i])))) goto xout; } else { if ((rc = add_conn_bi_pref(model, y, x, pf("LOGICIN%i", south_p[i]), y+1, x, pf("LOGICIN_S%i", south_p[i])))) goto xout; @@ -1659,7 +1659,7 @@ static int run_logic_inout(struct fpga_model* model) if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICIN_B%i", 5, 9, y, x+1, "IOI_LOGICINB%i", 5))) goto xout; if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICIN_B%i", 11, 62, y, x+1, "IOI_LOGICINB%i", 11))) goto xout; } - if (is_atx(X_ROUTING_TO_BRAM_COL, model, x)) { + if (is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) { if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICIN_B%i", 0, 62, y, x+1, "INT_INTERFACE_LOGICBIN%i", 0))) goto xout; if (tile[2].flags & TF_BRAM_DEV) { for (i = 0; i < 4; i++) { @@ -1669,7 +1669,7 @@ static int run_logic_inout(struct fpga_model* model) } } } - if (is_atx(X_ROUTING_TO_MACC_COL, model, x)) { + if (is_atx(X_FABRIC_MACC_ROUTING_COL, model, x)) { if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICIN_B%i", 0, 62, y, x+1, "INT_INTERFACE_LOGICBIN%i", 0))) goto xout; if (tile[2].flags & TF_MACC_DEV) { for (i = 0; i < 4; i++) { @@ -1903,7 +1903,7 @@ static int run_direction_wires(struct fpga_model* model) { "NR1E%i", 0, y-1, x }, { "" }}}; if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; } - if (is_aty(Y_INNER_BOTTOM, model, y+1) && !is_atx(X_ROUTING_TO_BRAM_COL, model, x)) { + if (is_aty(Y_INNER_BOTTOM, model, y+1) && !is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) { { struct w_net n = { 3, {{ "NR1E%i", 0, y, x }, @@ -1977,7 +1977,7 @@ static int run_direction_wires(struct fpga_model* model) if ((rc = add_conn_bi(model, y-2, x, "NN2E0", y-1, x, "NN2E_S0"))) goto xout; if (is_aty(Y_INNER_BOTTOM, model, y+1)) { if ((rc = add_conn_bi(model, y, x, "NN2E_S0", y-1, x, "NN2E0"))) goto xout; - if (!is_atx(X_ROUTING_TO_BRAM_COL, model, x)) { + if (!is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) { { struct w_net n = { 3, {{ "NN2E%i", 0, y-1, x }, @@ -2026,7 +2026,7 @@ static int run_direction_wires(struct fpga_model* model) if ((rc = add_conn_bi_pref(model, y, x, "SS2B3", y+2, x, "SS2E_N3"))) goto xout; if ((rc = add_conn_bi_pref(model, y+2, x, "SS2E_N3", y+3, x, "SS2E3"))) goto xout; } else if (is_aty(Y_INNER_BOTTOM, model, y+2)) { - if (!is_atx(X_ROUTING_TO_BRAM_COL, model, x)) { + if (!is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) { { struct w_net n = { 3, {{ "SS2B%i", 0, y, x }, @@ -2036,7 +2036,7 @@ static int run_direction_wires(struct fpga_model* model) if ((rc = add_conn_net(model, PREF_BI_F, &n))) goto xout; } } } else if (is_aty(Y_INNER_BOTTOM, model, y+1)) { - if (!is_atx(X_ROUTING_TO_BRAM_COL, model, x)) { + if (!is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) { if ((rc = add_conn_range(model, PREF_BI_F, y, x, "SS2B%i", 0, 3, y+1, x, "SS2B%i", 0))) goto xout; if ((rc = add_conn_bi_pref(model, y, x, "SS2E_N3", y+1, x, "SS2E_N3"))) goto xout; } diff --git a/model_devices.c b/model_devices.c index 3779b53..b66053b 100644 --- a/model_devices.c +++ b/model_devices.c @@ -265,7 +265,7 @@ int init_devices(struct fpga_model* model) // ILOGIC/OLOGIC/IODELAY for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) { - if (!is_atx(X_LOGIC_COL, model, x) + if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x) || is_atx(X_ROUTING_NO_IO, model, x-1)) continue; for (i = 0; i <= 1; i++) { @@ -394,7 +394,7 @@ int init_devices(struct fpga_model* model) if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail; } } - if (is_atx(X_LOGIC_COL, model, x) + if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x) && !is_atx(X_ROUTING_NO_IO, model, x-1)) { for (i = 0; i <= 1; i++) { y = TOP_IO_TILES+i; @@ -406,7 +406,7 @@ int init_devices(struct fpga_model* model) } // LOGIC for (x = 0; x < model->x_width; x++) { - if (!is_atx(X_LOGIC_COL, model, x)) + if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)) continue; for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) { // M and L are at index 0 (DEV_LOGM and DEV_LOGL), X is at index 1 (DEV_LOGX). diff --git a/model_helper.c b/model_helper.c index 934fb97..526619e 100644 --- a/model_helper.c +++ b/model_helper.c @@ -535,30 +535,18 @@ int is_atx(int check, struct fpga_model* model, int x) if (check & X_INNER_LEFT && x == 1) return 1; if (check & X_INNER_RIGHT && x == model->x_width-2) return 1; if (check & X_OUTER_RIGHT && x == model->x_width-1) return 1; - if (check & X_ROUTING_COL - && (model->tiles[x].flags & TF_FABRIC_ROUTING_COL - || x == LEFT_IO_ROUTING || x == model->x_width-5 - || x == model->center_x-3)) return 1; - if (model->tiles[x].flags & TF_FABRIC_ROUTING_COL) { - if (check & X_ROUTING_TO_BRAM_COL - && model->tiles[x+1].flags & TF_FABRIC_BRAM_VIA_COL - && model->tiles[x+2].flags & TF_FABRIC_BRAM_COL) return 1; - if (check & X_ROUTING_TO_MACC_COL - && model->tiles[x+1].flags & TF_FABRIC_MACC_VIA_COL - && model->tiles[x+2].flags & TF_FABRIC_MACC_COL) return 1; - } - if (check & X_ROUTING_NO_IO && model->tiles[x].flags & TF_ROUTING_NO_IO) return 1; - if (check & X_ROUTING_HAS_IO && !(model->tiles[x].flags & TF_ROUTING_NO_IO)) return 1; - if (check & X_LOGIC_COL - && (model->tiles[x].flags & TF_FABRIC_LOGIC_COL - || x == model->center_x-2)) return 1; - if (check & X_FABRIC_ROUTING_COL && model->tiles[x].flags & TF_FABRIC_ROUTING_COL) return 1; - // todo: the routing/no_io flags could be cleaned up - if (check & X_FABRIC_LOGIC_ROUTING_COL + if (check & X_ROUTING_NO_IO + && model->tiles[x].flags & TF_ROUTING_NO_IO) return 1; + if (check & X_FABRIC_LOGIC_XM_ROUTING_COL && model->tiles[x].flags & TF_FABRIC_ROUTING_COL - && model->tiles[x+1].flags & TF_FABRIC_LOGIC_COL) return 1; - if (check & X_FABRIC_LOGIC_COL && model->tiles[x].flags & TF_FABRIC_LOGIC_COL) return 1; - if (check & X_FABRIC_LOGIC_IO_COL && model->tiles[x].flags & TF_FABRIC_LOGIC_COL && !(model->tiles[x-1].flags & TF_ROUTING_NO_IO)) return 1; + && model->tiles[x+1].flags & TF_FABRIC_LOGIC_XM_COL) return 1; + if (check & X_FABRIC_LOGIC_XL_ROUTING_COL + && model->tiles[x].flags & TF_FABRIC_ROUTING_COL + && model->tiles[x+1].flags & TF_FABRIC_LOGIC_XL_COL) return 1; + if (check & X_FABRIC_LOGIC_XM_COL + && model->tiles[x].flags & TF_FABRIC_LOGIC_XM_COL) return 1; + if (check & X_FABRIC_LOGIC_XL_COL + && model->tiles[x].flags & TF_FABRIC_LOGIC_XL_COL) return 1; if (check & X_FABRIC_BRAM_ROUTING_COL && model->tiles[x].flags & TF_FABRIC_ROUTING_COL && model->tiles[x+1].flags & TF_FABRIC_BRAM_VIA_COL diff --git a/model_ports.c b/model_ports.c index c0aac62..def212d 100644 --- a/model_ports.c +++ b/model_ports.c @@ -395,7 +395,7 @@ int init_ports(struct fpga_model* model, int dup_warn) } } } - if (is_atx(X_LOGIC_COL, model, x)) { + if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)) { for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) { if (YX_TILE(model, y, x)->flags & (TF_LOGIC_XM_DEV|TF_LOGIC_XL_DEV)) { const char* pref[2]; diff --git a/model_switches.c b/model_switches.c index 72c95c6..998ca75 100644 --- a/model_switches.c +++ b/model_switches.c @@ -136,7 +136,7 @@ static int init_logic_switches(struct fpga_model* model) int x, y, rc; for (x = LEFT_SIDE_WIDTH; x < model->x_width-RIGHT_SIDE_WIDTH; x++) { - if (!is_atx(X_LOGIC_COL, model, x)) + if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)) continue; for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) { if (has_device(model, y, x, DEV_LOGIC)) { @@ -603,7 +603,7 @@ static int init_north_south_dirwire_term(struct fpga_model* model) "IOI_TTERM_", dir, /*inc*/ 3))) goto xout; } // bottom - if (is_atx(X_ROUTING_TO_BRAM_COL, model, x)) + if (is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) continue; for (i = 0; i < 4; i++) { rc = add_switch(model, @@ -704,7 +704,8 @@ static int init_ce_clk_switches(struct fpga_model* model) } } for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) { - if ((is_atx(X_FABRIC_LOGIC_IO_COL|X_CENTER_LOGIC_COL, model, x))) { + if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x) + && !is_atx(X_ROUTING_NO_IO, model, x-1)) { // top for (i = 0; i <= 3; i++) { rc = add_switch(model, TOP_INNER_ROW, x, diff --git a/model_tiles.c b/model_tiles.c index f46c434..3417584 100644 --- a/model_tiles.c +++ b/model_tiles.c @@ -66,7 +66,10 @@ int init_tiles(struct fpga_model* model) model->tiles[i].flags |= TF_FABRIC_ROUTING_COL; if (no_io) model->tiles[i].flags |= TF_ROUTING_NO_IO; - model->tiles[i+1].flags |= TF_FABRIC_LOGIC_COL; + model->tiles[i+1].flags |= + (cur_cfgcol == 'L' || cur_cfgcol == 'l') + ? TF_FABRIC_LOGIC_XL_COL + : TF_FABRIC_LOGIC_XM_COL; for (k = model->cfg_rows-1; k >= 0; k--) { row_top_y = 2 /* top IO tiles */ + (model->cfg_rows-1-k)*(8+1/*middle of row clock*/+8); if (k<(model->cfg_rows/2)) row_top_y++; // middle system tiles (center row)