blinking_led fix
This commit is contained in:
Wolfgang Spraul
parent
e919fb0f4b
commit
c79b42023e
230
blinking_led.c
230
blinking_led.c
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@ -17,9 +17,12 @@
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// synthesis attribute LOC clk "P55 | IOSTANDARD = LVCMOS33"
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// synthesis attribute LOC led "P48 | SLEW = QUIETIO | DRIVE = 8"
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reg [14:0] counter;
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// COUNTER_SIZE tested as 14 (32K crystal) and 23 (20M crystal)
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`define COUNTER_SIZE 23
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reg [`COUNTER_SIZE:0] counter;
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always @(posedge clk) counter <= counter + 1;
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assign led = counter[14];
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assign led = counter[`COUNTER_SIZE];
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endmodule
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*/
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@ -27,24 +30,31 @@
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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int param_bits;
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int param_highest_bit;
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const char *param_clock_pin, *param_led_pin;
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int iob_clk_y, iob_clk_x, iob_clk_type_idx;
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int iob_led_y, iob_led_x, iob_led_type_idx;
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int logic_y, logic_x, logic_type_idx;
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int logic_x, logic_type_idx, cur_bit;
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int cur_y, next_y, i;
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struct fpgadev_logic logic_cfg;
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net_idx_t net;
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net_idx_t clock_net, net;
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// todo: test with clock=C10/IO_L37N_GCLK12_0, led=M16/IO_L46N_FOE_B_M1DQ3_1
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// currently: T8/R5
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// todo: we could support more ways to specify a pin:
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// "bpp:0,30,1" - die-specific bank/pair/positive
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// "name:T8" - package-specific pin (including unbonded ones)
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// "desc:IO_L30N_2" - package-specific description
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if (cmdline_help(argc, argv)) {
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printf( " %*s [-Dbits=14|23]\n"
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" %*s [-Dclock_pin=IO_L30N_GCLK0_USERCCLK_2|...]\n"
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" %*s [-Dled_pin=IO_L48P_D7_2|...]\n"
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printf( " %*s [-Dhighest_bit=14|23]\n"
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" %*s [-Dclock_pin=desc:IO_L30N_GCLK0_USERCCLK_2|...]\n"
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" %*s [-Dled_pin=desc:IO_L48P_D7_2|...]\n"
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"\n", (int) strlen(*argv), "",
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(int) strlen(*argv), "", (int) strlen(*argv), "");
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return 0;
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}
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if (!(param_bits = cmdline_intvar(argc, argv, "bits")))
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param_bits = 14;
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if (!(param_highest_bit = cmdline_intvar(argc, argv, "highest_bit")))
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param_highest_bit = 14;
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if (!(param_clock_pin = cmdline_strvar(argc, argv, "clock_pin")))
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param_clock_pin = "IO_L30N_GCLK0_USERCCLK_2";
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@ -68,139 +78,95 @@ int main(int argc, char** argv)
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fdev_iob_drive(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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8);
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logic_y = 58;
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// todo: temporary because our routing is so fragile...
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if (param_highest_bit == 14)
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cur_y = 58;
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else
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cur_y = 52;
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logic_x = 13;
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logic_type_idx = DEV_LOG_M_OR_L;
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CLEAR(logic_cfg);
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logic_cfg.a2d[LUT_A].lut6 = "(A6+~A6)*(~A5)";
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logic_cfg.a2d[LUT_A].lut5 = "1";
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logic_cfg.a2d[LUT_A].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_A].ff = FF_FF;
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logic_cfg.a2d[LUT_A].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_A].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_B].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_B].lut5 = "0";
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logic_cfg.a2d[LUT_B].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_B].ff = FF_FF;
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logic_cfg.a2d[LUT_B].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_B].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_C].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_C].lut5 = "0";
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logic_cfg.a2d[LUT_C].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_C].ff = FF_FF;
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logic_cfg.a2d[LUT_C].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_C].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_D].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_D].lut5 = "0";
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logic_cfg.a2d[LUT_D].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_D].ff = FF_FF;
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logic_cfg.a2d[LUT_D].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_D].ff_srinit = FF_SRINIT0;
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logic_cfg.clk_inv = CLKINV_CLK;
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logic_cfg.sync_attr = SYNCATTR_ASYNC;
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logic_cfg.precyinit = PRECYINIT_0;
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logic_cfg.cout_used = 1;
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fdev_logic_setconf(&model, logic_y, logic_x, logic_type_idx, &logic_cfg);
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logic_y = 57;
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logic_cfg.precyinit = 0;
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logic_cfg.a2d[LUT_A].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_A].lut5 = "0";
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fdev_logic_setconf(&model, logic_y, logic_x, logic_type_idx, &logic_cfg);
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logic_y = 56;
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fdev_logic_setconf(&model, logic_y, logic_x, logic_type_idx, &logic_cfg);
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logic_y = 55;
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logic_cfg.cout_used = 0;
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logic_cfg.a2d[LUT_C].lut6 = "A5";
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logic_cfg.a2d[LUT_C].lut5 = 0;
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logic_cfg.a2d[LUT_C].cy0 = 0;
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logic_cfg.a2d[LUT_C].ff = FF_FF;
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logic_cfg.a2d[LUT_C].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_C].ff_srinit = FF_SRINIT0;
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CLEAR(logic_cfg.a2d[LUT_D]);
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fdev_logic_setconf(&model, logic_y, logic_x, logic_type_idx, &logic_cfg);
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// clock to logic devs
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fnet_new(&model, &net);
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fnet_add_port(&model, net, iob_clk_y, iob_clk_x, DEV_IOB,
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// clock net
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fnet_new(&model, &clock_net);
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fnet_add_port(&model, clock_net, iob_clk_y, iob_clk_x, DEV_IOB,
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iob_clk_type_idx, IOB_OUT_I);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CLK);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CLK);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CLK);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CLK);
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fnet_route(&model, net);
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// vcc to logic devs
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_A6);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_B6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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for (cur_bit = 0; cur_bit <= param_highest_bit; cur_bit++) {
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RC_ASSERT(&model, cur_y != -1);
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if (!(cur_bit % 4)) { // beginning of slice
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CLEAR(logic_cfg);
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logic_cfg.clk_inv = CLKINV_CLK;
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logic_cfg.sync_attr = SYNCATTR_ASYNC;
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}
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if (!cur_bit) { // first bit
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logic_cfg.precyinit = PRECYINIT_0;
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logic_cfg.a2d[LUT_A].lut6 = "(A6+~A6)*(~A5)";
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logic_cfg.a2d[LUT_A].lut5 = "1";
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logic_cfg.a2d[LUT_A].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_A].ff = FF_FF;
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logic_cfg.a2d[LUT_A].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_A].ff_srinit = FF_SRINIT0;
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} else if (cur_bit == param_highest_bit) {
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logic_cfg.a2d[cur_bit%4].lut6 = "A5";
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logic_cfg.a2d[cur_bit%4].ff = FF_FF;
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logic_cfg.a2d[cur_bit%4].ff_mux = MUX_XOR;
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logic_cfg.a2d[cur_bit%4].ff_srinit = FF_SRINIT0;
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} else {
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logic_cfg.a2d[cur_bit%4].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[cur_bit%4].lut5 = "0";
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logic_cfg.a2d[cur_bit%4].cy0 = CY0_O5;
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logic_cfg.a2d[cur_bit%4].ff = FF_FF;
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logic_cfg.a2d[cur_bit%4].ff_mux = MUX_XOR;
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logic_cfg.a2d[cur_bit%4].ff_srinit = FF_SRINIT0;
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}
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if (cur_bit%4 == 3 || cur_bit == param_highest_bit) {
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static const int out_pin[] = {LO_AQ, LO_BQ, LO_CQ, LO_DQ};
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static const int in_pin[] = {LI_A5, LI_B5, LI_C5, LI_D5};
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_A6);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_B6);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C6);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_D6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_A6);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_B6);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C6);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_D6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_A6);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_B6);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C6);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_D6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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// carry chain
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CIN);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_COUT);
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fnet_route(&model, net);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CIN);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_COUT);
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fnet_route(&model, net);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CIN);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_COUT);
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fnet_route(&model, net);
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// bit chain
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{
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int out_pin[] = {LO_AQ, LO_BQ, LO_CQ, LO_DQ};
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int in_pin[] = {LI_A5, LI_B5, LI_C5, LI_D5};
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int cur_y, i;
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for (cur_y = 58; cur_y >= 55; cur_y--) {
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for (i = 0; i < 4; i++) {
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if (cur_y == 55 && i >= 2)
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break;
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next_y = regular_row_up(cur_y, &model);
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if (cur_bit < param_highest_bit) {
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RC_ASSERT(&model, next_y != -1);
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logic_cfg.cout_used = 1;
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// carry chain
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fnet_new(&model, &net);
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fnet_add_port(&model, net, cur_y, 13, DEV_LOGIC, DEV_LOG_M_OR_L, out_pin[i]);
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fnet_add_port(&model, net, cur_y, 13, DEV_LOGIC, DEV_LOG_M_OR_L, in_pin[i]);
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LO_COUT);
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fnet_add_port(&model, net, next_y, logic_x, DEV_LOGIC, logic_type_idx, LI_CIN);
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fnet_route(&model, net);
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}
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fdev_logic_setconf(&model, cur_y, logic_x, logic_type_idx, &logic_cfg);
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// clock net
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fnet_add_port(&model, clock_net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_CLK);
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// lut5 net (drive vcc into A6 to enable lut5)
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if (logic_cfg.a2d[LUT_A].lut5
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|| logic_cfg.a2d[LUT_B].lut5
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|| logic_cfg.a2d[LUT_C].lut5
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|| logic_cfg.a2d[LUT_D].lut5) {
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fnet_new(&model, &net);
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if (logic_cfg.a2d[LUT_A].lut5)
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_A6);
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if (logic_cfg.a2d[LUT_B].lut5)
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_B6);
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if (logic_cfg.a2d[LUT_C].lut5)
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_C6);
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if (logic_cfg.a2d[LUT_D].lut5)
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_D6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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}
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for (i = 0; i <= cur_bit%4; i++) {
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fnet_new(&model, &net);
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, out_pin[i]);
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, in_pin[i]);
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if (cur_bit - cur_bit%4 + i == param_highest_bit)
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fnet_add_port(&model, net, iob_led_y, iob_led_x, DEV_IOB,
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iob_led_type_idx, IOB_IN_O);
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fnet_route(&model, net);
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}
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cur_y = next_y;
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}
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}
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_CQ);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C5);
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fnet_add_port(&model, net, iob_led_y, iob_led_x, DEV_IOB,
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iob_led_type_idx, IOB_IN_O);
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fnet_route(&model, net);
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fnet_route(&model, clock_net);
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write_floorplan(stdout, &model, FP_DEFAULT);
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return fpga_free_model(&model);
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}
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31
fp2bit.c
31
fp2bit.c
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@ -12,15 +12,14 @@
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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FILE *fbits, *fp = 0;
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FILE *fbits = 0, *fp = 0;
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int rc = -1;
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fbits = 0;
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if (argc != 3) {
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if (argc != 2 && argc != 3) {
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fprintf(stderr,
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"\n"
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"%s - floorplan to bitstream\n"
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"Usage: %s <floorplan_file|- for stdin> <bits_file>\n"
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"Usage: %s <floorplan_file|- for stdin> [<bits_file>]\n"
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"\n", argv[0], argv[0]);
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goto fail;
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}
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@ -34,10 +33,26 @@ int main(int argc, char** argv)
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goto fail;
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}
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}
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fbits = fopen(argv[2], "w");
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if (!fbits) {
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fprintf(stderr, "Error opening %s.\n", argv[2]);
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goto fail;
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if (argc == 3) {
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fbits = fopen(argv[2], "w");
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if (!fbits) {
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fprintf(stderr, "Error opening %s.\n", argv[2]);
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goto fail;
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}
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} else {
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if (fp == stdin)
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fbits = stdout;
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else {
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char out_name[256];
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int i = strlen(argv[1]);
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while (i && argv[1][i-1] != '.') i--;
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snprintf(out_name, sizeof(out_name), "%.*sbit", i, argv[1]);
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fbits = fopen(out_name, "w");
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if (!fbits) {
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fprintf(stderr, "Error opening %s.\n", out_name);
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goto fail;
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}
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}
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}
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if ((rc = fpga_build_model(&model, XC6SLX9, TQG144)))
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