more wires
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6
README
6
README
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@ -53,7 +53,7 @@ Design Principles
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- automatic test suite
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- public domain software
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TODO (as of October, 2012)
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TODO (as of November, 2012)
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short-term (1 month):
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* example: blinking_led
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@ -65,7 +65,7 @@ short-term (1 month):
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mid-term (6 months):
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* support chips other than xc6slx9, maybe an ftg256 or fgg484-packaged
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xc6 or the xc7a100
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* more cases in switches (98% done) and inter-tile connections (15% done)
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* more cases in switches (98% done) and inter-tile connections (70% done)
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* more cases in logic block configuration
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* configuration of bram and macc blocks, bram initialization data
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* write standard design elements for libfpga-stdlib library
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@ -85,7 +85,7 @@ long-term (>6 months):
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* support lm32 or openrisc core, either via libfpga or iverilog backend
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* ipv6 or vnc in hardware?
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* iverilog fpga backend
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* design fpga 'core' that uses high-speed icap/reconfig to process data
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* design fpga core that uses high-speed icap/reconfig to process data
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ChangeLog
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11
libs/model.h
11
libs/model.h
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@ -256,6 +256,10 @@ int is_aty(int check, struct fpga_model* model, int y);
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|X_CENTER_ROUTING_COL \
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|X_LEFT_IO_ROUTING_COL \
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|X_RIGHT_IO_ROUTING_COL)
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#define X_CENTER_MAJOR (X_CENTER_ROUTING_COL \
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|X_CENTER_LOGIC_COL \
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|X_CENTER_CMTPLL_COL \
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|X_CENTER_REGS_COL)
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// todo and realizations:
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// * maybe the center_logic and routing cols can also be
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@ -887,8 +891,8 @@ struct seed_data
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const char* str;
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};
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void seed_strx(struct fpga_model *model, struct seed_data *data);
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void seed_stry(struct fpga_model *model, struct seed_data *data);
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void seed_strx(struct fpga_model *model, const struct seed_data *data);
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void seed_stry(struct fpga_model *model, const struct seed_data *data);
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#define MAX_WIRENAME_LEN 64
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@ -1026,6 +1030,9 @@ enum extra_wires {
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IOCLK,
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PLLCE,
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PLLCLK,
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CKPIN,
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CLK_FEEDBACK,
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CLK_INDIRECT,
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VCC_WIRE = 150,
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GND_WIRE,
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GCLK0 = 200, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7,
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File diff suppressed because it is too large
Load Diff
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@ -523,7 +523,7 @@ fail:
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return rc;
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}
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void seed_strx(struct fpga_model *model, struct seed_data *data)
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void seed_strx(struct fpga_model *model, const struct seed_data *data)
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{
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int x, i;
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for (x = 0; x < model->x_width; x++) {
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@ -535,7 +535,7 @@ void seed_strx(struct fpga_model *model, struct seed_data *data)
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}
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}
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void seed_stry(struct fpga_model *model, struct seed_data *data)
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void seed_stry(struct fpga_model *model, const struct seed_data *data)
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{
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int y, i;
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for (y = 0; y < model->y_height; y++) {
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