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This commit is contained in:
Wolfgang Spraul 2012-11-11 07:40:39 +01:00
parent 865dbfbb73
commit c88c46b80d
4 changed files with 698 additions and 287 deletions
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6
README
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@ -53,7 +53,7 @@ Design Principles
- automatic test suite - automatic test suite
- public domain software - public domain software
TODO (as of October, 2012) TODO (as of November, 2012)
short-term (1 month): short-term (1 month):
* example: blinking_led * example: blinking_led
@ -65,7 +65,7 @@ short-term (1 month):
mid-term (6 months): mid-term (6 months):
* support chips other than xc6slx9, maybe an ftg256 or fgg484-packaged * support chips other than xc6slx9, maybe an ftg256 or fgg484-packaged
xc6 or the xc7a100 xc6 or the xc7a100
* more cases in switches (98% done) and inter-tile connections (15% done) * more cases in switches (98% done) and inter-tile connections (70% done)
* more cases in logic block configuration * more cases in logic block configuration
* configuration of bram and macc blocks, bram initialization data * configuration of bram and macc blocks, bram initialization data
* write standard design elements for libfpga-stdlib library * write standard design elements for libfpga-stdlib library
@ -85,7 +85,7 @@ long-term (>6 months):
* support lm32 or openrisc core, either via libfpga or iverilog backend * support lm32 or openrisc core, either via libfpga or iverilog backend
* ipv6 or vnc in hardware? * ipv6 or vnc in hardware?
* iverilog fpga backend * iverilog fpga backend
* design fpga 'core' that uses high-speed icap/reconfig to process data * design fpga core that uses high-speed icap/reconfig to process data
ChangeLog ChangeLog

11
libs/model.h
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@ -256,6 +256,10 @@ int is_aty(int check, struct fpga_model* model, int y);
|X_CENTER_ROUTING_COL \ |X_CENTER_ROUTING_COL \
|X_LEFT_IO_ROUTING_COL \ |X_LEFT_IO_ROUTING_COL \
|X_RIGHT_IO_ROUTING_COL) |X_RIGHT_IO_ROUTING_COL)
#define X_CENTER_MAJOR (X_CENTER_ROUTING_COL \
|X_CENTER_LOGIC_COL \
|X_CENTER_CMTPLL_COL \
|X_CENTER_REGS_COL)
// todo and realizations: // todo and realizations:
// * maybe the center_logic and routing cols can also be // * maybe the center_logic and routing cols can also be
@ -887,8 +891,8 @@ struct seed_data
const char* str; const char* str;
}; };
void seed_strx(struct fpga_model *model, struct seed_data *data); void seed_strx(struct fpga_model *model, const struct seed_data *data);
void seed_stry(struct fpga_model *model, struct seed_data *data); void seed_stry(struct fpga_model *model, const struct seed_data *data);
#define MAX_WIRENAME_LEN 64 #define MAX_WIRENAME_LEN 64
@ -1026,6 +1030,9 @@ enum extra_wires {
IOCLK, IOCLK,
PLLCE, PLLCE,
PLLCLK, PLLCLK,
CKPIN,
CLK_FEEDBACK,
CLK_INDIRECT,
VCC_WIRE = 150, VCC_WIRE = 150,
GND_WIRE, GND_WIRE,
GCLK0 = 200, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7, GCLK0 = 200, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7,

956
libs/model_conns.c
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File diff suppressed because it is too large Load Diff

4
libs/model_helper.c
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@ -523,7 +523,7 @@ fail:
return rc; return rc;
} }
void seed_strx(struct fpga_model *model, struct seed_data *data) void seed_strx(struct fpga_model *model, const struct seed_data *data)
{ {
int x, i; int x, i;
for (x = 0; x < model->x_width; x++) { for (x = 0; x < model->x_width; x++) {
@ -535,7 +535,7 @@ void seed_strx(struct fpga_model *model, struct seed_data *data)
} }
} }
void seed_stry(struct fpga_model *model, struct seed_data *data) void seed_stry(struct fpga_model *model, const struct seed_data *data)
{ {
int y, i; int y, i;
for (y = 0; y < model->y_height; y++) { for (y = 0; y < model->y_height; y++) {