wires
This commit is contained in:
Wolfgang Spraul
parent
44cd3b0b7f
commit
c9718d0372
277
model.c
277
model.c
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@ -187,6 +187,46 @@ int fpga_build_model(struct fpga_model* model, int fpga_rows, const char* column
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return 0;
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}
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const char* pf(const char* fmt, ...)
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{
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// safe to call it 8 times in 1 expression (such as function params)
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static char pf_buf[8][128];
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static int last_buf = 0;
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va_list list;
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last_buf = (last_buf+1)%8;
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pf_buf[last_buf][0] = 0;
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va_start(list, fmt);
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vsnprintf(pf_buf[last_buf], sizeof(pf_buf[0]), fmt, list);
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va_end(list);
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return pf_buf[last_buf];
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}
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const char* wpref(int flags, const char* wire_name)
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{
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static char buf[8][128];
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static int last_buf = 0;
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char* prefix;
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if (flags & TF_CHIP_HORIZ_AXSYMM_CENTER)
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prefix = "REGC_INT_";
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else if (flags & TF_CHIP_HORIZ_AXSYMM)
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prefix = "REGH_";
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else if (flags & TF_ROW_HORIZ_AXSYMM)
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prefix = "HCLK_";
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else if (flags & TF_UNDER_TOPMOST_TILE)
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prefix = "IOI_TTERM_";
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else if (flags & TF_ABOVE_BOTTOMMOST_TILE)
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prefix = "IOI_BTERM_";
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else
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prefix = "";
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last_buf = (last_buf+1)%8;
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buf[last_buf][0] = 0;
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strcpy(buf[last_buf], prefix);
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strcat(buf[last_buf], wire_name);
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return buf[last_buf];
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}
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#define CONN_NAMES_INCREMENT 128
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#define CONNS_INCREMENT 128
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@ -283,25 +323,60 @@ int add_conn_bi(struct fpga_model* model, int y1, int x1, const char* name1, int
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return add_conn_uni(model, y2, x2, name2, y1, x1, name1);
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}
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const char* pf(const char* fmt, ...)
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int add_conn_range(struct fpga_model* model, int y1, int x1, const char* name1, int start1, int count, int y2, int x2, const char* name2, int start2)
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{
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// safe to call it 4 times in 1 expression (such as function params)
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static char pf_buf[4][128];
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static int last_buf = 0;
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va_list list;
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last_buf = (last_buf+1)%4;
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pf_buf[last_buf][0] = 0;
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va_start(list, fmt);
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vsnprintf(pf_buf[last_buf], sizeof(pf_buf[0]), fmt, list);
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va_end(list);
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return pf_buf[last_buf];
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char buf1[128], buf2[128];
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int rc, i;
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if (count < 1)
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return add_conn_bi(model, y1, x1, name1, y2, x2, name2);
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for (i = 0; i < count; i++) {
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snprintf(buf1, sizeof(buf1), name1, start1+i);
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snprintf(buf2, sizeof(buf2), name2, start2+i);
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rc = add_conn_bi(model, y1, x1, buf1, y2, x2, buf2);
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if (rc) return rc;
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}
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return 0;
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}
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struct w_point // wire point
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{
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const char* name;
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int start_count; // if there is a %i in the name, this is the start number
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int y, x;
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};
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struct w_net
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{
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int wire_count; // if > 0, %i in the name will be incremented this many times
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struct w_point pts[8];
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};
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int add_conn_net(struct fpga_model* model, struct w_net* net)
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{
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int i, j, rc;
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for (i = 0; net->pts[i].name[0] && i < sizeof(net->pts)/sizeof(net->pts[0]); i++) {
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for (j = i+1; net->pts[j].name[0] && j < sizeof(net->pts)/sizeof(net->pts[0]); j++) {
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rc = add_conn_range(model,
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net->pts[i].y, net->pts[i].x,
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wpref(model->tiles[net->pts[i].y * model->tile_x_range + net->pts[i].x].flags, net->pts[i].name),
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net->pts[i].start_count,
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net->wire_count,
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net->pts[j].y, net->pts[j].x,
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wpref(model->tiles[net->pts[j].y * model->tile_x_range + net->pts[j].x].flags, net->pts[j].name),
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net->pts[j].start_count);
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if (rc) goto xout;
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}
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}
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return 0;
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xout:
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return rc;
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}
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int run_wires(struct fpga_model* model)
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{
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struct fpga_tile* tile, *tile_up1, *tile_up2, *tile_dn1, *tile_dn2;
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char b_wire[16], m_wire[16], e_wire[16], r1b_wire[16], r1e_wire[16];
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char* wire_fmt;
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int x, y, i, rc;
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rc = -1;
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@ -317,64 +392,58 @@ int run_wires(struct fpga_model* model)
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if (tile->flags & TF_VERT_ROUTING) {
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// NR1B-NR1E
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if (tile_up1->flags & TF_UNDER_TOPMOST_TILE) {
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for (i = 0; i <= 3; i++) {
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if ((rc = add_conn_bi(model, y, x, pf("NR1B%i", i), y-1, x, pf("IOI_TTERM_NR1B%i", i)))) goto xout;
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}
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} else if (tile_up1->flags & (TF_ROW_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM)) {
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if (tile_up1->flags & TF_ROW_HORIZ_AXSYMM)
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wire_fmt = "HCLK_%s";
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else if (tile[3].flags & TF_CHIP_VERT_AXSYMM)
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wire_fmt = "REGC_INT_%s";
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else
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wire_fmt = "REGH_%s";
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for (i = 0; i <= 3; i++) {
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sprintf(r1b_wire, "NR1B%i", i);
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sprintf(r1e_wire, "NR1E%i", i);
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-1, x, pf(wire_fmt, r1e_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y, x, r1b_wire, y-2, x, r1e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, pf(wire_fmt, r1e_wire), y-2, x, r1e_wire))) goto xout;
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}
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{ struct w_net net = {
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4,
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{{ "NR1B%i", 0, y, x },
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{ "NR1B%i", 0, y-1, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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} else if (tile_up1->flags & (TF_ROW_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM_CENTER)) {
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{ struct w_net net = {
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4,
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{{ "NR1B%i", 0, y, x },
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{ "NR1E%i", 0, y-1, x },
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{ "NR1E%i", 0, y-2, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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} else {
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for (i = 0; i <= 3; i++) {
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if ((rc = add_conn_bi(model, y, x, pf("NR1B%i", i), y-1, x, pf("NR1E%i", i)))) goto xout;
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{ struct w_net net = {
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4,
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{{ "NR1B%i", 0, y, x },
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{ "NR1E%i", 0, y-1, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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if (tile->flags & TF_MACC_COL && tile_dn1->flags & TF_ABOVE_BOTTOMMOST_TILE) {
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if ((rc = add_conn_bi(model, y, x, pf("NR1E%i", i), y+1, x, pf("IOI_BTERM_NR1E%i", i)))) goto xout;
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}
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{ struct w_net net = {
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4,
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{{ "NR1E%i", 0, y, x },
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{ "NR1E%i", 0, y+1, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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}
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}
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// NN2E_S0
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if (tile_up1->flags & TF_UNDER_TOPMOST_TILE) {
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if ((rc = add_conn_bi(model, y, x, "NN2E_S0", y-1, x, "IOI_TTERM_NN2E_S0"))) goto xout;
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{ struct w_net net = {
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-1,
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{{ "NN2E_S0", 0, y, x },
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{ "NN2E_S0", 0, y-1, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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} else if (tile_up2->flags & TF_UNDER_TOPMOST_TILE) {
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} else if (tile_up1->flags & (TF_ROW_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM)) {
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if (tile_up1->flags & TF_ROW_HORIZ_AXSYMM)
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wire_fmt = "HCLK_%s";
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else if (tile[3].flags & TF_CHIP_VERT_AXSYMM)
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wire_fmt = "REGC_INT_%s";
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else
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wire_fmt = "REGH_%s";
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if ((rc = add_conn_bi(model, y-1, x, pf(wire_fmt, "NN2M0"), y-2, x, "NN2E_S0"))) goto xout;
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} else if (tile_up1->flags & (TF_ROW_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM_CENTER)) {
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if ((rc = add_conn_bi(model, y-1, x, wpref(tile_up1->flags, "NN2M0"), y-2, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y-3, x, "NN2E0", y-2, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y, x, "NN2B0", y-2, x, "NN2E_S0"))) goto xout;
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} else if (tile_up2->flags & (TF_ROW_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM)) {
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if (tile_up2->flags & TF_ROW_HORIZ_AXSYMM)
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wire_fmt = "HCLK_%s";
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else if (tile[3].flags & TF_CHIP_VERT_AXSYMM)
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wire_fmt = "REGC_INT_%s";
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else
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wire_fmt = "REGH_%s";
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if ((rc = add_conn_bi(model, y-2, x, pf(wire_fmt, "NN2E0"), y-1, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y, x, "NN2B0", y-2, x, pf(wire_fmt, "NN2E_S0")))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, pf(wire_fmt, "NN2E_S0"), y-1, x, "NN2M0"))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, pf(wire_fmt, "NN2E_S0"), y-1, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, pf(wire_fmt, "NN2E_S0"), y-3, x, "NN2E0"))) goto xout;
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if ((rc = add_conn_bi(model, y-3, x, "NN2E0", y-1, x, "NN2E_S0"))) goto xout;
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} else if (tile_up2->flags & (TF_ROW_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM | TF_CHIP_HORIZ_AXSYMM_CENTER)) {
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if ((rc = add_conn_bi(model, y, x, "NN2B0", y-1, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y, x, "NN2B0", y-2, x, wpref(tile_up2->flags, "NN2E_S0")))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, wpref(tile_up2->flags, "NN2E0"), y-1, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, wpref(tile_up2->flags, "NN2E_S0"), y-1, x, "NN2M0"))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, wpref(tile_up2->flags, "NN2E_S0"), y-1, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, wpref(tile_up2->flags, "NN2E_S0"), y-3, x, "NN2E0"))) goto xout;
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if ((rc = add_conn_bi(model, y-3, x, "NN2E0", y-1, x, "NN2E_S0"))) goto xout;
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} else {
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if ((rc = add_conn_bi(model, y, x, "NN2B0", y-1, x, "NN2E_S0"))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, "NN2E0", y-1, x, "NN2E_S0"))) goto xout;
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@ -388,56 +457,50 @@ int run_wires(struct fpga_model* model)
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}
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}
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if (!(tile->flags & TF_DIRWIRE_START))
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continue;
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for (i = 0; i <= 3; i++) {
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sprintf(b_wire, "NN2B%i", i);
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sprintf(m_wire, "NN2M%i", i);
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sprintf(e_wire, "NN2E%i", i);
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sprintf(r1b_wire, "NR1B%i", i);
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sprintf(r1e_wire, "NR1E%i", i);
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if (tile->flags & TF_DIRWIRE_START) {
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if (tile_up1->flags & TF_UNDER_TOPMOST_TILE) {
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, pf("IOI_TTERM_%s", b_wire)))) goto xout;
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{ struct w_net net = {
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4,
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{{ "NN2B%i", 0, y, x },
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{ "NN2B%i", 0, y-1, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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} else if (tile_up2->flags & TF_UNDER_TOPMOST_TILE) {
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-2, x, pf("IOI_TTERM_%s", m_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, pf("IOI_TTERM_%s", m_wire)))) goto xout;
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} else if (tile_up1->flags & (TF_ROW_HORIZ_AXSYMM|TF_CHIP_HORIZ_AXSYMM)) {
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{ struct w_net net = {
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4,
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{{ "NN2B%i", 0, y, x },
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{ "NN2M%i", 0, y-1, x },
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{ "NN2M%i", 0, y-2, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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} else if (tile_up1->flags & (TF_ROW_HORIZ_AXSYMM|TF_CHIP_HORIZ_AXSYMM|TF_CHIP_HORIZ_AXSYMM_CENTER)) {
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if (tile_up1->flags & TF_ROW_HORIZ_AXSYMM)
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wire_fmt = "HCLK_%s";
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else if (tile[3].flags & TF_CHIP_VERT_AXSYMM)
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wire_fmt = "REGC_INT_%s";
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else
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wire_fmt = "REGH_%s";
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, pf(wire_fmt, m_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-2, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, pf(wire_fmt, m_wire), y-2, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, pf(wire_fmt, m_wire), y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, m_wire, y-3, x, e_wire))) goto xout;
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} else if (tile_up2->flags & (TF_ROW_HORIZ_AXSYMM|TF_CHIP_HORIZ_AXSYMM)) {
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if (tile_up2->flags & TF_ROW_HORIZ_AXSYMM)
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wire_fmt = "HCLK_%s";
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else if (tile[3].flags & TF_CHIP_VERT_AXSYMM)
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wire_fmt = "REGC_INT_%s";
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else
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wire_fmt = "REGH_%s";
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-2, x, pf(wire_fmt, e_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, pf(wire_fmt, e_wire)))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, m_wire, y-3, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-2, x, pf(wire_fmt, e_wire), y-3, x, e_wire))) goto xout;
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{ struct w_net net = {
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4,
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{{ "NN2B%i", 0, y, x },
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{ "NN2M%i", 0, y-1, x },
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{ "NN2M%i", 0, y-2, x },
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{ "NN2E%i", 0, y-3, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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} else if (tile_up2->flags & (TF_ROW_HORIZ_AXSYMM|TF_CHIP_HORIZ_AXSYMM|TF_CHIP_HORIZ_AXSYMM_CENTER)) {
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{ struct w_net net = {
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4,
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{{ "NN2B%i", 0, y, x },
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{ "NN2M%i", 0, y-1, x },
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{ "NN2E%i", 0, y-2, x },
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{ "NN2E%i", 0, y-3, x },
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{ "" }}};
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if ((rc = add_conn_net(model, &net))) goto xout; }
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} else {
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if ((rc = add_conn_bi(model, y, x, b_wire, y-1, x, m_wire))) goto xout;
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if ((rc = add_conn_bi(model, y, x, b_wire, y-2, x, e_wire))) goto xout;
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if ((rc = add_conn_bi(model, y-1, x, m_wire, y-2, x, e_wire))) goto xout;
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{ struct w_net net = {
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4,
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{{ "NN2B%i", 0, y, x },
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{ "NN2M%i", 0, y-1, x },
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{ "NN2E%i", 0, y-2, x },
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{ "" }}};
|
||||
if ((rc = add_conn_net(model, &net))) goto xout; }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -762,9 +825,13 @@ int init_tiles(struct fpga_model* model)
|
|||
model->tiles[(tile_rows-2)*tile_columns + i + 3].type = REGV_TERM_B;
|
||||
|
||||
model->tiles[center_row*tile_columns + i].type = REGC_ROUTING;
|
||||
model->tiles[center_row*tile_columns + i].flags |= TF_CHIP_HORIZ_AXSYMM_CENTER;
|
||||
model->tiles[center_row*tile_columns + i + 1].type = REGC_LOGIC;
|
||||
model->tiles[center_row*tile_columns + i + 1].flags |= TF_CHIP_HORIZ_AXSYMM_CENTER;
|
||||
model->tiles[center_row*tile_columns + i + 2].type = REGC_CMT;
|
||||
model->tiles[center_row*tile_columns + i + 2].flags |= TF_CHIP_HORIZ_AXSYMM_CENTER;
|
||||
model->tiles[center_row*tile_columns + i + 3].type = CENTER;
|
||||
model->tiles[center_row*tile_columns + i + 3].flags |= TF_CHIP_HORIZ_AXSYMM_CENTER;
|
||||
|
||||
i += 4;
|
||||
break;
|
||||
|
|
|
|||
11
model.h
11
model.h
|
|
@ -130,11 +130,12 @@ enum fpga_tile_type
|
|||
#define TF_ROW_HORIZ_AXSYMM 0x0020
|
||||
#define TF_BOTTOM_OF_ROW 0x0040
|
||||
#define TF_CHIP_HORIZ_AXSYMM 0x0080
|
||||
#define TF_CHIP_VERT_AXSYMM 0x0100
|
||||
#define TF_VERT_ROUTING 0x0200
|
||||
#define TF_LOGIC_COL 0x0400
|
||||
#define TF_MACC_COL 0x0800
|
||||
#define TF_BRAM_COL 0x1000
|
||||
#define TF_CHIP_HORIZ_AXSYMM_CENTER 0x0100
|
||||
#define TF_CHIP_VERT_AXSYMM 0x0200
|
||||
#define TF_VERT_ROUTING 0x0400
|
||||
#define TF_LOGIC_COL 0x0800
|
||||
#define TF_MACC_COL 0x1000
|
||||
#define TF_BRAM_COL 0x2000
|
||||
|
||||
struct fpga_tile
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user