diff --git a/hello_world.c b/hello_world.c index e196030..bd0eb87 100644 --- a/hello_world.c +++ b/hello_world.c @@ -9,8 +9,6 @@ #include "floorplan.h" #include "control.h" -// Searches a connection in search_y/search_x that connects to -// target_y/target_x/target_pt. int fpga_find_conn(struct fpga_model* model, int search_y, int search_x, str16_t* pt, int target_y, int target_x, str16_t target_pt) { @@ -44,34 +42,27 @@ static int froute_direct(struct fpga_model* model, int start_y, int start_x, struct sw_set end_switches; int i, rc; -printf("start %02i %02i %s end %02i %02i %s\n", start_y, start_x, strarray_lookup(&model->str, start_pt), - end_y, end_x, strarray_lookup(&model->str, end_pt)); - rc = fpga_swset_fromto(model, end_y, end_x, end_pt, SW_TO, &end_switches); if (rc) FAIL(rc); -fpga_swset_print(model, end_y, end_x, &end_switches, SW_TO); if (!end_switches.len) FAIL(EINVAL); -// TODO: WR1 is not in model, so cannot connect... - if (construct_sw_conns(&conns, model, start_y, start_x, start_pt, SW_FROM, /*max_depth*/ 1)) - { HERE(); return; } + rc = construct_sw_conns(&conns, model, start_y, start_x, start_pt, + SW_FROM, /*max_depth*/ 1); + if (rc) FAIL(rc); + while (fpga_switch_conns(&conns) != NO_CONN) { if (conns.dest_y != end_y || conns.dest_x != end_x) continue; for (i = 0; i < end_switches.len; i++) { - if (conns.dest_str_i == fpga_switch_str_i(model, end_y, end_x, end_switches.sw[i], SW_FROM)) { + if (conns.dest_str_i == fpga_switch_str_i(model, end_y, + end_x, end_switches.sw[i], SW_FROM)) { *start_set = conns.chain.set; end_set->len = 1; end_set->sw[0] = end_switches.sw[i]; return 0; } } - printf("sw %s conn y%02i x%02i %s\n", fmt_swset(model, start_y, start_x, - &conns.chain.set, SW_FROM), - conns.dest_y, conns.dest_x, - strarray_lookup(&model->str, conns.dest_str_i)); } - printf("sw -\n"); destruct_sw_conns(&conns); start_set->len = 0; end_set->len = 0; @@ -85,9 +76,8 @@ static int fnet_autoroute(struct fpga_model* model, net_idx_t net_i) struct fpga_net* net_p; struct fpga_device* dev_p, *out_dev, *in_dev; struct switch_to_yx switch_to; - struct sw_chain ch; - struct sw_set logic_set, logic_route_set, iologic_route_set; - str16_t route_pt; + struct sw_set logic_route_set, iologic_route_set; + struct switch_to_rel switch_to_rel; int i, out_i, in_i, rc; // todo: gnd and vcc nets are special and have no outpin @@ -153,94 +143,105 @@ static int fnet_autoroute(struct fpga_model* model, net_idx_t net_i) switch_to.set.sw, switch_to.set.len); if (rc) FAIL(rc); - // switch inside logic tile - rc = fpga_swset_fromto(model, net_p->el[in_i].y, - net_p->el[in_i].x, - in_dev->pinw[net_p->el[in_i].idx & NET_IDX_MASK], - SW_TO, &logic_set); + // switch from logic tile to logic routing tile + switch_to_rel.model = model; + switch_to_rel.start_y = net_p->el[in_i].y; + switch_to_rel.start_x = net_p->el[in_i].x; + switch_to_rel.start_switch = + in_dev->pinw[net_p->el[in_i].idx & NET_IDX_MASK]; + switch_to_rel.from_to = SW_TO; + switch_to_rel.rel_y = 0; + switch_to_rel.rel_x = -1; + switch_to_rel.target_connpt = STRIDX_NO_ENTRY; + rc = fpga_switch_to_rel(&switch_to_rel); if (rc) FAIL(rc); - if (logic_set.len != 1) FAIL(EINVAL); - - // switch in routing tile connecting to logic tile - rc = fpga_find_conn(model, - net_p->el[in_i].y, net_p->el[in_i].x-1, &route_pt, - net_p->el[in_i].y, net_p->el[in_i].x, - fpga_switch_str_i(model, net_p->el[in_i].y, - net_p->el[in_i].x, logic_set.sw[0], SW_FROM)); + rc = fnet_add_sw(model, net_i, switch_to_rel.start_y, + switch_to_rel.start_x, switch_to_rel.set.sw, + switch_to_rel.set.len); if (rc) FAIL(rc); -printf("%s\n", strarray_lookup(&model->str, route_pt)); // route from ilogic routing to logic routing rc = froute_direct(model, switch_to.dest_y, switch_to.dest_x, switch_to.dest_connpt, - net_p->el[in_i].y, net_p->el[in_i].x-1, route_pt, + switch_to_rel.dest_y, switch_to_rel.dest_x, + switch_to_rel.dest_connpt, &iologic_route_set, &logic_route_set); if (rc) FAIL(rc); -#if 0 -static int froute_direct(struct fpga_model* model, int start_y, int start_x, - str16_t start_pt, int end_y, int end_x, str16_t end_pt, - int from_to, struct sw_set* sw) - - switch_to.yx_req = YX_ROUTING_TO_FABLOGIC; - switch_to.flags = SWTO_YX_CLOSEST; - switch_to.model = model; - switch_to.y = switch_to.dest_y; - switch_to.x = switch_to.dest_x; - switch_to.start_switch = switch_to.dest_connpt; - switch_to.from_to = SW_FROM; -printf("from1 y%02i x%02i %s\n", switch_to.dest_y, switch_to.dest_x, - strarray_lookup(&model->str, switch_to.dest_connpt)); -67/12/LOGICOUT7 - -> WR1B1 - -> 68/12 WR1E1 - -> LOGICIN_B30 -params: 67/12/LOGICOUT7 - dest: 68/12/LOGICIN_B30 - -func: - SW_TO LOGICIN_B30 - go through, call switch_to with target_connpt - - rc = fpga_switch_to_yx(&switch_to); + if (!iologic_route_set.len || !logic_route_set.len) FAIL(EINVAL); + rc = fnet_add_sw(model, net_i, switch_to.dest_y, switch_to.dest_x, + iologic_route_set.sw, iologic_route_set.len); if (rc) FAIL(rc); - rc = fnet_add_sw(model, net_i, switch_to.y, switch_to.x, - switch_to.set.sw, switch_to.set.len); + rc = fnet_add_sw(model, net_i, net_p->el[in_i].y, net_p->el[in_i].x-1, + logic_route_set.sw, logic_route_set.len); if (rc) FAIL(rc); - switch_to.yx_req = YX_DEV_LOGIC; - switch_to.flags = SWTO_YX_TARGET_CONNPT|SWTO_YX_MAX_SWITCH_DEPTH; - switch_to.model = model; - switch_to.y = switch_to.dest_y; - switch_to.x = switch_to.dest_x; - switch_to.start_switch = switch_to.dest_connpt; - switch_to.from_to = SW_FROM; - switch_to.max_switch_depth = 1; -printf("from y%02i x%02i %s\n", switch_to.dest_y, switch_to.dest_x, - strarray_lookup(&model->str, switch_to.dest_connpt)); - - rc = construct_sw_chain(&ch, model, switch_to.dest_y, - switch_to.dest_x+1, in_dev->pinw[net_p->el[in_i].idx - & NET_IDX_MASK], SW_TO, /*max_depth*/ -1, - /*block*/ 0, 0); - if (rc) FAIL(rc); - if (fpga_switch_chain(&ch) == NO_CONN) FAIL(EINVAL); - if (!ch.set.len) { HERE(); FAIL(EINVAL); } - switch_to.target_connpt = fpga_switch_str_i(model, - switch_to.dest_y, switch_to.dest_x+1, - ch.set.sw[ch.set.len-1], SW_FROM); - rc = fpga_switch_to_yx(&switch_to); - if (rc) FAIL(rc); -printf_switch_to_yx_result(&switch_to); - rc = fnet_add_sw(model, net_i, switch_to.y, switch_to.x, - switch_to.set.sw, switch_to.set.len); - if (rc) FAIL(rc); -#endif - return 0; } if (out_dev->type == DEV_LOGIC) { if (in_dev->type != DEV_IOB) FAIL(ENOTSUP); + + // switch from ologic to iob + switch_to.yx_req = YX_DEV_OLOGIC; + switch_to.flags = SWTO_YX_DEF; + switch_to.model = model; + switch_to.y = net_p->el[in_i].y; + switch_to.x = net_p->el[in_i].x; + switch_to.start_switch = in_dev->pinw[net_p->el[in_i].idx + & NET_IDX_MASK]; + switch_to.from_to = SW_TO; + rc = fpga_switch_to_yx(&switch_to); + if (rc) FAIL(rc); + rc = fnet_add_sw(model, net_i, switch_to.y, switch_to.x, + switch_to.set.sw, switch_to.set.len); + if (rc) FAIL(rc); + + // switches inside ologic to ologic routing + switch_to.yx_req = YX_ROUTING_TILE; + switch_to.flags = SWTO_YX_DEF; + switch_to.model = model; + switch_to.y = switch_to.dest_y; + switch_to.x = switch_to.dest_x; + switch_to.start_switch = switch_to.dest_connpt; + switch_to.from_to = SW_TO; + rc = fpga_switch_to_yx(&switch_to); + if (rc) FAIL(rc); + rc = fnet_add_sw(model, net_i, switch_to.y, switch_to.x, + switch_to.set.sw, switch_to.set.len); + if (rc) FAIL(rc); + + // switch inside logic tile + switch_to_rel.model = model; + switch_to_rel.start_y = net_p->el[out_i].y; + switch_to_rel.start_x = net_p->el[out_i].x; + switch_to_rel.start_switch = + out_dev->pinw[net_p->el[out_i].idx & NET_IDX_MASK]; + switch_to_rel.from_to = SW_FROM; + switch_to_rel.rel_y = 0; + switch_to_rel.rel_x = -1; + switch_to_rel.target_connpt = STRIDX_NO_ENTRY; + rc = fpga_switch_to_rel(&switch_to_rel); + if (rc) FAIL(rc); + rc = fnet_add_sw(model, net_i, switch_to_rel.start_y, + switch_to_rel.start_x, switch_to_rel.set.sw, + switch_to_rel.set.len); + if (rc) FAIL(rc); + + // route from logic routing to ilogic routing + rc = froute_direct(model, switch_to_rel.dest_y, + switch_to_rel.dest_x, switch_to_rel.dest_connpt, + switch_to.dest_y, switch_to.dest_x, switch_to.dest_connpt, + &logic_route_set, &iologic_route_set); + if (rc) FAIL(rc); + if (!iologic_route_set.len || !logic_route_set.len) FAIL(EINVAL); + rc = fnet_add_sw(model, net_i, switch_to.dest_y, switch_to.dest_x, + iologic_route_set.sw, iologic_route_set.len); + if (rc) FAIL(rc); + rc = fnet_add_sw(model, net_i, switch_to_rel.dest_y, + switch_to_rel.dest_x, logic_route_set.sw, + logic_route_set.len); + if (rc) FAIL(rc); + return 0; } FAIL(ENOTSUP); @@ -278,75 +279,31 @@ int main(int argc, char** argv) logic_y = 68; logic_x = 13; - logic_type_idx = DEV_LOGM; + logic_type_idx = DEV_LOGX; if ((rc = fdev_logic_set_lut(&model, logic_y, logic_x, logic_type_idx, - LUT_A, 6, "A1*A2", ZTERM))) FAIL(rc); + LUT_D, 6, "A3*A5", ZTERM))) FAIL(rc); if ((rc = fnet_new(&model, &inA_net))) FAIL(rc); if ((rc = fnet_add_port(&model, inA_net, iob_inA_y, iob_inA_x, DEV_IOB, iob_inA_type_idx, IOB_OUT_I))) FAIL(rc); if ((rc = fnet_add_port(&model, inA_net, logic_y, logic_x, DEV_LOGIC, - logic_type_idx, LI_A1))) FAIL(rc); + logic_type_idx, LI_D3))) FAIL(rc); if ((rc = fnet_autoroute(&model, inA_net))) FAIL(rc); if ((rc = fnet_new(&model, &inB_net))) FAIL(rc); if ((rc = fnet_add_port(&model, inB_net, iob_inB_y, iob_inB_x, DEV_IOB, iob_inB_type_idx, IOB_OUT_I))) FAIL(rc); if ((rc = fnet_add_port(&model, inB_net, logic_y, logic_x, DEV_LOGIC, - logic_type_idx, LI_A2))) FAIL(rc); + logic_type_idx, LI_D5))) FAIL(rc); if ((rc = fnet_autoroute(&model, inB_net))) FAIL(rc); if ((rc = fnet_new(&model, &out_net))) FAIL(rc); if ((rc = fnet_add_port(&model, out_net, logic_y, logic_x, DEV_LOGIC, - logic_type_idx, LO_A))) FAIL(rc); + logic_type_idx, LO_D))) FAIL(rc); if ((rc = fnet_add_port(&model, out_net, iob_out_y, iob_out_x, DEV_IOB, iob_out_type_idx, IOB_IN_O))) FAIL(rc); if ((rc = fnet_autoroute(&model, out_net))) FAIL(rc); -#if 0 - switch_to.yx_req = YX_DEV_LOGIC; - switch_to.flags = SWTO_YX_TARGET_CONNPT|SWTO_YX_MAX_SWITCH_DEPTH; - switch_to.model = &model; - switch_to.y = switch_to.dest_y; - switch_to.x = switch_to.dest_x; - switch_to.start_switch = switch_to.dest_connpt; - switch_to.from_to = SW_FROM; - switch_to.max_switch_depth = 1; - { - note: update to constructor - struct sw_chain c = { - .model = &model, .y = switch_to.dest_y, - .x = switch_to.dest_x+1, - .start_switch = logic_dev->pinw[LI_D3], - .from_to = SW_TO, - .max_depth = SW_SET_SIZE, - .block_list = 0 }; - if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL); - if (c.set.len == 0) { HERE(); FAIL(EINVAL); } - switch_to.target_connpt = fpga_switch_str_i(&model, - switch_to.dest_y, switch_to.dest_x+1, - c.set.sw[c.set.len-1], SW_FROM); - } - rc = fpga_switch_to_yx(&switch_to); - if (rc) FAIL(rc); - rc = fnet_add_switches(&model, P46_net, switch_to.y, - switch_to.x, &switch_to.set); - if (rc) FAIL(rc); - { - note: update to constructor - struct sw_chain c = { - .model = &model, .y = switch_to.dest_y, - .x = switch_to.dest_x, - .start_switch = switch_to.dest_connpt, - .from_to = SW_FROM, - .max_depth = SW_SET_SIZE, - .block_list = 0 }; - if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL); - if (c.set.len == 0) { HERE(); FAIL(EINVAL); } - rc = fnet_add_switches(&model, P46_net, c.y, c.x, &c.set); - if (rc) FAIL(rc); - } -#endif if ((rc = write_floorplan(stdout, &model, FP_DEFAULT))) FAIL(rc); return EXIT_SUCCESS; fail: