started modeling left side of chip
This commit is contained in:
Wolfgang Spraul
parent
2bdbea85fb
commit
f69912f094
2
Makefile
2
Makefile
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@ -14,7 +14,7 @@ LDLIBS = -lxml2
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all: bit2txt draw_fpga xc6slx9.svg
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xc6slx9.svg: draw_fpga
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./draw_fpga | xmllint --pretty 1 - > $@
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./draw_fpga --svg | xmllint --pretty 1 - > $@
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bit2txt: bit2txt.o helper.o
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209
draw_fpga.c
209
draw_fpga.c
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@ -8,7 +8,9 @@
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <libxml/tree.h>
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#include <libxml/parser.h>
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@ -40,20 +42,14 @@ enum fpga_tile_type
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BRAM_ROUTING,
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BRAM_ROUTING_BRK,
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BRAM,
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BRAM_ROUTING_T,
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BRAM_ROUTING_TERM_T,
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BRAM_ROUTING_TERM_B,
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BRAM_ROUTING_B,
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BRAM_ROUTING_VIA_T,
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BRAM_ROUTING_VIA_TERM_T,
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BRAM_ROUTING_VIA_TERM_B,
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BRAM_ROUTING_VIA_B,
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BRAM_T,
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BRAM_TERM_LT,
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BRAM_TERM_RT,
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BRAM_TERM_LB,
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BRAM_TERM_RB,
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BRAM_B,
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HCLK_BRAM_ROUTING,
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HCLK_BRAM_ROUTING_VIA,
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HCLK_BRAM,
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@ -107,15 +103,10 @@ enum fpga_tile_type
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IO_BUFPLL_TERM_B,
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IO_LOGIC_REG_TERM_B,
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LOGIC_ROUTING_TERM_B,
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LOGIC_EMPTY_TERM_B,
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MACC_ROUTING_EMPTY_T,
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MACC_ROUTING_EMPTY_B,
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LOGIC_NOIO_TERM_B,
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MACC_ROUTING_TERM_T,
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MACC_ROUTING_TERM_B,
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MACC_VIA_EMPTY,
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MACC_VIA_TERM_T,
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MACC_EMPTY_T,
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MACC_EMPTY_B,
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MACC_TERM_TL,
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MACC_TERM_TR,
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MACC_TERM_BL,
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@ -124,6 +115,19 @@ enum fpga_tile_type
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ROUTING_VIA_IO,
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ROUTING_VIA_IO_DCM,
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ROUTING_VIA_CARRY,
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CORNER_TERM_L,
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IO_TERM_L_UPPER_TOP,
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IO_TERM_L_UPPER_BOT,
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IO_TERM_L_LOWER_TOP,
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IO_TERM_L_LOWER_BOT,
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IO_TERM_L,
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HCLK_TERM_L,
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REGH_IO_TERM_L,
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REG_L,
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IO_PCI_L,
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IO_RDY_L,
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IO_L,
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IO_PCI_CONN_L,
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};
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const char* fpga_ttstr[] = // tile type strings
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@ -145,20 +149,14 @@ const char* fpga_ttstr[] = // tile type strings
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[BRAM_ROUTING] = "BRAM_ROUTING",
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[BRAM_ROUTING_BRK] = "BRAM_ROUTING_BRK",
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[BRAM] = "BRAM",
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[BRAM_ROUTING_T] = "BRAM_ROUTING_T",
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[BRAM_ROUTING_TERM_T] = "BRAM_ROUTING_TERM_T",
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[BRAM_ROUTING_TERM_B] = "BRAM_ROUTING_TERM_B",
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[BRAM_ROUTING_B] = "BRAM_ROUTING_B",
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[BRAM_ROUTING_VIA_T] = "BRAM_ROUTING_VIA_T",
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[BRAM_ROUTING_VIA_TERM_T] = "BRAM_ROUTING_VIA_TERM_T",
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[BRAM_ROUTING_VIA_TERM_B] = "BRAM_ROUTING_VIA_TERM_B",
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[BRAM_ROUTING_VIA_B] = "BRAM_ROUTING_VIA_B",
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[BRAM_T] = "BRAM_T",
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[BRAM_TERM_LT] = "BRAM_TERM_LT",
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[BRAM_TERM_RT] = "BRAM_TERM_RT",
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[BRAM_TERM_LB] = "BRAM_TERM_LB",
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[BRAM_TERM_RB] = "BRAM_TERM_RB",
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[BRAM_B] = "BRAM_B",
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[HCLK_BRAM_ROUTING] = "HCLK_BRAM_ROUTING",
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[HCLK_BRAM_ROUTING_VIA] = "HCLK_BRAM_ROUTING_VIA",
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[HCLK_BRAM] = "HCLK_BRAM",
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@ -212,15 +210,10 @@ const char* fpga_ttstr[] = // tile type strings
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[IO_BUFPLL_TERM_B] = "IO_BUFPLL_TERM_B",
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[IO_LOGIC_REG_TERM_B] = "IO_LOGIC_REG_TERM_B",
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[LOGIC_ROUTING_TERM_B] = "LOGIC_ROUTING_TERM_B",
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[LOGIC_EMPTY_TERM_B] = "LOGIC_EMPTY_TERM_B",
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[MACC_ROUTING_EMPTY_T] = "MACC_ROUTING_EMPTY_T",
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[MACC_ROUTING_EMPTY_B] = "MACC_ROUTING_EMPTY_B",
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[LOGIC_NOIO_TERM_B] = "LOGIC_NOIO_TERM_B",
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[MACC_ROUTING_TERM_T] = "MACC_ROUTING_TERM_T",
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[MACC_ROUTING_TERM_B] = "MACC_ROUTING_TERM_B",
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[MACC_VIA_EMPTY] = "MACC_VIA_EMPTY",
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[MACC_VIA_TERM_T] = "MACC_VIA_TERM_T",
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[MACC_EMPTY_T] = "MACC_EMPTY_T",
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[MACC_EMPTY_B] = "MACC_EMPTY_B",
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[MACC_TERM_TL] = "MACC_TERM_TL",
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[MACC_TERM_TR] = "MACC_TERM_TR",
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[MACC_TERM_BL] = "MACC_TERM_BL",
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@ -229,11 +222,54 @@ const char* fpga_ttstr[] = // tile type strings
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[ROUTING_VIA_IO] = "ROUTING_VIA_IO",
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[ROUTING_VIA_IO_DCM] = "ROUTING_VIA_IO_DCM",
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[ROUTING_VIA_CARRY] = "ROUTING_VIA_CARRY",
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[CORNER_TERM_L] = "CORNER_TERM_L",
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[IO_TERM_L_UPPER_TOP] = "IO_TERM_L_UPPER_TOP",
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[IO_TERM_L_UPPER_BOT] = "IO_TERM_L_UPPER_BOT",
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[IO_TERM_L_LOWER_TOP] = "IO_TERM_L_LOWER_TOP",
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[IO_TERM_L_LOWER_BOT] = "IO_TERM_L_LOWER_BOT",
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[IO_TERM_L] = "IO_TERM_L",
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[HCLK_TERM_L] = "HCLK_TERM_L",
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[REGH_IO_TERM_L] = "REGH_IO_TERM_L",
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[REG_L] = "REG_L",
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[IO_PCI_L] = "IO_PCI_L",
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[IO_RDY_L] = "IO_RDY_L",
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[IO_L] = "IO_L",
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[IO_PCI_CONN_L] = "IO_PCI_CONN_L",
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};
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struct fpga_tile
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{
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enum fpga_tile_type type;
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// expect up to 64 devices per tile
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int num_devices;
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struct fpga_device* devices;
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// expect up to 28k connections to other tiles per tile
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// 3*16 bit per connection:
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// - x coordinate of other tile (16bit)
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// - y coordinate of other tile (16bit)
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// - endpoint index in other tile (16bit)
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int num_conns; // conns array is 3*num_conns 16-bit words
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uint16_t* conns; // num_conns*3 16-bit words: 16(x)-16(y)-16(endpoint)
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// expect up to 5k endpoints per tile
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// 16-bit index into conns (not yet multiplied by 3)
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int num_endpoints;
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uint16_t* endpoints;
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// endpoints0 are conceptual endpoints without outgoing wires.
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// Imagine their indices added to the end of num_endpoints, so
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// the first endpoint0 is at index num_endpoints, the second one
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// at num_endpoints+1, and so on.
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int num_endpoints0;
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// expect up to 4k connection pairs per tile
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// 32bit: 31 off: not in use on: used
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// 30 off: unidirectional on: bidirectional
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// 29:15 from, index into endpoints
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// 14:0 to, index into endpoints
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int num_connect_pairs;
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uint32_t* connect_pairs;
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};
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// columns
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@ -244,35 +280,61 @@ struct fpga_tile
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// 'B' = block ram
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// 'D' = dsp (macc)
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// 'R' = registers and center IO/logic column
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//
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// wiring on the left and right side is described with 16
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// characters for each row - 'W' = wired, 'U' = unwired
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// order is top-down
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#define XC6SLX9_ROWS 4
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#define XC6SLX9_COLUMNS "MLBMLDMRMlMLBML"
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#define XC6SLX9_LEFT_WIRING \
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/* row 3 */ "UWUWUWUW" "WWWWUUUU" \
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/* row 2 */ "UUUUUUUU" "WWWWWWUU" \
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/* row 1 */ "WWWUUWUU" "WUUWUUWU" \
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/* row 0 */ "UWUUWUUW" "UUWWWWUU"
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#define XC6SLX9_RIGHT_WIRING \
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/* row 3 */ "UUWWUWUW" "WWWWUUUU" \
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/* row 2 */ "UUUUUUUU" "WWWWWWUU" \
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/* row 1 */ "WWWUUWUU" "WUUWUUWU" \
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/* row 0 */ "UWUUWUUW" "UUWWWWUU"
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struct fpga_model* build_model(int fpga_rows, const char* columns);
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void printf_model(struct fpga_model* model);
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struct fpga_model* build_model(int fpga_rows, const char* columns,
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const char* left_wiring, const char* right_wiring);
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void print_svg_tiles(struct fpga_model* model);
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void write_folders(struct fpga_model* model, const char* root_folder);
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int main(int argc, char** argv)
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{
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struct fpga_model* model = 0;
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//
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// build memory model
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//
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if (argc < 2) {
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printf("\n"
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"draw_fpga - model and view of an FPGA\n"
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"Public domain work by Wolfgang Spraul\n"
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"\n"
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"draw_fpga [options]\n"
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" --svg writes a simple svg tile grid to stdout\n"
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" --folder <path> writes a folder structure of tiles and devices\n"
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"\n");
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return EXIT_SUCCESS;
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}
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model = build_model(XC6SLX9_ROWS, XC6SLX9_COLUMNS);
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model = build_model(XC6SLX9_ROWS, XC6SLX9_COLUMNS,
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XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING);
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if (!model) goto fail;
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//
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// write svg
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//
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if (!strcmp(argv[1], "--svg"))
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print_svg_tiles(model);
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if (!strcmp(argv[1], "--folder"))
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write_folders(model, argv[2]);
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printf_model(model);
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return EXIT_SUCCESS;
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fail:
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return EXIT_FAILURE;
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}
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struct fpga_model* build_model(int fpga_rows, const char* columns)
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struct fpga_model* build_model(int fpga_rows, const char* columns,
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const char* left_wiring, const char* right_wiring)
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{
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int tile_rows, tile_columns, i, j, k, l, row_top_y, center_row, left_side;
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int start, end;
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@ -304,9 +366,15 @@ struct fpga_model* build_model(int fpga_rows, const char* columns)
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model->tiles[i].type = NA;
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if (!(tile_rows % 2))
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fprintf(stderr, "Unexpected even number of tile rows (%i).\n", tile_rows);
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i = 5; // left IO columns
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center_row = 2 /* top IO files */ + (fpga_rows/2)*(8+1/*middle of row clock*/+8);
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//
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// top, bottom, center:
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// go through columns from left to right, rows from top to bottom
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//
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left_side = 1; // turn off (=right side) when reaching the 'R' middle column
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i = 5; // skip left IO columns
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for (j = 0; columns[j]; j++) {
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switch (columns[j]) {
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case 'L':
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@ -360,7 +428,7 @@ struct fpga_model* build_model(int fpga_rows, const char* columns)
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if (columns[j] == 'L' || columns[j] == 'M')
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model->tiles[(tile_rows-2)*tile_columns + i + 1].type = IO_LOGIC_TERM_B;
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else
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model->tiles[(tile_rows-2)*tile_columns + i + 1].type = LOGIC_EMPTY_TERM_B;
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model->tiles[(tile_rows-2)*tile_columns + i + 1].type = LOGIC_NOIO_TERM_B;
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}
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if (columns[j] == 'L' || columns[j] == 'M') {
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model->tiles[2*tile_columns + i + 1].type = IO_OUTER_T;
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@ -393,18 +461,12 @@ struct fpga_model* build_model(int fpga_rows, const char* columns)
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model->tiles[(row_top_y+8)*tile_columns + i + 2].type = HCLK_BRAM;
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}
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model->tiles[i].type = BRAM_ROUTING_T;
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model->tiles[tile_columns + i].type = BRAM_ROUTING_TERM_T;
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model->tiles[(tile_rows-2)*tile_columns + i].type = BRAM_ROUTING_TERM_B;
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model->tiles[(tile_rows-1)*tile_columns + i].type = BRAM_ROUTING_B;
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model->tiles[i + 1].type = BRAM_ROUTING_VIA_T;
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model->tiles[tile_columns + i + 1].type = BRAM_ROUTING_VIA_TERM_T;
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model->tiles[(tile_rows-2)*tile_columns + i + 1].type = BRAM_ROUTING_VIA_TERM_B;
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model->tiles[(tile_rows-1)*tile_columns + i + 1].type = BRAM_ROUTING_VIA_B;
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model->tiles[i + 2].type = BRAM_T;
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model->tiles[tile_columns + i + 2].type = left_side ? BRAM_TERM_LT : BRAM_TERM_RT;
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model->tiles[(tile_rows-2)*tile_columns + i + 2].type = left_side ? BRAM_TERM_LB : BRAM_TERM_RB;
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model->tiles[(tile_rows-1)*tile_columns + i + 2].type = BRAM_B;
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model->tiles[center_row*tile_columns + i].type = REGH_BRAM_ROUTING;
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model->tiles[center_row*tile_columns + i + 1].type = REGH_BRAM_ROUTING_VIA;
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@ -426,18 +488,12 @@ struct fpga_model* build_model(int fpga_rows, const char* columns)
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model->tiles[(row_top_y+8)*tile_columns + i + 2].type = HCLK_MACC;
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}
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model->tiles[i].type = MACC_ROUTING_EMPTY_T;
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model->tiles[tile_columns + i].type = MACC_ROUTING_TERM_T;
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model->tiles[(tile_rows-2)*tile_columns + i].type = MACC_ROUTING_TERM_B;
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model->tiles[(tile_rows-1)*tile_columns + i].type = MACC_ROUTING_EMPTY_B;
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model->tiles[i + 1].type = MACC_VIA_EMPTY;
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model->tiles[tile_columns + i + 1].type = MACC_VIA_TERM_T;
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model->tiles[(tile_rows-2)*tile_columns + i + 1].type = IO_LOGIC_TERM_B;
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model->tiles[(tile_rows-1)*tile_columns + i + 1].type = MACC_VIA_EMPTY;
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model->tiles[i + 2].type = MACC_EMPTY_T;
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model->tiles[tile_columns + i + 2].type = left_side ? MACC_TERM_TL : MACC_TERM_TR;
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model->tiles[(tile_rows-2)*tile_columns + i + 2].type = left_side ? MACC_TERM_BL : MACC_TERM_BR;
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model->tiles[(tile_rows-1)*tile_columns + i + 2].type = MACC_EMPTY_B;
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model->tiles[center_row*tile_columns + i].type = REGH_MACC_ROUTING;
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model->tiles[center_row*tile_columns + i + 1].type = REGH_MACC_ROUTING_VIA;
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@ -502,7 +558,6 @@ struct fpga_model* build_model(int fpga_rows, const char* columns)
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model->tiles[(row_top_y+8)*tile_columns + i + 1].type = HCLK_LOGIC_XL;
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model->tiles[(row_top_y+8)*tile_columns + i + 3].type = HCLK_REGV;
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}
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model->tiles[i].type = IO_T;
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model->tiles[(tile_rows-1)*tile_columns + i].type = IO_B;
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model->tiles[tile_columns + i].type = IO_TERM_T;
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@ -537,10 +592,48 @@ struct fpga_model* build_model(int fpga_rows, const char* columns)
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break;
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}
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}
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//
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// left IO
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//
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for (k = fpga_rows-1; k >= 0; k--) {
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row_top_y = 2 /* top IO tiles */ + (fpga_rows-1-k)*(8+1/*middle of row clock*/+8);
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if (k<(fpga_rows/2)) row_top_y++; // middle system tiles
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for (l = 0; l < 16; l++) {
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if (left_wiring[(fpga_rows-1-k)*16+l] == 'W')
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns].type = IO_L;
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if ((k == fpga_rows-1 && !l) || (!k && l==15))
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + 1].type = CORNER_TERM_L;
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else if (k == fpga_rows/2 && l == 12)
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model->tiles[(row_top_y+l+1)*tile_columns + 1].type = IO_TERM_L_UPPER_TOP;
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else if (k == fpga_rows/2 && l == 13)
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model->tiles[(row_top_y+l+1)*tile_columns + 1].type = IO_TERM_L_UPPER_BOT;
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else if (k == (fpga_rows/2)-1 && !l)
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model->tiles[(row_top_y+l)*tile_columns + 1].type = IO_TERM_L_LOWER_TOP;
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else if (k == (fpga_rows/2)-1 && l == 1)
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model->tiles[(row_top_y+l)*tile_columns + 1].type = IO_TERM_L_LOWER_BOT;
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else
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||||
model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + 1].type = IO_TERM_L;
|
||||
}
|
||||
model->tiles[(row_top_y+8)*tile_columns + 1].type = HCLK_TERM_L;
|
||||
}
|
||||
|
||||
model->tiles[(center_row-3)*tile_columns].type = IO_PCI_L;
|
||||
model->tiles[(center_row-2)*tile_columns].type = IO_PCI_CONN_L;
|
||||
model->tiles[(center_row-1)*tile_columns].type = IO_PCI_CONN_L;
|
||||
model->tiles[center_row*tile_columns].type = REG_L;
|
||||
model->tiles[center_row*tile_columns + 1].type = REGH_IO_TERM_L;
|
||||
model->tiles[(center_row+1)*tile_columns].type = IO_RDY_L;
|
||||
|
||||
//
|
||||
// right IO
|
||||
//
|
||||
return model;
|
||||
}
|
||||
|
||||
void printf_model(struct fpga_model* model)
|
||||
void print_svg_tiles(struct fpga_model* model)
|
||||
{
|
||||
static const xmlChar* empty_svg = (const xmlChar*)
|
||||
"<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n"
|
||||
|
|
@ -614,3 +707,17 @@ fail:
|
|||
if (doc) xmlFreeDoc(doc);
|
||||
xmlCleanupParser();
|
||||
}
|
||||
|
||||
void write_folders(struct fpga_model* model, const char* root_folder)
|
||||
{
|
||||
char path[1024];
|
||||
|
||||
sprintf(path, "%s/devices", root_folder);
|
||||
if (mkdir(path, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH)) {
|
||||
fprintf(stderr, "Cannot create folder %s\n", path);
|
||||
return;
|
||||
}
|
||||
|
||||
// root/devices/IOB
|
||||
// root/tile_type/1file_per_tile
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user