From f7ada88c59ebf49ebdec84c9e5670955a150645e Mon Sep 17 00:00:00 2001 From: Wolfgang Spraul Date: Fri, 27 Jul 2012 03:31:30 +0200 Subject: [PATCH] some dcm and pll wiring --- model.c | 43 +++++++++++++++++++++++++++++++++++++++++-- model.h | 2 ++ 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/model.c b/model.c index 2f78ef0..28d46d6 100644 --- a/model.c +++ b/model.c @@ -489,6 +489,42 @@ int run_wires(struct fpga_model* model) } } } + if (tile->flags & TF_CENTER) { + if (tile[2].flags & (TF_PLL_DEV|TF_DCM_DEV)) { + const char* prefix = (tile[2].flags & TF_PLL_DEV) ? "PLL_CLB2" : "DCM_CLB2"; + + for (i = 0;; i = 2) { + if ((rc = add_conn_range(model, NOPREF_BI_F, y+i, x, "LOGICIN_B%i", 0, 3, y+i, x+1, "INT_INTERFACE_LOGICBIN%i", 0))) goto xout; + if ((rc = add_conn_bi(model, y+i, x, "INT_IOI_LOGICIN_B4", y+i, x+1, "INT_INTERFACE_IOI_LOGICBIN4"))) goto xout; + if ((rc = add_conn_range(model, NOPREF_BI_F, y+i, x, "LOGICIN_B%i", 5, 9, y+i, x+1, "INT_INTERFACE_LOGICBIN%i", 5))) goto xout; + if ((rc = add_conn_bi(model, y+i, x, "INT_IOI_LOGICIN_B10", y+i, x+1, "INT_INTERFACE_IOI_LOGICBIN10"))) goto xout; + if ((rc = add_conn_range(model, NOPREF_BI_F, y+i, x, "LOGICIN_B%i", 11, 62, y+i, x+1, "INT_INTERFACE_LOGICBIN%i", 11))) goto xout; + + if ((rc = add_conn_range(model, NOPREF_BI_F, y+i, x, "LOGICIN_B%i", 0, 3, y, x+2, pf("%s_LOGICINB%%i", prefix), 0))) goto xout; + if ((rc = add_conn_bi(model, y+i, x, "INT_IOI_LOGICIN_B4", y, x+2, pf("%s_LOGICINB4", prefix)))) goto xout; + if ((rc = add_conn_range(model, NOPREF_BI_F, y+i, x, "LOGICIN_B%i", 5, 9, y, x+2, pf("%s_LOGICINB%%i", prefix), 5))) goto xout; + if ((rc = add_conn_bi(model, y+i, x, "INT_IOI_LOGICIN_B10", y, x+2, pf("%s_LOGICINB10", prefix)))) goto xout; + if ((rc = add_conn_range(model, NOPREF_BI_F, y+i, x, "LOGICIN_B%i", 11, 62, y, x+2, pf("%s_LOGICINB%%i", prefix), 11))) goto xout; + + if (tile[2].flags & TF_PLL_DEV) { + if ((rc = add_conn_range(model, NOPREF_BI_F, y+2, x, "LOGICIN_B%i", 0, 62, y+2, x+1, "INT_INTERFACE_LOGICBIN%i", 0))) goto xout; + if ((rc = add_conn_range(model, NOPREF_BI_F, y+2, x, "LOGICIN_B%i", 0, 62, y, x+2, "PLL_CLB1_LOGICINB%i", 0))) goto xout; + break; + } + if (i == 2) break; + prefix = "DCM_CLB1"; + } + } + if (tile_dn1->flags & TF_CHIP_HORIZ_AXSYMM_CENTER) { + if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICIN_B%i", 0, 62, y, x+1, "INT_INTERFACE_REGC_LOGICBIN%i", 0))) goto xout; + int clk_pins[16] = { 24, 15, 7, 42, 5, 12, 62, 16, 47, 20, 38, 23, 48, 57, 44, 4 }; + for (i = 0; i <= 15; i++) { + if ((rc = add_conn_bi(model, y, x, pf("LOGICIN_B%i", clk_pins[i]), y+1, x+1, pf("REGC_CLE_SEL%i", i)))) goto xout; + if ((rc = add_conn_bi(model, y, x, pf("LOGICIN_B%i", clk_pins[i]), y+1, x+2, pf("REGC_CMT_SEL%i", i)))) goto xout; + if ((rc = add_conn_bi(model, y, x, pf("LOGICIN_B%i", clk_pins[i]), y+1, x+3, pf("CLKC_SEL%i_PLL", i)))) goto xout; + } + } + } } // NR1 @@ -937,10 +973,13 @@ int init_tiles(struct fpga_model* model) } if (l == 7) { - if (k%2) // odd + if (k%2) { // odd + model->tiles[(row_top_y+l)*tile_columns + i + 2].flags |= TF_PLL_DEV; model->tiles[(row_top_y+l)*tile_columns + i + 2].type = (k<(model->cfg_rows/2)) ? PLL_B : PLL_T; - else // even + } else { // even + model->tiles[(row_top_y+l)*tile_columns + i + 2].flags |= TF_DCM_DEV; model->tiles[(row_top_y+l)*tile_columns + i + 2].type = (k<(model->cfg_rows/2)) ? DCM_B : DCM_T; + } } // four midbuf tiles, in the middle of the top and bottom halves if (l == 15) { diff --git a/model.h b/model.h index 7e9e83f..0df66c7 100644 --- a/model.h +++ b/model.h @@ -144,6 +144,8 @@ enum fpga_tile_type #define TF_LOGIC_XL_DEVICE 0x00080000 #define TF_LOGIC_XM_DEVICE 0x00100000 #define TF_IOLOGIC_DELAY_DEV 0x00200000 +#define TF_DCM_DEV 0x00400000 +#define TF_PLL_DEV 0x00800000 #define SWITCH_BIDIRECTIONAL 0x40000000