working on C model
This commit is contained in:
Wolfgang Spraul
parent
1582b4833c
commit
f99572195a
5
Makefile
5
Makefile
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@ -11,7 +11,10 @@ CFLAGS = -Wall -g
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#OBJS = $(TARGETS:=.o)
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LDLIBS = -lxml2
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all: bit2txt draw_fpga
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all: bit2txt draw_fpga xc6slx9.svg
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xc6slx9.svg: draw_fpga
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./draw_fpga | xmllint --pretty 1 - > $@
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bit2txt: bit2txt.o helper.o
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341
draw_fpga.c
341
draw_fpga.c
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@ -23,11 +23,106 @@ struct fpga_model
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enum fpga_tile_type
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{
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NULL_T,
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NA,
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ROUTING,
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ROUTING_BRK,
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ROUTING_VIA,
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HCLK_ROUTING_XM,
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HCLK_ROUTING_XL,
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HCLK_LOGIC_XM,
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HCLK_LOGIC_XL,
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LOGIC_XM,
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LOGIC_XL,
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REGH_ROUTING_XM,
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REGH_ROUTING_XL,
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REGH_LOGIC_XM,
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REGH_LOGIC_XL,
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BRAM_ROUTING,
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BRAM_ROUTING_BRK,
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BRAM,
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HCLK_BRAM_ROUTING,
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HCLK_BRAM_ROUTING_VIA,
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HCLK_BRAM,
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REGH_BRAM_ROUTING,
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REGH_BRAM_ROUTING_VIA,
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REGH_BRAM_L,
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REGH_BRAM_R,
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MACC,
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HCLK_MACC_ROUTING,
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HCLK_MACC_ROUTING_VIA,
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HCLK_MACC,
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REGH_MACC_ROUTING,
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REGH_MACC_ROUTING_VIA,
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REGH_MACC_L,
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PLL_T,
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DCM_T,
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PLL_B,
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DCM_B,
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HCLK_REG_V,
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REG_V,
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REG_V_BRK,
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REG_V_TOP,
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REG_V_BOTTOM,
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REG_V_MIDBUF_TOP,
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REG_V_HCLKBUF_TOP,
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REG_V_HCLKBUF_BOTTOM,
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REG_V_MIDBUF_BOTTOM,
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REGC_ROUTING,
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REGC_LOGIC,
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REGC_CMT,
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CENTER, // unique center tile in the middle of the chip
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};
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const char* fpga_ttstr[] = // tile type strings
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{
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[NA] = "NA",
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[ROUTING] = "ROUTING",
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[ROUTING_BRK] = "ROUTING_BRK",
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[ROUTING_VIA] = "ROUTING_VIA",
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[HCLK_ROUTING_XM] = "HCLK_ROUTING_XM",
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[HCLK_ROUTING_XL] = "HCLK_ROUTING_XL",
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[HCLK_LOGIC_XM] = "HCLK_LOGIC_XM",
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[HCLK_LOGIC_XL] = "HCLK_LOGIC_XL",
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[LOGIC_XM] = "LOGIC_XM",
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[LOGIC_XL] = "LOGIC_XL",
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[REGH_ROUTING_XM] = "REGH_ROUTING_XM",
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[REGH_ROUTING_XL] = "REGH_ROUTING_XL",
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[REGH_LOGIC_XM] = "REGH_LOGIC_XM",
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[REGH_LOGIC_XL] = "REGH_LOGIC_XL",
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[BRAM_ROUTING] = "BRAM_ROUTING",
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[BRAM_ROUTING_BRK] = "BRAM_ROUTING_BRK",
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[BRAM] = "BRAM",
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[HCLK_BRAM_ROUTING] = "HCLK_BRAM_ROUTING",
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[HCLK_BRAM_ROUTING_VIA] = "HCLK_BRAM_ROUTING_VIA",
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[HCLK_BRAM] = "HCLK_BRAM",
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[REGH_BRAM_ROUTING] = "REGH_BRAM_ROUTING",
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[REGH_BRAM_ROUTING_VIA] = "REGH_BRAM_ROUTING_VIA",
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[REGH_BRAM_L] = "REGH_BRAM_L",
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[REGH_BRAM_R] = "REGH_BRAM_R",
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[MACC] = "MACC",
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[HCLK_MACC_ROUTING] = "HCLK_MACC_ROUTING",
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[HCLK_MACC_ROUTING_VIA] = "HCLK_MACC_ROUTING_VIA",
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[HCLK_MACC] = "HCLK_MACC",
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[REGH_MACC_ROUTING] = "REGH_MACC_ROUTING",
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[REGH_MACC_ROUTING_VIA] = "REGH_MACC_ROUTING_VIA",
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[REGH_MACC_L] = "REGH_MACC_L",
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[PLL_T] = "PLL_T",
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[DCM_T] = "DCM_T",
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[PLL_B] = "PLL_B",
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[DCM_B] = "DCM_B",
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[HCLK_REG_V] = "HCLK_REG_V",
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[REG_V] = "REG_V",
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[REG_V_BRK] = "REG_V_BRK",
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[REG_V_TOP] = "REG_V_TOP",
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[REG_V_BOTTOM] = "REG_V_BOTTOM",
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[REG_V_MIDBUF_TOP] = "REG_V_MIDBUF_TOP",
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[REG_V_HCLKBUF_TOP] = "REG_V_HCLKBUF_TOP",
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[REG_V_HCLKBUF_BOTTOM] = "REG_V_HCLKBUF_BOTTOM",
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[REG_V_MIDBUF_BOTTOM] = "REG_V_MIDBUF_BOTTOM",
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[REGC_ROUTING] = "REGC_ROUTING",
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[REGC_LOGIC] = "REGC_LOGIC",
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[REGC_CMT] = "REGC_CMT",
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[CENTER] = "CENTER",
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};
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struct fpga_tile
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@ -35,40 +130,18 @@ struct fpga_tile
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enum fpga_tile_type type;
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};
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struct fpga_model* build_model(int rows, const char* columns)
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{
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int tile_rows, tile_columns, i;
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tile_rows = 1 /* middle */ + (8+1+8)*rows
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+ 2+2 /* two extra tiles at top and bottom */;
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tile_columns = 5 /* left */ + 2 /* middle regs */ + 5 /* right */;
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for (i = 0; columns[i] != 0; i++) {
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tile_columns += 2; // 2 for logic blocks L/M or middle regs
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if (columns[i] == 'B' || columns[i] == 'D')
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tile_columns++; // 3 for bram or macc
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}
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return 0;
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}
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// columns
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// 'L' = X+L logic block
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// 'M' = X+M logic block
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// 'B' = block ram
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// 'D' = dsp (macc)
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// 'R' = registers (middle)
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// 'R' = registers and center IO/logic column
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#define XC6SLX9_ROWS 4
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#define XC6SLX9_COLUMNS "MLBMLDMLRMLMLBML"
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#define XC6SLX9_COLUMNS "MLBMLDMRMLMLBML"
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static const xmlChar* empty_svg = (const xmlChar*)
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"<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n"
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"<svg\n"
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" version=\"2.0\"\n"
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" xmlns=\"http://www.w3.org/2000/svg\"\n"
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" xmlns:xlink=\"http://www.w3.org/1999/xlink\"\n"
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" width=\"1000\" height=\"1000\"\n"
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" id=\"root\">\n"
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"</svg>\n";
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struct fpga_model* build_model(int fpga_rows, const char* columns);
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void printf_model(struct fpga_model* model);
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int main(int argc, char** argv)
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{
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@ -78,72 +151,238 @@ int main(int argc, char** argv)
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// build memory model
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//
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// build_model(XC6SLX9_ROWS, XC6SLX9_COLUMNS);
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model = build_model(XC6SLX9_ROWS, XC6SLX9_COLUMNS);
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if (!model) goto fail;
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//
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// write svg
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//
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// can't get indent formatting to work - use 'xmllint --pretty 1 -'
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// on the output for now
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printf_model(model);
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return EXIT_SUCCESS;
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fail:
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return EXIT_FAILURE;
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}
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struct fpga_model* build_model(int fpga_rows, const char* columns)
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{
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int tile_rows, tile_columns, i, j, k, l, row_top_y, center_row, left_side;
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struct fpga_model* model;
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tile_rows = 1 /* middle */ + (8+1+8)*fpga_rows + 2+2 /* two extra tiles at top and bottom */;
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tile_columns = 5 /* left */ + 5 /* right */;
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for (i = 0; columns[i] != 0; i++) {
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tile_columns += 2; // 2 for logic blocks L/M and minimum for others
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if (columns[i] == 'B' || columns[i] == 'D')
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tile_columns++; // 3 for bram or macc
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else if (columns[i] == 'R')
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tile_columns+=2; // 2+2 for middle IO+logic+PLL/DCM
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}
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model = calloc(1 /* nelem */, sizeof(struct fpga_model));
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if (!model) {
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fprintf(stderr, "%i: Out of memory.\n", __LINE__);
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return 0;
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}
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model->tile_x_range = tile_columns;
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model->tile_y_range = tile_rows;
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model->tiles = calloc(tile_columns * tile_rows, sizeof(struct fpga_tile));
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if (!model->tiles) {
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fprintf(stderr, "%i: Out of memory.\n", __LINE__);
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free(model);
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return 0;
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}
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for (i = 0; i < tile_rows * tile_columns; i++)
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model->tiles[i].type = NA;
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if (!(tile_rows % 2))
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fprintf(stderr, "Unexpected even number of tile rows (%i).\n", tile_rows);
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i = 5; // left IO columns
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center_row = 2 /* top IO files */ + (fpga_rows/2)*(8+1/*middle of row clock*/+8);
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left_side = 1; // turn off (=right side) when reaching the 'R' middle column
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for (j = 0; columns[j]; j++) {
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switch (columns[j]) {
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case 'L':
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case 'M':
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for (k = fpga_rows-1; k >= 0; k--) {
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row_top_y = 2 /* top IO tiles */ + (fpga_rows-1-k)*(8+1/*middle of row clock*/+8);
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if (k<(fpga_rows/2)) row_top_y++; // middle system tiles (center row)
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for (l = ((k == fpga_rows-1) ? 2 : 0); l < ((k > 0) ? 16 : 14); l++) {
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i].type = (l < 15) ? ROUTING : ROUTING_BRK;
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i + 1].type
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= (columns[j] == 'L') ? LOGIC_XL : LOGIC_XM;
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}
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if (columns[j] == 'L') {
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model->tiles[(row_top_y+8)*tile_columns + i].type = HCLK_ROUTING_XL;
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model->tiles[(row_top_y+8)*tile_columns + i + 1].type = HCLK_LOGIC_XL;
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} else {
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model->tiles[(row_top_y+8)*tile_columns + i].type = HCLK_ROUTING_XM;
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model->tiles[(row_top_y+8)*tile_columns + i + 1].type = HCLK_LOGIC_XM;
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}
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}
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if (columns[j] == 'L') {
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model->tiles[center_row*tile_columns + i].type = REGH_ROUTING_XL;
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model->tiles[center_row*tile_columns + i + 1].type = REGH_LOGIC_XL;
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} else {
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model->tiles[center_row*tile_columns + i].type = REGH_ROUTING_XM;
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model->tiles[center_row*tile_columns + i + 1].type = REGH_LOGIC_XM;
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}
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i += 2;
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break;
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case 'B':
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for (k = fpga_rows-1; k >= 0; k--) {
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row_top_y = 2 /* top IO tiles */ + (fpga_rows-1-k)*(8+1/*middle of row clock*/+8);
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if (k<(fpga_rows/2)) row_top_y++; // middle system tiles
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for (l = 0; l < 16; l++) {
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i].type = (l < 15) ? BRAM_ROUTING : BRAM_ROUTING_BRK;
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i + 1].type = ROUTING_VIA;
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if (!(l%4))
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model->tiles[(row_top_y+3+(l<8?l:l+1))*tile_columns + i + 2].type = BRAM;
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}
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model->tiles[(row_top_y+8)*tile_columns + i].type = HCLK_BRAM_ROUTING;
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model->tiles[(row_top_y+8)*tile_columns + i + 1].type = HCLK_BRAM_ROUTING_VIA;
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model->tiles[(row_top_y+8)*tile_columns + i + 2].type = HCLK_BRAM;
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}
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model->tiles[center_row*tile_columns + i].type = REGH_BRAM_ROUTING;
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model->tiles[center_row*tile_columns + i + 1].type = REGH_BRAM_ROUTING_VIA;
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model->tiles[center_row*tile_columns + i + 2].type = left_side ? REGH_BRAM_L : REGH_BRAM_R;
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i += 3;
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break;
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case 'D':
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for (k = fpga_rows-1; k >= 0; k--) {
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row_top_y = 2 /* top IO tiles */ + (fpga_rows-1-k)*(8+1/*middle of row clock*/+8);
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if (k<(fpga_rows/2)) row_top_y++; // middle system tiles
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for (l = 0; l < 16; l++) {
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i].type = (l < 15) ? ROUTING : ROUTING_BRK;
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i + 1].type = ROUTING_VIA;
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if (!(l%4))
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model->tiles[(row_top_y+3+(l<8?l:l+1))*tile_columns + i + 2].type = MACC;
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}
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model->tiles[(row_top_y+8)*tile_columns + i].type = HCLK_MACC_ROUTING;
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model->tiles[(row_top_y+8)*tile_columns + i + 1].type = HCLK_MACC_ROUTING_VIA;
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model->tiles[(row_top_y+8)*tile_columns + i + 2].type = HCLK_MACC;
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}
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model->tiles[center_row*tile_columns + i].type = REGH_MACC_ROUTING;
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model->tiles[center_row*tile_columns + i + 1].type = REGH_MACC_ROUTING_VIA;
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model->tiles[center_row*tile_columns + i + 2].type = REGH_MACC_L;
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i += 3;
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break;
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case 'R':
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left_side = 0;
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for (k = fpga_rows-1; k >= 0; k--) {
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row_top_y = 2 /* top IO tiles */ + (fpga_rows-1-k)*(8+1/*middle of row clock*/+8);
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if (k<(fpga_rows/2)) row_top_y++; // middle system tiles
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for (l = 0; l < 16; l++) {
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if (l == 7) {
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if (k%2) // odd
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model->tiles[(row_top_y+l)*tile_columns + i + 2].type = (k<(fpga_rows/2)) ? PLL_B : PLL_T;
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else // even
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model->tiles[(row_top_y+l)*tile_columns + i + 2].type = (k<(fpga_rows/2)) ? DCM_B : DCM_T;
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}
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// four midbuf tiles, in the middle of the top and bottom halves
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if (l == 15) {
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if (k == fpga_rows*3/4)
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model->tiles[(row_top_y+l+1)*tile_columns + i + 3].type = REG_V_MIDBUF_TOP;
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else if (k == fpga_rows/4)
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model->tiles[(row_top_y+l+1)*tile_columns + i + 3].type = REG_V_HCLKBUF_BOTTOM;
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else
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model->tiles[(row_top_y+l+1)*tile_columns + i + 3].type = REG_V_BRK;
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} else if (l == 0 && k == fpga_rows*3/4-1) {
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model->tiles[(row_top_y+l)*tile_columns + i + 3].type = REG_V_HCLKBUF_TOP;
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} else if (l == 0 && k == fpga_rows/4-1) {
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model->tiles[(row_top_y+l)*tile_columns + i + 3].type = REG_V_MIDBUF_BOTTOM;
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} else if (l == 8) {
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model->tiles[(row_top_y+l+1)*tile_columns + i + 3].type = (k<fpga_rows/2) ? REG_V_BOTTOM : REG_V_TOP;
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} else
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model->tiles[(row_top_y+(l<8?l:l+1))*tile_columns + i + 3].type = REG_V;
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}
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model->tiles[(row_top_y+8)*tile_columns + i].type = HCLK_ROUTING_XL;
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model->tiles[(row_top_y+8)*tile_columns + i + 1].type = HCLK_LOGIC_XL;
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model->tiles[(row_top_y+8)*tile_columns + i + 3].type = HCLK_REG_V;
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}
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model->tiles[center_row*tile_columns + i].type = REGC_ROUTING;
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model->tiles[center_row*tile_columns + i + 1].type = REGC_LOGIC;
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model->tiles[center_row*tile_columns + i + 2].type = REGC_CMT;
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model->tiles[center_row*tile_columns + i + 3].type = CENTER;
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i += 4;
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break;
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default:
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fprintf(stderr, "Unexpected column identifier '%c'\n", columns[i]);
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break;
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}
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}
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return model;
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}
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void printf_model(struct fpga_model* model)
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{
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static const xmlChar* empty_svg = (const xmlChar*)
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"<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n"
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"<svg version=\"2.0\"\n"
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" xmlns=\"http://www.w3.org/2000/svg\"\n"
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" xmlns:xlink=\"http://www.w3.org/1999/xlink\"\n"
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" xmlns:fpga=\"http://qi-hw.com/fpga\"\n"
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" id=\"root\">\n"
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"<style type=\"text/css\"><![CDATA[text{font-size:6pt;text-anchor:end;}]]></style>\n"
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"</svg>\n";
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xmlDocPtr doc = 0;
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xmlXPathContextPtr xpathCtx = 0;
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xmlXPathObjectPtr xpathObj = 0;
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xmlNodePtr new_node;
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char str[128];
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int i, j;
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// can't get indent formatting to work - use 'xmllint --pretty 1 -'
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// on the output for now
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xmlInitParser();
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doc = xmlParseDoc(empty_svg);
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if (!doc) {
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fprintf(stderr, "Internal error %i.\n", __LINE__);
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goto fail_xml;
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goto fail;
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}
|
||||
xpathCtx = xmlXPathNewContext(doc);
|
||||
if (!xpathCtx) {
|
||||
fprintf(stderr, "Cannot create XPath context.\n");
|
||||
goto fail_xml;
|
||||
goto fail;
|
||||
}
|
||||
xmlXPathRegisterNs(xpathCtx, BAD_CAST "svg", BAD_CAST "http://www.w3.org/2000/svg");
|
||||
xpathObj = xmlXPathEvalExpression(BAD_CAST "//svg:*[@id='root']", xpathCtx);
|
||||
if (!xpathObj) {
|
||||
fprintf(stderr, "Cannot evaluate root expression.\n");
|
||||
goto fail_xml;
|
||||
goto fail;
|
||||
}
|
||||
if (!xpathObj->nodesetval) {
|
||||
fprintf(stderr, "Cannot find root node.\n");
|
||||
goto fail_xml;
|
||||
goto fail;
|
||||
}
|
||||
if (xpathObj->nodesetval->nodeNr != 1) {
|
||||
fprintf(stderr, "Found %i root nodes.\n", xpathObj->nodesetval->nodeNr);
|
||||
goto fail_xml;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
{
|
||||
xmlNodePtr new_node;
|
||||
int i;
|
||||
|
||||
//<text x="6900" y="1058">NULL</text>
|
||||
for (i = 0; i < 10; i++) {
|
||||
new_node = xmlNewChild(xpathObj->nodesetval->nodeTab[0], 0 /* xmlNsPtr */, BAD_CAST "use", 0 /* content */);
|
||||
xmlSetProp(new_node, BAD_CAST "xlink:href", BAD_CAST "lib.svg#IOB");
|
||||
xmlSetProp(new_node, BAD_CAST "x", xmlXPathCastNumberToString(50+i*50));
|
||||
xmlSetProp(new_node, BAD_CAST "y", BAD_CAST "50");
|
||||
xmlSetProp(new_node, BAD_CAST "width", BAD_CAST "50");
|
||||
xmlSetProp(new_node, BAD_CAST "height", BAD_CAST "50");
|
||||
for (i = 0; i < model->tile_y_range; i++) {
|
||||
for (j = 0; j < model->tile_x_range; j++) {
|
||||
strcpy(str, fpga_ttstr[model->tiles[i*model->tile_x_range+j].type]);
|
||||
new_node = xmlNewChild(xpathObj->nodesetval->nodeTab[0], 0 /* xmlNsPtr */, BAD_CAST "text", BAD_CAST str);
|
||||
xmlSetProp(new_node, BAD_CAST "x", xmlXPathCastNumberToString(130 + j*130));
|
||||
xmlSetProp(new_node, BAD_CAST "y", xmlXPathCastNumberToString(40 + i*20));
|
||||
xmlSetProp(new_node, BAD_CAST "fpga:tile_y", BAD_CAST xmlXPathCastNumberToString(i));
|
||||
xmlSetProp(new_node, BAD_CAST "fpga:tile_x", BAD_CAST xmlXPathCastNumberToString(j));
|
||||
}
|
||||
}
|
||||
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "width", BAD_CAST xmlXPathCastNumberToString(model->tile_x_range * 130 + 65));
|
||||
xmlSetProp(xpathObj->nodesetval->nodeTab[0], BAD_CAST "height", BAD_CAST xmlXPathCastNumberToString(model->tile_y_range * 20 + 60));
|
||||
|
||||
xmlDocFormatDump(stdout, doc, 1 /* format */);
|
||||
|
||||
xmlXPathFreeObject(xpathObj);
|
||||
xmlXPathFreeContext(xpathCtx);
|
||||
xmlFreeDoc(doc);
|
||||
xmlCleanupParser();
|
||||
return EXIT_SUCCESS;
|
||||
return;
|
||||
|
||||
fail_xml:
|
||||
fail:
|
||||
if (xpathObj) xmlXPathFreeObject(xpathObj);
|
||||
if (xpathCtx) xmlXPathFreeContext(xpathCtx);
|
||||
if (doc) xmlFreeDoc(doc);
|
||||
xmlCleanupParser();
|
||||
return EXIT_FAILURE;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user