184 lines
6.6 KiB
C
184 lines
6.6 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include "model.h"
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#include "floorplan.h"
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#include "control.h"
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/*
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This C design corresponds to the following Verilog:
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module blinking(input clk, output led);
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// synthesis attribute LOC clk "T8 | IOSTANDARD = LVCMOS33"
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// synthesis attribute LOC led "R5 | SLEW = QUIETIO | DRIVE = 8"
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// COUNTER_SIZE tested as 14 (32K crystal) and 23 (20M crystal)
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`define COUNTER_SIZE 23
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reg [`COUNTER_SIZE:0] counter;
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always @(posedge clk) counter <= counter + 1;
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assign led = counter[`COUNTER_SIZE];
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endmodule
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*/
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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int param_highest_bit;
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const char *param_clock_pin, *param_led_pin;
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int iob_clk_y, iob_clk_x, iob_clk_type_idx;
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int iob_led_y, iob_led_x, iob_led_type_idx;
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int logic_x, logic_type_idx, cur_bit;
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int cur_y, next_y, i, rc;
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int lut_a5_used, lut_b5_used, lut_c5_used, lut_d5_used;
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struct fpgadev_logic logic_cfg;
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net_idx_t clock_net, net;
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// todo: test with clock=C10/IO_L37N_GCLK12_0, led=M16/IO_L46N_FOE_B_M1DQ3_1
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// currently: T8/R5
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// todo: we could support more ways to specify a pin:
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// "bpp:0,30,1" - die-specific bank/pair/positive
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// "name:T8" - package-specific pin (including unbonded ones)
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// "desc:IO_L30N_2" - package-specific description
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if (cmdline_help(argc, argv)) {
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printf( " %*s [-Dhighest_bit=14|23]\n"
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" %*s [-Dclock_pin=desc:IO_L30N_GCLK0_USERCCLK_2|...]\n"
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" %*s [-Dled_pin=desc:IO_L48P_D7_2|...]\n"
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"\n", (int) strlen(*argv), "",
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(int) strlen(*argv), "", (int) strlen(*argv), "");
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return 0;
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}
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if (!(param_highest_bit = cmdline_intvar(argc, argv, "highest_bit")))
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param_highest_bit = 14;
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if (!(param_clock_pin = cmdline_strvar(argc, argv, "clock_pin")))
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param_clock_pin = "IO_L30N_GCLK0_USERCCLK_2";
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if (!(param_led_pin = cmdline_strvar(argc, argv, "led_pin")))
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param_led_pin = "IO_L48P_D7_2";
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fpga_build_model(&model, cmdline_part(argc, argv),
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cmdline_package(argc, argv));
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fpga_find_iob(&model, xc6_find_pkg_pin(model.pkg, param_clock_pin),
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&iob_clk_y, &iob_clk_x, &iob_clk_type_idx);
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fdev_iob_input(&model, iob_clk_y, iob_clk_x, iob_clk_type_idx,
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IO_LVCMOS33);
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fpga_find_iob(&model, xc6_find_pkg_pin(model.pkg, param_led_pin),
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&iob_led_y, &iob_led_x, &iob_led_type_idx);
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fdev_iob_output(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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IO_LVCMOS25);
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fdev_iob_slew(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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SLEW_QUIETIO);
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fdev_iob_drive(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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8);
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// todo: temporary because our routing is so fragile...
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if (param_highest_bit == 14)
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cur_y = 58;
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else
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cur_y = 52;
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logic_x = 13;
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logic_type_idx = DEV_LOG_M_OR_L;
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// clock net
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fnet_new(&model, &clock_net);
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fnet_add_port(&model, clock_net, iob_clk_y, iob_clk_x, DEV_IOB,
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iob_clk_type_idx, IOB_OUT_I);
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for (cur_bit = 0; cur_bit <= param_highest_bit; cur_bit++) {
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RC_ASSERT(&model, cur_y != -1);
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if (!(cur_bit % 4)) { // beginning of slice
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CLEAR(logic_cfg);
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logic_cfg.clk_inv = CLKINV_CLK;
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logic_cfg.sync_attr = SYNCATTR_ASYNC;
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}
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if (!cur_bit) { // first bit
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logic_cfg.precyinit = PRECYINIT_0;
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logic_cfg.a2d[LUT_A].flags |= LUT5VAL_SET | LUT6VAL_SET;
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if ((rc = bool_str2lut_pair(
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/*lut6*/ "(A6+~A6)*(~A5)",
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/*lut5*/ "1",
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&logic_cfg.a2d[LUT_A].lut6_val,
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&logic_cfg.a2d[LUT_A].lut5_val))) RC_FAIL(&model, rc);
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logic_cfg.a2d[LUT_A].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_A].ff = FF_FF;
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logic_cfg.a2d[LUT_A].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_A].ff_srinit = FF_SRINIT0;
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} else if (cur_bit == param_highest_bit) {
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logic_cfg.a2d[cur_bit%4].flags |= LUT6VAL_SET;
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if ((rc = bool_str2u64("A5", &logic_cfg.a2d[cur_bit%4].lut6_val)))
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RC_FAIL(&model, rc);
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logic_cfg.a2d[cur_bit%4].ff = FF_FF;
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logic_cfg.a2d[cur_bit%4].ff_mux = MUX_XOR;
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logic_cfg.a2d[cur_bit%4].ff_srinit = FF_SRINIT0;
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} else {
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logic_cfg.a2d[cur_bit%4].flags |= LUT5VAL_SET | LUT6VAL_SET;
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if ((rc = bool_str2lut_pair(
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/*lut6*/ "(A6+~A6)*(A5)",
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/*lut5*/ "0",
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&logic_cfg.a2d[cur_bit%4].lut6_val,
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&logic_cfg.a2d[cur_bit%4].lut5_val))) RC_FAIL(&model, rc);
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logic_cfg.a2d[cur_bit%4].cy0 = CY0_O5;
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logic_cfg.a2d[cur_bit%4].ff = FF_FF;
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logic_cfg.a2d[cur_bit%4].ff_mux = MUX_XOR;
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logic_cfg.a2d[cur_bit%4].ff_srinit = FF_SRINIT0;
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}
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if (cur_bit%4 == 3 || cur_bit == param_highest_bit) {
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static const int out_pin[] = {LO_AQ, LO_BQ, LO_CQ, LO_DQ};
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static const int in_pin[] = {LI_A5, LI_B5, LI_C5, LI_D5};
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next_y = regular_row_up(cur_y, &model);
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if (cur_bit < param_highest_bit) {
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RC_ASSERT(&model, next_y != -1);
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logic_cfg.cout_used = 1;
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// carry chain
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fnet_new(&model, &net);
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LO_COUT);
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fnet_add_port(&model, net, next_y, logic_x, DEV_LOGIC, logic_type_idx, LI_CIN);
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fnet_route(&model, net);
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}
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fdev_logic_setconf(&model, cur_y, logic_x, logic_type_idx, &logic_cfg);
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// clock net
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fnet_add_port(&model, clock_net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_CLK);
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// lut5 net (drive vcc into A6 to enable lut5)
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lut_a5_used = fdev_logic_o5_used(&model, cur_y, logic_x, logic_type_idx, LUT_A);
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lut_b5_used = fdev_logic_o5_used(&model, cur_y, logic_x, logic_type_idx, LUT_B);
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lut_c5_used = fdev_logic_o5_used(&model, cur_y, logic_x, logic_type_idx, LUT_C);
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lut_d5_used = fdev_logic_o5_used(&model, cur_y, logic_x, logic_type_idx, LUT_D);
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if (lut_a5_used || lut_b5_used || lut_c5_used || lut_d5_used) {
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if (lut_a5_used)
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_A6);
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if (lut_b5_used)
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_B6);
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if (lut_c5_used)
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_C6);
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if (lut_d5_used)
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, LI_D6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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}
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for (i = 0; i <= cur_bit%4; i++) {
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fnet_new(&model, &net);
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, out_pin[i]);
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fnet_add_port(&model, net, cur_y, logic_x, DEV_LOGIC, logic_type_idx, in_pin[i]);
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if (cur_bit - cur_bit%4 + i == param_highest_bit)
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fnet_add_port(&model, net, iob_led_y, iob_led_x, DEV_IOB,
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iob_led_type_idx, IOB_IN_O);
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fnet_route(&model, net);
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}
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cur_y = next_y;
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}
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}
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fnet_route(&model, clock_net);
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write_floorplan(stdout, &model, FP_DEFAULT);
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return fpga_free_model(&model);
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}
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