455 lines
12 KiB
C
455 lines
12 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include <time.h>
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#include "model.h"
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#include "floorplan.h"
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#include "control.h"
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time_t g_start_time;
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#define TIME() (time(0)-g_start_time)
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#define TIMESTAMP() printf("O timestamp %lld\n", (long long) TIME())
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#define MEMUSAGE() printf("O memusage %i\n", get_vm_mb());
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#define TIME_AND_MEM() TIMESTAMP(); MEMUSAGE()
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#define AUTOTEST_TMP_DIR "autotest.tmp"
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struct test_state
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{
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struct fpga_model* model;
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// test filenames are: tmp_dir/autotest_<base_name>_<diff_counter>.???
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char tmp_dir[256];
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char base_name[256];
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int next_diff_counter;
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};
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static int dump_file(const char* path)
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{
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char line[1024];
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FILE* f;
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printf("\n");
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printf("O begin dump %s\n", path);
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f = fopen(path, "r");
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EXIT(!f);
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while (fgets(line, sizeof(line), f)) {
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if (!strncmp(line, "--- ", 4)
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|| !strncmp(line, "+++ ", 4)
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|| !strncmp(line, "@@ ", 3))
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continue;
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printf(line);
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}
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fclose(f);
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printf("O end dump %s\n", path);
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return 0;
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}
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static int diff_start(struct test_state* tstate, const char* base_name)
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{
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strcpy(tstate->base_name, base_name);
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tstate->next_diff_counter = 1;
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return 0;
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}
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static int diff_printf(struct test_state* tstate)
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{
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char path[1024], tmp[1024], prior_fp[1024];
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int path_base;
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FILE* dest_f = 0;
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int rc;
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snprintf(path, sizeof(path), "%s/autotest_%s_%04i", tstate->tmp_dir,
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tstate->base_name, tstate->next_diff_counter);
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path_base = strlen(path);
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if (tstate->next_diff_counter == 1)
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strcpy(prior_fp, "/dev/null");
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else {
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snprintf(prior_fp, sizeof(prior_fp), "%s/autotest_%s_%04i.fp",
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tstate->tmp_dir, tstate->base_name,
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tstate->next_diff_counter-1);
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}
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strcpy(&path[path_base], ".fp");
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dest_f = fopen(path, "w");
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if (!dest_f) FAIL(errno);
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rc = printf_devices(dest_f, tstate->model, /*config_only*/ 1);
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if (rc) FAIL(rc);
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rc = printf_nets(dest_f, tstate->model);
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if (rc) FAIL(rc);
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fclose(dest_f);
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dest_f = 0;
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path[path_base] = 0;
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snprintf(tmp, sizeof(tmp), "./autotest_diff.sh %s %s.fp >%s.log 2>&1",
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prior_fp, path, path);
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rc = system(tmp);
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if (rc) FAIL(rc);
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strcpy(&path[path_base], ".diff");
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rc = dump_file(path);
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if (rc) FAIL(rc);
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tstate->next_diff_counter++;
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return 0;
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fail:
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if (dest_f) fclose(dest_f);
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return rc;
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}
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static void cut_sw_from_end(struct fpga_net* net, int cut_o)
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{
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if (cut_o <= 2) return;
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memmove(&net->el[2], &net->el[cut_o],
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(net->len-cut_o)*sizeof(net->el[0]));
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net->len = 2 + net->len-cut_o;
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}
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static int test_net(struct test_state* tstate, net_idx_t net_i)
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{
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struct fpga_net* net;
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struct fpga_net copy_net;
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swidx_t same_sw[64];
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int same_len;
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int i, j, rc;
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net = fpga_net_get(tstate->model, net_i);
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if (!net) FAIL(EINVAL);
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copy_net = *net;
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for (i = net->len-1; i >= 2; i--) {
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printf("round i %i\n", i);
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*net = copy_net;
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cut_sw_from_end(net, i);
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if (net->len <= 2) {
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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continue;
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}
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// what other switches go to SW_TO(el[2])?
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printf_swchain(tstate->model,
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net->el[2].y, net->el[2].x,
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fpga_switch_str_i(tstate->model,
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net->el[2].y, net->el[2].x,
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net->el[2].idx, SW_TO), SW_TO, 1);
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same_len = sizeof(same_sw)/sizeof(*same_sw);
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rc = fpga_switch_same_fromto(tstate->model,
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net->el[2].y, net->el[2].x,
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net->el[2].idx, SW_TO, same_sw, &same_len);
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if (rc) FAIL(rc);
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printf("same_len at this level %i\n", same_len);
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for (j = 0; j < same_len; j++) {
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net->el[2].idx = same_sw[j];
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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}
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}
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return 0;
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fail:
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return rc;
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}
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static int test_net2(struct test_state* tstate, net_idx_t net_i)
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{
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struct fpga_net* net;
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struct fpga_net copy_net;
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swidx_t same_sw[64];
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int same_len;
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int i, j, rc;
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net = fpga_net_get(tstate->model, net_i);
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if (!net) FAIL(EINVAL);
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copy_net = *net;
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for (i = 3; i <= net->len-1; i++) {
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printf("round i %i\n", i);
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net->len = i;
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// what other switches go from SW_FROM(el[i-1])?
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printf_swchain(tstate->model,
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net->el[i-1].y, net->el[i-1].x,
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fpga_switch_str_i(tstate->model,
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net->el[i-1].y, net->el[i-1].x,
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net->el[i-1].idx, SW_FROM), SW_FROM, 1);
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same_len = sizeof(same_sw)/sizeof(*same_sw);
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rc = fpga_switch_same_fromto(tstate->model,
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net->el[i-1].y, net->el[i-1].x,
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net->el[i-1].idx, SW_FROM, same_sw, &same_len);
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if (rc) FAIL(rc);
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printf("same_len at this level %i\n", same_len);
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#if 1
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for (j = 0; j < same_len; j++) {
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net->el[i-1].idx = same_sw[j];
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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}
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#endif
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*net = copy_net;
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}
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return 0;
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fail:
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return rc;
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}
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static int test_all_logic_configs(struct test_state* tstate)
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{
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struct fpga_device* dev;
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struct switch_to_yx switch_to;
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struct sw_chain chain;
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net_idx_t net_idx;
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int y, x, i, from_to, rc;
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// todo: goal: configure valid logic with as many possible in and out
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// pins, for M and X device
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y = 68;
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x = 13;
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rc = fdev_logic_set_lut(tstate->model, y, x,
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DEV_LOGX, D6_LUT, "A3", ZTERM);
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if (rc) FAIL(rc);
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rc = fdev_set_required_pins(tstate->model, y, x, DEV_LOGIC, DEV_LOGX);
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if (rc) FAIL(rc);
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// fdev_print_required_pins(tstate->model, y, x, DEV_LOGIC, DEV_LOGX);
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dev = fdev_p(tstate->model, y, x, DEV_LOGIC, DEV_LOGX);
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if (!dev) FAIL(EINVAL);
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for (i = 0; i < dev->pinw_req_total; i++) {
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from_to = (i < dev->pinw_req_in) ? SW_TO : SW_FROM;
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switch_to.yx_req = YX_ROUTING_TILE;
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switch_to.flags = SWTO_YX_DEF;
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switch_to.model = tstate->model;
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switch_to.y = y;
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switch_to.x = x;
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switch_to.start_switch = dev->pinw[dev->pinw_req_for_cfg[i]];
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switch_to.from_to = from_to;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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// printf_switch_to_result(&switch_to);
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chain.model = tstate->model;
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chain.y = switch_to.dest_y;
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chain.x = switch_to.dest_x;
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chain.start_switch = switch_to.dest_connpt;
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chain.from_to = from_to;
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chain.max_chain_size = 1;
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while (fpga_switch_chain(&chain) != NO_SWITCH) {
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rc = fpga_net_new(tstate->model, &net_idx);
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if (rc) FAIL(rc);
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// add port
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rc = fpga_net_add_port(tstate->model, net_idx,
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y, x, fpga_dev_idx(tstate->model, y, x,
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DEV_LOGIC, DEV_LOGX), dev->pinw_req_for_cfg[i]);
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if (rc) FAIL(rc);
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// add (one) switch in logic tile
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rc = fpga_net_add_switches(tstate->model, net_idx,
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y, x, &switch_to.set);
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if (rc) FAIL(rc);
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// add switches in routing tile
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rc = fpga_net_add_switches(tstate->model, net_idx,
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switch_to.dest_y, switch_to.dest_x, &chain.set);
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if (rc) FAIL(rc);
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// fprintf_net(stdout, tstate->model, net_idx);
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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fpga_net_delete(tstate->model, net_idx);
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}
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}
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return 0;
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fail:
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return rc;
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}
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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struct fpga_device* P46_dev, *P48_dev, *logic_dev;
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int P46_y, P46_x, P46_dev_idx, P46_type_idx;
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int P48_y, P48_x, P48_dev_idx, P48_type_idx, logic_dev_idx, rc;
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struct test_state tstate;
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struct switch_to_yx switch_to;
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net_idx_t P46_net;
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// flush after every line is better for the autotest
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// output, tee, etc.
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// for example: ./autotest 2>&1 | tee autotest.log
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setvbuf(stdout, /*buf*/ 0, _IOLBF, /*size*/ 0);
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printf("\n");
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printf("O fpgatools automatic test suite. Be welcome and be "
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"our guest. namo namaha.\n");
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printf("\n");
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printf("O Time measured in seconds from 0.\n");
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g_start_time = time(0);
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TIMESTAMP();
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printf("O Memory usage reported in megabytes.\n");
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MEMUSAGE();
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printf("O Building memory model...\n");
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if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
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XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING)))
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goto fail;
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printf("O Done\n");
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TIME_AND_MEM();
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tstate.model = &model;
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strcpy(tstate.tmp_dir, AUTOTEST_TMP_DIR);
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mkdir(tstate.tmp_dir, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH);
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rc = diff_start(&tstate, "and");
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if (rc) FAIL(rc);
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#if 0
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// configure P46
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rc = fpga_find_iob(&model, "P46", &P46_y, &P46_x, &P46_type_idx);
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if (rc) FAIL(rc);
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P46_dev_idx = fpga_dev_idx(&model, P46_y, P46_x, DEV_IOB, P46_type_idx);
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if (P46_dev_idx == NO_DEV) FAIL(EINVAL);
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P46_dev = FPGA_DEV(&model, P46_y, P46_x, P46_dev_idx);
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P46_dev->instantiated = 1;
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strcpy(P46_dev->iob.istandard, IO_LVCMOS33);
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P46_dev->iob.bypass_mux = BYPASS_MUX_I;
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P46_dev->iob.I_mux = IMUX_I;
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// configure P48
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rc = fpga_find_iob(&model, "P48", &P48_y, &P48_x, &P48_type_idx);
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if (rc) FAIL(rc);
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P48_dev_idx = fpga_dev_idx(&model, P48_y, P48_x, DEV_IOB, P48_type_idx);
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if (P48_dev_idx == NO_DEV) FAIL(EINVAL);
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P48_dev = FPGA_DEV(&model, P48_y, P48_x, P48_dev_idx);
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P48_dev->instantiated = 1;
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strcpy(P48_dev->iob.ostandard, IO_LVCMOS33);
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P48_dev->iob.drive_strength = 12;
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P48_dev->iob.O_used = 1;
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P48_dev->iob.slew = SLEW_SLOW;
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P48_dev->iob.suspend = SUSP_3STATE;
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#endif
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// configure logic
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// todo: goal: configure valid logic with as many possible in and out
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// pins, for M and X device
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#if 0
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logic_dev_idx = fpga_dev_idx(&model, /*y*/ 68, /*x*/ 13,
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DEV_LOGIC, DEV_LOGX);
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if (logic_dev_idx == NO_DEV) FAIL(EINVAL);
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logic_dev = FPGA_DEV(&model, /*y*/ 68, /*x*/ 13, logic_dev_idx);
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logic_dev->instantiated = 1;
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logic_dev->logic.D_used = 1;
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rc = fpga_set_lut(&model, logic_dev, D6_LUT, "A3", ZTERM);
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if (rc) FAIL(rc);
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#endif
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rc = test_all_logic_configs(&tstate);
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if (rc) FAIL(rc);
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#if 0
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rc = diff_printf(&tstate);
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if (rc) FAIL(rc);
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#endif
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#if 0
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// configure net from P46.I to logic.D3
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rc = fpga_net_new(&model, &P46_net);
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if (rc) FAIL(rc);
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rc = fpga_net_add_port(&model, P46_net, P46_y, P46_x,
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P46_dev_idx, IOB_OUT_I);
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if (rc) FAIL(rc);
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rc = fpga_net_add_port(&model, P46_net, /*y*/ 68, /*x*/ 13,
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logic_dev_idx, LOGIC_IN_D3);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_DEV_ILOGIC;
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switch_to.flags = SWTO_YX_DEF;
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switch_to.model = &model;
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switch_to.y = P46_y;
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switch_to.x = P46_x;
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switch_to.start_switch = P46_dev->pinw[IOB_OUT_I];
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switch_to.from_to = SW_FROM;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fpga_net_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_ROUTING_TILE;
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switch_to.flags = SWTO_YX_DEF;
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switch_to.model = &model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fpga_net_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_ROUTING_TO_FABLOGIC;
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switch_to.flags = SWTO_YX_CLOSEST;
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switch_to.model = &model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fpga_net_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_DEV_LOGIC;
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switch_to.flags = SWTO_YX_TARGET_CONNPT|SWTO_YX_MAX_SWITCH_DEPTH;
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switch_to.model = &model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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switch_to.max_switch_depth = 1;
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{
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struct sw_chain c = {
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.model = &model, .y = switch_to.dest_y,
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.x = switch_to.dest_x+1,
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.start_switch = logic_dev->pinw[LOGIC_IN_D3],
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.from_to = SW_TO, .max_chain_size = MAX_SW_DEPTH };
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if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
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if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
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switch_to.target_connpt = fpga_switch_str_i(&model,
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switch_to.dest_y, switch_to.dest_x+1,
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c.set.sw[c.set.len-1], SW_FROM);
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}
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fpga_net_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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{
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struct sw_chain c = {
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.model = &model, .y = switch_to.dest_y,
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.x = switch_to.dest_x,
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.start_switch = switch_to.dest_connpt,
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.from_to = SW_FROM, .max_chain_size = MAX_SW_DEPTH };
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if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
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if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
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rc = fpga_net_add_switches(&model, P46_net, c.y, c.x, &c.set);
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if (rc) FAIL(rc);
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|
}
|
|
|
|
rc = test_net2(&tstate, P46_net);
|
|
if (rc) FAIL(rc);
|
|
#endif
|
|
|
|
printf("\n");
|
|
printf("O Test suite completed.\n");
|
|
TIME_AND_MEM();
|
|
printf("\n");
|
|
return EXIT_SUCCESS;
|
|
fail:
|
|
return rc;
|
|
}
|