232 lines
8.1 KiB
C
232 lines
8.1 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <assert.h>
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#include <sys/stat.h>
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#define MACRO_STR(arg) #arg
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#include "helper.h"
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//
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// columns
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// 'L' = X+L logic block
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// 'M' = X+M logic block
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// 'B' = block ram
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// 'D' = dsp (macc)
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// 'R' = registers and center IO/logic column
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//
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// 'n' = noio - can follow L or M to designate a logic
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// column without IO at top or bottom
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// 'g' = gclk - can follow LlMmBD to designate exactly one
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// place on the left and right side of the chip where
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// the global clock is separated into left and right
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// half (on each side of the chip, for a total of 4
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// vertical clock separations).
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//
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// wiring on the left and right side is described with 16
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// characters for each row, order is top-down
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// 'W' = wired
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// 'U' = unwired
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//
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#define XC6SLX9_ROWS 4
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#define XC6SLX9_COLUMNS "M L Bg M L D M R M Ln M L Bg M L"
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#define XC6SLX9_LEFT_WIRING \
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/* row 3 */ "UWUWUWUW" "WWWWUUUU" \
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/* row 2 */ "UUUUUUUU" "WWWWWWUU" \
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/* row 1 */ "WWWUUWUU" "WUUWUUWU" \
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/* row 0 */ "UWUUWUUW" "UUWWWWUU"
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#define XC6SLX9_RIGHT_WIRING \
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/* row 3 */ "UUWWUWUW" "WWWWUUUU" \
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/* row 2 */ "UUUUUUUU" "WWWWWWUU" \
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/* row 1 */ "WWWUUWUU" "WUUWUUWU" \
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/* row 0 */ "UWUUWUUW" "UUWWWWUU"
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struct fpga_model
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{
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int cfg_rows;
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char cfg_columns[512];
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char cfg_left_wiring[1024], cfg_right_wiring[1024];
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int tile_x_range, tile_y_range;
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int center_x;
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int center_y;
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// Left and right gclk separators will be located on
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// the device column (+1 or +2) of the logic or dsp/macc
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// column as indicated in the chip's cfg_columns with a 'g'.
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int left_gclk_sep_x, right_gclk_sep_x;
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struct fpga_tile* tiles;
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struct hashed_strarray str;
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// tmp_str will be allocated to hold max(tile_x_range, tile_y_range)
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// pointers, useful for string seeding when running wires.
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const char** tmp_str;
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};
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enum fpga_tile_type
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{
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NA = 0,
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ROUTING, ROUTING_BRK, ROUTING_VIA,
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HCLK_ROUTING_XM, HCLK_ROUTING_XL, HCLK_LOGIC_XM, HCLK_LOGIC_XL,
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LOGIC_XM, LOGIC_XL,
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REGH_ROUTING_XM, REGH_ROUTING_XL, REGH_LOGIC_XM, REGH_LOGIC_XL,
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BRAM_ROUTING, BRAM_ROUTING_BRK,
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BRAM,
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BRAM_ROUTING_TERM_T, BRAM_ROUTING_TERM_B, BRAM_ROUTING_VIA_TERM_T, BRAM_ROUTING_VIA_TERM_B,
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BRAM_TERM_LT, BRAM_TERM_RT, BRAM_TERM_LB, BRAM_TERM_RB,
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HCLK_BRAM_ROUTING, HCLK_BRAM_ROUTING_VIA, HCLK_BRAM,
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REGH_BRAM_ROUTING, REGH_BRAM_ROUTING_VIA, REGH_BRAM_L, REGH_BRAM_R,
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MACC,
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HCLK_MACC_ROUTING, HCLK_MACC_ROUTING_VIA, HCLK_MACC,
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REGH_MACC_ROUTING, REGH_MACC_ROUTING_VIA, REGH_MACC_L,
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PLL_T, DCM_T, PLL_B, DCM_B, REG_T,
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REG_TERM_T, REG_TERM_B, REG_B,
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REGV_TERM_T, REGV_TERM_B,
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HCLK_REGV,
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REGV, REGV_BRK, REGV_T, REGV_B, REGV_MIDBUF_T, REGV_HCLKBUF_T, REGV_HCLKBUF_B, REGV_MIDBUF_B,
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REGC_ROUTING, REGC_LOGIC, REGC_CMT,
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CENTER, // unique center tile in the middle of the chip
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IO_T, IO_B, IO_TERM_T, IO_TERM_B, IO_ROUTING, IO_LOGIC_TERM_T, IO_LOGIC_TERM_B,
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IO_OUTER_T, IO_INNER_T, IO_OUTER_B, IO_INNER_B,
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IO_BUFPLL_TERM_T, IO_LOGIC_REG_TERM_T, IO_BUFPLL_TERM_B, IO_LOGIC_REG_TERM_B,
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LOGIC_ROUTING_TERM_B, LOGIC_NOIO_TERM_B,
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MACC_ROUTING_TERM_T, MACC_ROUTING_TERM_B, MACC_VIA_TERM_T,
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MACC_TERM_TL, MACC_TERM_TR, MACC_TERM_BL, MACC_TERM_BR,
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ROUTING_VIA_REGC, ROUTING_VIA_IO, ROUTING_VIA_IO_DCM, ROUTING_VIA_CARRY,
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CORNER_TERM_L, CORNER_TERM_R,
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IO_TERM_L_UPPER_TOP, IO_TERM_L_UPPER_BOT, IO_TERM_L_LOWER_TOP, IO_TERM_L_LOWER_BOT,
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IO_TERM_R_UPPER_TOP, IO_TERM_R_UPPER_BOT, IO_TERM_R_LOWER_TOP, IO_TERM_R_LOWER_BOT,
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IO_TERM_L, IO_TERM_R,
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HCLK_TERM_L, HCLK_TERM_R,
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REGH_IO_TERM_L, REGH_IO_TERM_R,
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REG_L, REG_R,
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IO_PCI_L, IO_PCI_R, IO_RDY_L, IO_RDY_R,
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IO_L, IO_R,
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IO_PCI_CONN_L, IO_PCI_CONN_R,
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CORNER_TERM_T, CORNER_TERM_B,
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ROUTING_IO_L,
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HCLK_ROUTING_IO_L, HCLK_ROUTING_IO_R, REGH_ROUTING_IO_L, REGH_ROUTING_IO_R,
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ROUTING_IO_L_BRK, ROUTING_GCLK,
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REGH_IO_L, REGH_IO_R, REGH_MCB, HCLK_MCB,
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ROUTING_IO_VIA_L, ROUTING_IO_VIA_R, ROUTING_IO_PCI_CE_L, ROUTING_IO_PCI_CE_R,
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CORNER_TL, CORNER_BL,
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CORNER_TR_UPPER, CORNER_TR_LOWER, CORNER_BR_UPPER, CORNER_BR_LOWER,
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HCLK_IO_TOP_UP_L, HCLK_IO_TOP_UP_R,
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HCLK_IO_TOP_SPLIT_L, HCLK_IO_TOP_SPLIT_R,
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HCLK_IO_TOP_DN_L, HCLK_IO_TOP_DN_R,
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HCLK_IO_BOT_UP_L, HCLK_IO_BOT_UP_R,
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HCLK_IO_BOT_SPLIT_L, HCLK_IO_BOT_SPLIT_R,
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HCLK_IO_BOT_DN_L, HCLK_IO_BOT_DN_R,
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};
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// Some constant to make the core more readable
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#define LEFT_IO_ROUTING 2
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#define LEFT_IO_DEVS 3
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#define TOP_IO_TILES 2
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// tile flags
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#define TF_FABRIC_ROUTING_COL 0x00000001 // only set in y==0, not for left and right IO routing or center
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#define TF_FABRIC_LOGIC_COL 0x00000002 // only set in y==0
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#define TF_FABRIC_BRAM_MACC_ROUTING_COL 0x00000004 // only set in y==0
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#define TF_FABRIC_BRAM_COL 0x00000008 // only set in y==0
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#define TF_FABRIC_MACC_COL 0x00000010 // only set in y==0
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#define TF_BRAM_DEV 0x00000020
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#define TF_MACC_DEV 0x00000040
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#define TF_LOGIC_XL_DEV 0x00000080
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#define TF_LOGIC_XM_DEV 0x00000100
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#define TF_IOLOGIC_DELAY_DEV 0x00000200
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#define TF_DCM_DEV 0x00000400
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#define TF_PLL_DEV 0x00000800
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#define Y_INNER_TOP 0x0001
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#define Y_INNER_BOTTOM 0x0002
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#define Y_CHIP_HORIZ_REGS 0x0004
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#define Y_ROW_HORIZ_AXSYMM 0x0008
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#define Y_BOTTOM_OF_ROW 0x0010
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// multiple checks are combined with OR logic
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int is_aty(int check, struct fpga_model* model, int y);
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#define X_OUTER_LEFT 0x00000001
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#define X_INNER_LEFT 0x00000002
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#define X_INNER_RIGHT 0x00000004
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#define X_OUTER_RIGHT 0x00000008
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#define X_ROUTING_COL 0x00000010 // includes routing col in left and right IO and center
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#define X_ROUTING_TO_BRAM_COL 0x00000020
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#define X_ROUTING_TO_MACC_COL 0x00000040
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#define X_LOGIC_COL 0x00000080 // includes the center logic col
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#define X_FABRIC_ROUTING_COL 0x00000100
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#define X_FABRIC_LOGIC_COL 0x00000200
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#define X_FABRIC_BRAM_MACC_ROUTING_COL 0x00000400
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#define X_FABRIC_BRAM_COL 0x00000800
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#define X_FABRIC_MACC_COL 0x00001000
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#define X_CENTER_ROUTING_COL 0x00002000
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#define X_CENTER_LOGIC_COL 0x00004000
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#define X_CENTER_CMTPLL_COL 0x00008000
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#define X_CENTER_REGS_COL 0x00010000
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#define X_LEFT_IO_ROUTING_COL 0x00020000
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#define X_LEFT_IO_DEVS_COL 0x00040000
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#define X_RIGHT_IO_ROUTING_COL 0x00080000
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#define X_RIGHT_IO_DEVS_COL 0x00100000
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#define X_LEFT_SIDE 0x00200000 // true for anything left of the center (not including center)
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// multiple checks are combined with OR logic
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int is_atx(int check, struct fpga_model* model, int x);
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// True for all tiles that are in the regular 0..15 row tiles of a routing col
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#define YX_ROUTING_TILE 0x0001
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int is_atyx(int check, struct fpga_model* model, int y, int x);
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#define SWITCH_BIDIRECTIONAL 0x40000000
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struct fpga_tile
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{
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enum fpga_tile_type type;
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int flags;
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// expect up to 64 devices per tile
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int num_devices;
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struct fpga_device* devices;
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// expect up to 5k connection point names per tile
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// 2*16 bit per entry
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// - index into conn_point_dests (not multiplied by 3) (16bit)
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// - hashed string array index (16 bit)
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int num_conn_point_names; // conn_point_names is 2*num_conn_point_names 16-bit words
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uint16_t* conn_point_names; // num_conn_point_names*2 16-bit-words: 16(conn)-16(str)
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// expect up to 28k connection point destinations to other tiles per tile
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// 3*16 bit per destination:
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// - x coordinate of other tile (16bit)
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// - y coordinate of other tile (16bit)
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// - hashed string array index for conn_point_names name in other tile (16bit)
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int num_conn_point_dests; // conn_point_dests array is 3*num_conn_point_dests 16-bit words
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uint16_t* conn_point_dests; // num_conn_point_dests*3 16-bit words: 16(x)-16(y)-16(conn_name)
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// expect up to 4k switches per tile
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// 32bit: 31 off: no connection on: connected
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// 30 off: unidirectional on: bidirectional
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// 29:15 from, index into conn_point_names
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// 14:0 to, index into conn_point_names
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int num_switches;
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uint32_t* switches;
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};
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int fpga_build_model(struct fpga_model* model,
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int fpga_rows, const char* columns,
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const char* left_wiring, const char* right_wiring);
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void fpga_free_model(struct fpga_model* model);
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const char* fpga_tiletype_str(enum fpga_tile_type type);
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