701 lines
19 KiB
C
701 lines
19 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include "model.h"
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#include "bit.h"
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#include "parts.h"
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#include "control.h"
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#define HCLK_BYTES 2
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static uint8_t* get_first_minor(struct fpga_bits* bits, int row, int major)
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{
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int i, num_frames;
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num_frames = 0;
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for (i = 0; i < major; i++)
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num_frames += get_major_minors(XC6SLX9, i);
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return &bits->d[(row*FRAMES_PER_ROW + num_frames)*FRAME_SIZE];
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}
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static int get_bit(struct fpga_bits* bits,
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int row, int major, int minor, int bit_i)
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{
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return frame_get_bit(get_first_minor(bits, row, major)
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+ minor*FRAME_SIZE, bit_i);
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}
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static void set_bit(struct fpga_bits* bits,
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int row, int major, int minor, int bit_i)
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{
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return frame_set_bit(get_first_minor(bits, row, major)
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+ minor*FRAME_SIZE, bit_i);
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}
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static void clear_bit(struct fpga_bits* bits,
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int row, int major, int minor, int bit_i)
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{
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return frame_clear_bit(get_first_minor(bits, row, major)
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+ minor*FRAME_SIZE, bit_i);
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}
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struct bit_pos
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{
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int row;
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int major;
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int minor;
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int bit_i;
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};
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static int get_bitp(struct fpga_bits* bits, struct bit_pos* pos)
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{
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return get_bit(bits, pos->row, pos->major, pos->minor, pos->bit_i);
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}
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static void set_bitp(struct fpga_bits* bits, struct bit_pos* pos)
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{
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set_bit(bits, pos->row, pos->major, pos->minor, pos->bit_i);
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}
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static void clear_bitp(struct fpga_bits* bits, struct bit_pos* pos)
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{
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clear_bit(bits, pos->row, pos->major, pos->minor, pos->bit_i);
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}
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static struct bit_pos s_default_bits[] = {
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{ 0, 0, 3, 66 },
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{ 0, 1, 23, 1034 },
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{ 0, 1, 23, 1035 },
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{ 0, 1, 23, 1039 },
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{ 2, 0, 3, 66 }};
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struct sw_yxpos
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{
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int y;
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int x;
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swidx_t idx;
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};
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#define MAX_YX_SWITCHES 1024
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struct extract_state
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{
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struct fpga_model* model;
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struct fpga_bits* bits;
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// yx switches are fully extracted ones pointing into the
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// model, stored here for later processing into nets.
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int num_yx_pos;
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struct sw_yxpos yx_pos[MAX_YX_SWITCHES]; // needs to be dynamically alloced...
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};
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static int write_iobs(struct fpga_bits* bits, struct fpga_model* model)
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{
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int i, y, x, type_idx, part_idx, dev_idx, rc;
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struct fpga_device* dev;
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uint32_t* u32_p;
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const char* name;
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for (i = 0; (name = fpga_enum_iob(model, i, &y, &x, &type_idx)); i++) {
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dev_idx = fpga_dev_idx(model, y, x, DEV_IOB, type_idx);
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if (dev_idx == NO_DEV) FAIL(EINVAL);
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dev = FPGA_DEV(model, y, x, dev_idx);
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if (!dev->instantiated)
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continue;
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part_idx = find_iob_sitename(XC6SLX9, name);
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if (part_idx == -1) {
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HERE();
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continue;
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}
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u32_p = (uint32_t*)
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&bits->d[IOB_DATA_START + part_idx*IOB_ENTRY_LEN];
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if (dev->u.iob.O_used) {
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u32_p[0] = 0x00000180;
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u32_p[1] = 0x06001100;
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} else if (dev->u.iob.I_mux == IMUX_I) {
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u32_p[0] = 0x00000107;
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u32_p[1] = 0x0B002400;
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}
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}
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return 0;
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fail:
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return rc;
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}
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static int extract_iobs(struct fpga_model* model, struct fpga_bits* bits)
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{
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int i, num_iobs, iob_y, iob_x, iob_idx, dev_idx, rc;
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uint32_t* u32_p;
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const char* iob_sitename;
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struct fpga_device* dev;
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num_iobs = get_num_iobs(XC6SLX9);
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for (i = 0; i < num_iobs; i++) {
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u32_p = (uint32_t*) &bits->d[IOB_DATA_START + i*IOB_ENTRY_LEN];
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if (!u32_p[0] && !u32_p[1])
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continue;
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iob_sitename = get_iob_sitename(XC6SLX9, i);
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if (!iob_sitename) {
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HERE();
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continue;
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}
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rc = fpga_find_iob(model, iob_sitename, &iob_y, &iob_x, &iob_idx);
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if (rc) FAIL(rc);
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dev_idx = fpga_dev_idx(model, iob_y, iob_x, DEV_IOB, iob_idx);
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if (dev_idx == NO_DEV) FAIL(EINVAL);
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dev = FPGA_DEV(model, iob_y, iob_x, dev_idx);
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// we only support 2 hardcoded types of IOB right now
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// todo: bit 7 goes on when out-net connected?
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if ((u32_p[0] & 0xFFFFFF7F) == 0x00000100
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&& u32_p[1] == 0x06001100) {
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dev->instantiated = 1;
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strcpy(dev->u.iob.ostandard, IO_LVCMOS33);
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dev->u.iob.drive_strength = 12;
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dev->u.iob.O_used = 1;
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dev->u.iob.slew = SLEW_SLOW;
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dev->u.iob.suspend = SUSP_3STATE;
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u32_p[0] = 0;
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u32_p[1] = 0;
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} else if (u32_p[0] == 0x00000107
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&& u32_p[1] == 0x0B002400) {
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dev->instantiated = 1;
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strcpy(dev->u.iob.istandard, IO_LVCMOS33);
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dev->u.iob.bypass_mux = BYPASS_MUX_I;
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dev->u.iob.I_mux = IMUX_I;
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u32_p[0] = 0;
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u32_p[1] = 0;
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} else HERE();
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}
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return 0;
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fail:
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return rc;
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}
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static int extract_logic(struct fpga_model* model, struct fpga_bits* bits)
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{
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int dev_idx, row, row_pos, rc;
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int x, y, byte_off;
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uint8_t* u8_p;
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uint64_t u64;
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const char* lut_str;
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for (x = LEFT_SIDE_WIDTH; x < model->x_width-RIGHT_SIDE_WIDTH; x++) {
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if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x))
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continue;
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!has_device_type(model, y, x, DEV_LOGIC, LOGIC_M))
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continue;
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row = which_row(y, model);
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row_pos = pos_in_row(y, model);
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if (row == -1 || row_pos == -1 || row_pos == 8) {
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HERE();
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continue;
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}
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if (row_pos > 8) row_pos--;
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u8_p = get_first_minor(bits, row, model->x_major[x]);
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byte_off = row_pos * 8;
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if (row_pos >= 8) byte_off += HCLK_BYTES;
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// M device
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dev_idx = fpga_dev_idx(model, y, x, DEV_LOGIC, DEV_LOGM);
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if (dev_idx == NO_DEV) FAIL(EINVAL);
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// A6_LUT
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if (frame_get_u32(u8_p + 24*FRAME_SIZE + byte_off + 4)
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|| frame_get_u32(u8_p + 25*FRAME_SIZE + byte_off + 4)) {
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u64 = read_lut64(u8_p + 24*FRAME_SIZE, (byte_off+4)*8);
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{ int logic_base[6] = {0,1,0,0,1,0};
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lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 1); }
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if (*lut_str) {
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rc = fdev_logic_set_lut(model, y, x, DEV_LOGM,
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LUT_A, 6, lut_str, ZTERM);
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if (rc) FAIL(rc);
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*(uint32_t*)(u8_p+24*FRAME_SIZE+byte_off+4) = 0;
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*(uint32_t*)(u8_p+25*FRAME_SIZE+byte_off+4) = 0;
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}
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}
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// B6_LUT
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if (frame_get_u32(u8_p + 21*FRAME_SIZE + byte_off + 4)
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|| frame_get_u32(u8_p + 22*FRAME_SIZE + byte_off + 4)) {
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u64 = read_lut64(u8_p + 21*FRAME_SIZE, (byte_off+4)*8);
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{ int logic_base[6] = {1,1,0,1,0,1};
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lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 1); }
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if (*lut_str) {
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rc = fdev_logic_set_lut(model, y, x, DEV_LOGM,
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LUT_B, 6, lut_str, ZTERM);
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if (rc) FAIL(rc);
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*(uint32_t*)(u8_p+21*FRAME_SIZE+byte_off+4) = 0;
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*(uint32_t*)(u8_p+22*FRAME_SIZE+byte_off+4) = 0;
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}
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}
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// C6_LUT
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if (frame_get_u32(u8_p + 24*FRAME_SIZE + byte_off)
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|| frame_get_u32(u8_p + 25*FRAME_SIZE + byte_off)) {
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u64 = read_lut64(u8_p + 24*FRAME_SIZE, byte_off*8);
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{ int logic_base[6] = {0,1,0,0,1,0};
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lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 1); }
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if (*lut_str) {
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rc = fdev_logic_set_lut(model, y, x, DEV_LOGM,
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LUT_C, 6, lut_str, ZTERM);
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if (rc) FAIL(rc);
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*(uint32_t*)(u8_p+24*FRAME_SIZE+byte_off) = 0;
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*(uint32_t*)(u8_p+25*FRAME_SIZE+byte_off) = 0;
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}
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}
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// D6_LUT
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if (frame_get_u32(u8_p + 21*FRAME_SIZE + byte_off)
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|| frame_get_u32(u8_p + 22*FRAME_SIZE + byte_off)) {
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u64 = read_lut64(u8_p + 21*FRAME_SIZE, byte_off*8);
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{ int logic_base[6] = {1,1,0,1,0,1};
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lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 1); }
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if (*lut_str) {
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rc = fdev_logic_set_lut(model, y, x, DEV_LOGM,
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LUT_D, 6, lut_str, ZTERM);
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if (rc) FAIL(rc);
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*(uint32_t*)(u8_p+21*FRAME_SIZE+byte_off) = 0;
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*(uint32_t*)(u8_p+22*FRAME_SIZE+byte_off) = 0;
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}
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}
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// X device
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u64 = frame_get_u64(u8_p + 26*FRAME_SIZE + byte_off);
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if ( u64 ) {
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// 21, 22, 36 and 37 are actually not default
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// and can go off with the FFMUXes or routing
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// say D over the FF to DQ etc. (AFFMUX=b37,
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// BFFMUX=b36, CFFMUX=b22, DFFMUX=b21).
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if (!(u64 & (1ULL<<1) && u64 & (1ULL<<2)
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&& u64 & (1ULL<<7) && u64 & (1ULL<<21)
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&& u64 & (1ULL<<22) && u64 & (1ULL<<36)
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&& u64 & (1ULL<<37) && u64 & (1ULL<<39))) {
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HERE();
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continue;
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}
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if (u64 & ~(0x000000B000600086ULL)) {
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HERE();
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continue;
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}
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dev_idx = fpga_dev_idx(model, y, x, DEV_LOGIC, DEV_LOGX);
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if (dev_idx == NO_DEV) FAIL(EINVAL);
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*(uint64_t*)(u8_p+26*FRAME_SIZE+byte_off) = 0;
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// A6_LUT
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u64 = read_lut64(u8_p + 27*FRAME_SIZE, (byte_off+4)*8);
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{ int logic_base[6] = {1,1,0,1,1,0};
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lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 0); }
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if (*lut_str) {
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rc = fdev_logic_set_lut(model, y, x, DEV_LOGX,
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LUT_A, 6, lut_str, ZTERM);
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if (rc) FAIL(rc);
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*(uint32_t*)(u8_p+27*FRAME_SIZE+byte_off+4) = 0;
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*(uint32_t*)(u8_p+28*FRAME_SIZE+byte_off+4) = 0;
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}
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// B6_LUT
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u64 = read_lut64(u8_p + 29*FRAME_SIZE, (byte_off+4)*8);
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{ int logic_base[6] = {1,1,0,1,1,0};
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lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 0); }
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if (*lut_str) {
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rc = fdev_logic_set_lut(model, y, x, DEV_LOGX,
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LUT_B, 6, lut_str, ZTERM);
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*(uint32_t*)(u8_p+29*FRAME_SIZE+byte_off+4) = 0;
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*(uint32_t*)(u8_p+30*FRAME_SIZE+byte_off+4) = 0;
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}
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// C6_LUT
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u64 = read_lut64(u8_p + 27*FRAME_SIZE, byte_off*8);
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{ int logic_base[6] = {0,1,0,0,0,1};
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lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 0); }
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if (*lut_str) {
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rc = fdev_logic_set_lut(model, y, x, DEV_LOGX,
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LUT_C, 6, lut_str, ZTERM);
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*(uint32_t*)(u8_p+27*FRAME_SIZE+byte_off) = 0;
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*(uint32_t*)(u8_p+28*FRAME_SIZE+byte_off) = 0;
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}
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// D6_LUT
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u64 = read_lut64(u8_p + 29*FRAME_SIZE, byte_off*8);
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{ int logic_base[6] = {0,1,0,0,0,1};
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lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 0); }
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if (*lut_str) {
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rc = fdev_logic_set_lut(model, y, x, DEV_LOGX,
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LUT_D, 6, lut_str, ZTERM);
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*(uint32_t*)(u8_p+29*FRAME_SIZE+byte_off) = 0;
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*(uint32_t*)(u8_p+30*FRAME_SIZE+byte_off) = 0;
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}
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}
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}
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}
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return 0;
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fail:
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return rc;
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}
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static int bitpos_is_set(struct extract_state* es, int y, int x,
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struct xc6_routing_bitpos* swpos, int* is_set)
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{
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int row_num, row_pos, start_in_frame, two_bits_val, rc;
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*is_set = 0;
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is_in_row(es->model, y, &row_num, &row_pos);
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if (row_num == -1 || row_pos == -1
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|| row_pos == HCLK_POS) FAIL(EINVAL);
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if (row_pos > HCLK_POS)
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start_in_frame = (row_pos-1)*64 + 16;
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else
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start_in_frame = row_pos*64;
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if (swpos->minor == 20) {
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two_bits_val = (get_bit(es->bits, row_num, es->model->x_major[x],
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20, start_in_frame + swpos->two_bits_o) << 1)
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| (get_bit(es->bits, row_num, es->model->x_major[x],
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20, start_in_frame + swpos->two_bits_o+1) << 2);
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if (two_bits_val != swpos->two_bits_val)
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return 0;
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if (!get_bit(es->bits, row_num, es->model->x_major[x], 20,
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start_in_frame + swpos->one_bit_o))
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return 0;
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} else {
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two_bits_val =
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(get_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->two_bits_o/2) << 1)
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| (get_bit(es->bits, row_num, es->model->x_major[x], swpos->minor+1,
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start_in_frame + swpos->two_bits_o/2) << 2);
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if (two_bits_val != swpos->two_bits_val)
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return 0;
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if (!get_bit(es->bits, row_num, es->model->x_major[x],
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swpos->minor + (swpos->one_bit_o&1),
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start_in_frame + swpos->one_bit_o/2))
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return 0;
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}
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*is_set = 1;
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return 0;
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fail:
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return rc;
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}
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static int bitpos_clear_bits(struct extract_state* es, int y, int x,
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struct xc6_routing_bitpos* swpos)
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{
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int row_num, row_pos, start_in_frame, rc;
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is_in_row(es->model, y, &row_num, &row_pos);
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if (row_num == -1 || row_pos == -1
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|| row_pos == HCLK_POS) FAIL(EINVAL);
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if (row_pos > HCLK_POS)
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start_in_frame = (row_pos-1)*64 + 16;
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else
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start_in_frame = row_pos*64;
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if (swpos->minor == 20) {
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->two_bits_o);
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->two_bits_o+1);
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->one_bit_o);
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} else {
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor,
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start_in_frame + swpos->two_bits_o/2);
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor + 1,
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start_in_frame + swpos->two_bits_o/2);
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clear_bit(es->bits, row_num, es->model->x_major[x], swpos->minor + (swpos->one_bit_o&1),
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start_in_frame + swpos->one_bit_o/2);
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}
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return 0;
|
|
fail:
|
|
return rc;
|
|
}
|
|
|
|
static int bitpos_set_bits(struct fpga_bits* bits, struct fpga_model* model,
|
|
int y, int x, struct xc6_routing_bitpos* swpos)
|
|
{
|
|
int row_num, row_pos, start_in_frame, rc;
|
|
|
|
is_in_row(model, y, &row_num, &row_pos);
|
|
if (row_num == -1 || row_pos == -1
|
|
|| row_pos == HCLK_POS) FAIL(EINVAL);
|
|
if (row_pos > HCLK_POS)
|
|
start_in_frame = (row_pos-1)*64 + 16;
|
|
else
|
|
start_in_frame = row_pos*64;
|
|
|
|
if (swpos->minor == 20) {
|
|
if (swpos->two_bits_val & 0x02)
|
|
set_bit(bits, row_num, model->x_major[x], swpos->minor,
|
|
start_in_frame + swpos->two_bits_o);
|
|
if (swpos->two_bits_val & 0x01)
|
|
set_bit(bits, row_num, model->x_major[x], swpos->minor,
|
|
start_in_frame + swpos->two_bits_o+1);
|
|
set_bit(bits, row_num, model->x_major[x], swpos->minor,
|
|
start_in_frame + swpos->one_bit_o);
|
|
} else {
|
|
if (swpos->two_bits_val & 0x02)
|
|
set_bit(bits, row_num, model->x_major[x], swpos->minor,
|
|
start_in_frame + swpos->two_bits_o/2);
|
|
if (swpos->two_bits_val & 0x01)
|
|
set_bit(bits, row_num, model->x_major[x], swpos->minor + 1,
|
|
start_in_frame + swpos->two_bits_o/2);
|
|
set_bit(bits, row_num, model->x_major[x], swpos->minor + (swpos->one_bit_o&1),
|
|
start_in_frame + swpos->one_bit_o/2);
|
|
}
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|
|
|
|
static int extract_routing_switches(struct extract_state* es, int y, int x)
|
|
{
|
|
struct fpga_tile* tile;
|
|
swidx_t sw_idx;
|
|
int i, is_set, rc;
|
|
|
|
tile = YX_TILE(es->model, y, x);
|
|
|
|
for (i = 0; i < es->model->num_bitpos; i++) {
|
|
rc = bitpos_is_set(es, y, x, &es->model->sw_bitpos[i], &is_set);
|
|
if (rc) FAIL(rc);
|
|
if (!is_set) continue;
|
|
|
|
sw_idx = fpga_switch_lookup(es->model, y, x,
|
|
fpga_wire2str_i(es->model, es->model->sw_bitpos[i].from),
|
|
fpga_wire2str_i(es->model, es->model->sw_bitpos[i].to));
|
|
if (sw_idx == NO_SWITCH) FAIL(EINVAL);
|
|
// todo: es->model->sw_bitpos[i].bidir handling
|
|
|
|
if (tile->switches[sw_idx] & SWITCH_BIDIRECTIONAL)
|
|
HERE();
|
|
if (tile->switches[sw_idx] & SWITCH_USED)
|
|
HERE();
|
|
if (es->num_yx_pos >= MAX_YX_SWITCHES)
|
|
{ FAIL(ENOTSUP); }
|
|
es->yx_pos[es->num_yx_pos].y = y;
|
|
es->yx_pos[es->num_yx_pos].x = x;
|
|
es->yx_pos[es->num_yx_pos].idx = sw_idx;
|
|
es->num_yx_pos++;
|
|
rc = bitpos_clear_bits(es, y, x, &es->model->sw_bitpos[i]);
|
|
if (rc) FAIL(rc);
|
|
}
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|
|
|
|
static int extract_switches(struct extract_state* es)
|
|
{
|
|
int x, y, rc;
|
|
|
|
for (x = 0; x < es->model->x_width; x++) {
|
|
for (y = 0; y < es->model->y_height; y++) {
|
|
if (is_atx(X_ROUTING_COL, es->model, x)
|
|
&& y >= TOP_IO_TILES
|
|
&& y < es->model->y_height-BOT_IO_TILES
|
|
&& !is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
|
|
es->model, y)) {
|
|
rc = extract_routing_switches(es, y, x);
|
|
if (rc) FAIL(rc);
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|
|
|
|
static int construct_extract_state(struct extract_state* es,
|
|
struct fpga_model* model)
|
|
{
|
|
memset(es, 0, sizeof(*es));
|
|
es->model = model;
|
|
return 0;
|
|
}
|
|
|
|
int extract_model(struct fpga_model* model, struct fpga_bits* bits)
|
|
{
|
|
struct extract_state es;
|
|
net_idx_t net_idx;
|
|
int i, rc;
|
|
|
|
rc = construct_extract_state(&es, model);
|
|
if (rc) FAIL(rc);
|
|
es.bits = bits;
|
|
for (i = 0; i < sizeof(s_default_bits)/sizeof(s_default_bits[0]); i++) {
|
|
if (!get_bitp(bits, &s_default_bits[i]))
|
|
FAIL(EINVAL);
|
|
clear_bitp(bits, &s_default_bits[i]);
|
|
}
|
|
|
|
rc = extract_iobs(model, bits);
|
|
if (rc) FAIL(rc);
|
|
rc = extract_logic(model, bits);
|
|
if (rc) FAIL(rc);
|
|
rc = extract_switches(&es);
|
|
if (rc) FAIL(rc);
|
|
|
|
// turn switches into nets
|
|
if (model->nets)
|
|
HERE(); // should be empty here
|
|
for (i = 0; i < es.num_yx_pos; i++) {
|
|
rc = fnet_new(model, &net_idx);
|
|
if (rc) FAIL(rc);
|
|
rc = fnet_add_sw(model, net_idx, es.yx_pos[i].y,
|
|
es.yx_pos[i].x, &es.yx_pos[i].idx, 1);
|
|
if (rc) FAIL(rc);
|
|
}
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|
|
|
|
int printf_swbits(struct fpga_model* model)
|
|
{
|
|
char bit_str[129];
|
|
int i, j, width;
|
|
|
|
for (i = 0; i < model->num_bitpos; i++) {
|
|
|
|
width = (model->sw_bitpos[i].minor == 20) ? 64 : 128;
|
|
for (j = 0; j < width; j++)
|
|
bit_str[j] = '0';
|
|
bit_str[j] = 0;
|
|
|
|
if (model->sw_bitpos[i].two_bits_val & 2)
|
|
bit_str[model->sw_bitpos[i].two_bits_o] = '1';
|
|
if (model->sw_bitpos[i].two_bits_val & 1)
|
|
bit_str[model->sw_bitpos[i].two_bits_o+1] = '1';
|
|
bit_str[model->sw_bitpos[i].one_bit_o] = '1';
|
|
printf("mi%02i %s %s %s %s\n", model->sw_bitpos[i].minor,
|
|
fpga_wire2str(model->sw_bitpos[i].to),
|
|
bit_str,
|
|
fpga_wire2str(model->sw_bitpos[i].from),
|
|
model->sw_bitpos[i].bidir ? "<->" : "->");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int find_bitpos(struct fpga_model* model, int y, int x, swidx_t sw)
|
|
{
|
|
enum extra_wires from_w, to_w;
|
|
const char* from_str, *to_str;
|
|
int i;
|
|
|
|
from_str = fpga_switch_str(model, y, x, sw, SW_FROM);
|
|
to_str = fpga_switch_str(model, y, x, sw, SW_TO);
|
|
from_w = fpga_str2wire(from_str);
|
|
to_w = fpga_str2wire(to_str);
|
|
|
|
if (from_w == NO_WIRE || to_w == NO_WIRE) {
|
|
HERE();
|
|
return -1;
|
|
}
|
|
for (i = 0; i < model->num_bitpos; i++) {
|
|
if (model->sw_bitpos[i].from == from_w
|
|
&& model->sw_bitpos[i].to == to_w)
|
|
return i;
|
|
if (model->sw_bitpos[i].bidir
|
|
&& model->sw_bitpos[i].to == from_w
|
|
&& model->sw_bitpos[i].from == to_w) {
|
|
if (!fpga_switch_is_bidir(model, y, x, sw))
|
|
HERE();
|
|
return i;
|
|
}
|
|
}
|
|
fprintf(stderr, "#E switch %s (%i) to %s (%i) not in model\n",
|
|
from_str, from_w, to_str, to_w);
|
|
return -1;
|
|
}
|
|
|
|
static int write_switches(struct fpga_bits* bits, struct fpga_model* model)
|
|
{
|
|
struct fpga_tile* tile;
|
|
int x, y, i, bit_pos, rc;
|
|
|
|
for (x = 0; x < model->x_width; x++) {
|
|
for (y = 0; y < model->y_height; y++) {
|
|
if (!is_atx(X_ROUTING_COL, model, x)
|
|
|| y < TOP_IO_TILES
|
|
|| y >= model->y_height-BOT_IO_TILES
|
|
|| is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
|
|
model, y))
|
|
continue;
|
|
tile = YX_TILE(model, y, x);
|
|
// go through enabled switches, lookup in sw_bitpos
|
|
// and set bits
|
|
for (i = 0; i < tile->num_switches; i++) {
|
|
if (!(tile->switches[i] & SWITCH_USED))
|
|
continue;
|
|
bit_pos = find_bitpos(model, y, x, i);
|
|
if (bit_pos == -1)
|
|
continue;
|
|
rc = bitpos_set_bits(bits, model, y, x,
|
|
&model->sw_bitpos[bit_pos]);
|
|
if (rc) FAIL(rc);
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|
|
|
|
static int write_logic(struct fpga_bits* bits, struct fpga_model* model)
|
|
{
|
|
int dev_idx, row, row_pos, rc;
|
|
int x, y, byte_off;
|
|
struct fpga_device* dev;
|
|
uint8_t* u8_p;
|
|
|
|
for (x = LEFT_SIDE_WIDTH; x < model->x_width-RIGHT_SIDE_WIDTH; x++) {
|
|
if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x))
|
|
continue;
|
|
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
|
|
if (!has_device_type(model, y, x, DEV_LOGIC, LOGIC_M))
|
|
continue;
|
|
row = which_row(y, model);
|
|
row_pos = pos_in_row(y, model);
|
|
if (row == -1 || row_pos == -1 || row_pos == 8) {
|
|
HERE();
|
|
continue;
|
|
}
|
|
if (row_pos > 8) row_pos--;
|
|
u8_p = get_first_minor(bits, row, model->x_major[x]);
|
|
byte_off = row_pos * 8;
|
|
if (row_pos >= 8) byte_off += HCLK_BYTES;
|
|
|
|
// X device
|
|
dev_idx = fpga_dev_idx(model, y, x, DEV_LOGIC, DEV_LOGX);
|
|
if (dev_idx == NO_DEV) FAIL(EINVAL);
|
|
dev = FPGA_DEV(model, y, x, dev_idx);
|
|
if (!dev->instantiated)
|
|
continue;
|
|
printf("y%02i x%02i major %i byte_off %i\n", y, x, model->x_major[x], byte_off);
|
|
}
|
|
}
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|
|
|
|
int write_model(struct fpga_bits* bits, struct fpga_model* model)
|
|
{
|
|
int i, rc;
|
|
|
|
for (i = 0; i < sizeof(s_default_bits)/sizeof(s_default_bits[0]); i++)
|
|
set_bitp(bits, &s_default_bits[i]);
|
|
rc = write_switches(bits, model);
|
|
if (rc) FAIL(rc);
|
|
rc = write_iobs(bits, model);
|
|
if (rc) FAIL(rc);
|
|
rc = write_logic(bits, model);
|
|
if (rc) FAIL(rc);
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|