112 lines
2.7 KiB
C
112 lines
2.7 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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// The highest 4 bits are the binary revision and not
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// used when performing IDCODE verification.
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// ug380, Configuration Sequence, page 78
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#define IDCODE_MASK 0x0FFFFFFF
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#define XC6SLX4 0x04000093
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#define XC6SLX9 0x04001093
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#define XC6SLX16 0x04002093
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#define XC6SLX25 0x04004093
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#define XC6SLX25T 0x04024093
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#define XC6SLX45 0x04008093
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#define XC6SLX45T 0x04028093
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#define XC6SLX75 0x0400E093
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#define XC6SLX75T 0x0402E093
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#define XC6SLX100 0x04011093
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#define XC6SLX100T 0x04031093
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#define XC6SLX150 0x0401D093
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// xc6 configuration registers, documentation in ug380, page90
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enum fpga_config_reg {
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CRC = 0, FAR_MAJ, FAR_MIN, FDRI, FDRO, CMD, CTL, MASK, STAT, LOUT, COR1,
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COR2, PWRDN_REG, FLR, IDCODE, CWDT, HC_OPT_REG, CSBO = 18,
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GENERAL1, GENERAL2, GENERAL3, GENERAL4, GENERAL5, MODE_REG, PU_GWE,
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PU_GTS, MFWR, CCLK_FREQ, SEU_OPT, EXP_SIGN, RDBK_SIGN, BOOTSTS,
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EYE_MASK, CBC_REG
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};
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#define REG_NOOP -1 // pseudo register for noops
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#define COR1_DEF 0x3D00
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#define COR2_DEF 0x09EE
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#define MASK_DEF 0xCF
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#define MASK_SECURITY 0x0030
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#define CTL_DEF 0x81
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#define CCLK_FREQ_DEF 0x3CC8
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#define PWRDN_REG_DEF 0x0881
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#define EYE_MASK_DEF 0x0000
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#define HC_OPT_REG_DEF 0x1F
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#define CWDT_DEF 0xFFFF
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#define PU_GWE_DEF 0x005
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#define PU_GTS_DEF 0x004
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#define MODE_REG_DEF 0x100
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#define GENERAL1_DEF 0x0000
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#define GENERAL2_DEF 0x0000
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#define GENERAL3_DEF 0x0000
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#define GENERAL4_DEF 0x0000
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#define GENERAL5_DEF 0x0000
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#define SEU_OPT_DEF 0x1BE2
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#define EXP_SIGN_DEF 0
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#define FAR_MAJ_O 0
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#define FAR_MIN_O 1
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struct fpga_config_reg_rw
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{
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enum fpga_config_reg reg;
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union {
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int int_v;
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int far[2]; // 0 (FAR_MAJ_O) = major, 1 (FAR_MIN_O) = minor
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};
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};
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enum {
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CMD_NULL = 0, CMD_WCFG, CMD_MFW, CMD_LFRM, CMD_RCFG, CMD_START,
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CMD_RCRC = 7, CMD_AGHIGH, CMD_GRESTORE = 10, CMD_SHUTDOWN,
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CMD_DESYNC = 13, CMD_IPROG
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};
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#define MAX_HEADER_STR_LEN 128
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#define MAX_REG_ACTIONS 256
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#define BRAM_DATA_START (4*505*130)
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#define BRAM_DATA_LEN (4*144*130)
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struct fpga_config
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{
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char header_str[4][MAX_HEADER_STR_LEN];
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int num_regs;
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struct fpga_config_reg_rw reg[MAX_REG_ACTIONS];
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// indices into reg (initialized to -1)
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int num_regs_before_bits;
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int idcode_reg;
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int FLR_reg;
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int bits_len;
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uint8_t* bits;
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int bram_off;
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int IOB_off;
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};
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int read_bitfile(struct fpga_config* cfg, FILE* f);
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int extract_model(struct fpga_config* cfg, struct fpga_model* model);
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#define DUMP_HEADER_STR 0x0001
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#define DUMP_REGS 0x0002
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#define DUMP_BITS 0x0004
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int dump_config(struct fpga_config* cfg, int flags);
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void free_config(struct fpga_config* cfg);
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int write_bits(FILE* f, struct fpga_model* model);
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