431 lines
14 KiB
C
431 lines
14 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include <stdarg.h>
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#include "model.h"
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#include "control.h"
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void free_devices(struct fpga_model* model)
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{
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int i, j;
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for (i = 0; i < model->x_width * model->y_height; i++) {
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if (!model->tiles[i].num_devs)
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continue;
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EXIT(!model->tiles[i].devs);
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for (j = 0; j < model->tiles[i].num_devs; j++) {
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if (model->tiles[i].devs[j].type != DEV_LOGIC)
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continue;
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free(model->tiles[i].devs[i].logic.A6_lut);
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model->tiles[i].devs[i].logic.A6_lut = 0;
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free(model->tiles[i].devs[i].logic.B6_lut);
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model->tiles[i].devs[i].logic.B6_lut = 0;
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free(model->tiles[i].devs[i].logic.C6_lut);
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model->tiles[i].devs[i].logic.C6_lut = 0;
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free(model->tiles[i].devs[i].logic.D6_lut);
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model->tiles[i].devs[i].logic.D6_lut = 0;
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}
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free(model->tiles[i].devs);
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model->tiles[i].devs = 0;
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model->tiles[i].num_devs = 0;
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}
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}
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static int init_iob(struct fpga_model* model, int y, int x,
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int idx, int subtype)
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{
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struct fpga_tile* tile;
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const char* prefix;
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int type_idx, rc;
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tile = YX_TILE(model, y, x);
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tile->devs[idx].iob.subtype = subtype;
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type_idx = fpga_dev_typecount(model, y, x, DEV_IOB, idx);
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if (!y)
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prefix = "TIOB";
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else if (y == model->y_height - BOT_OUTER_ROW)
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prefix = "BIOB";
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else if (x == 0)
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prefix = "LIOB";
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else if (x == model->x_width - RIGHT_OUTER_O)
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prefix = "RIOB";
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else
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FAIL(EINVAL);
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snprintf(tile->devs[idx].iob.pinw_in_O,
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sizeof(tile->devs[idx].iob.pinw_in_O),
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"%s_O%i_PINW", prefix, type_idx);
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rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_in_O);
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if (rc) FAIL(rc);
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snprintf(tile->devs[idx].iob.pinw_in_T,
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sizeof(tile->devs[idx].iob.pinw_in_T),
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"%s_T%i_PINW", prefix, type_idx);
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rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_in_T);
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if (rc) FAIL(rc);
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snprintf(tile->devs[idx].iob.pinw_out_I,
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sizeof(tile->devs[idx].iob.pinw_out_I),
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"%s_IBUF%i_PINW", prefix, type_idx);
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rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_out_I);
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if (rc) FAIL(rc);
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snprintf(tile->devs[idx].iob.pinw_out_PADOUT,
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sizeof(tile->devs[idx].iob.pinw_out_PADOUT),
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"%s_PADOUT%i", prefix, type_idx);
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rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_out_PADOUT);
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if (rc) FAIL(rc);
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snprintf(tile->devs[idx].iob.pinw_in_DIFFI_IN,
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sizeof(tile->devs[idx].iob.pinw_in_DIFFI_IN),
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"%s_DIFFI_IN%i", prefix, type_idx);
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rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_in_DIFFI_IN);
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if (rc) FAIL(rc);
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snprintf(tile->devs[idx].iob.pinw_in_DIFFO_IN,
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sizeof(tile->devs[idx].iob.pinw_in_DIFFO_IN),
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"%s_DIFFO_IN%i", prefix, type_idx);
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rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_in_DIFFO_IN);
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if (rc) FAIL(rc);
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snprintf(tile->devs[idx].iob.pinw_out_DIFFO_OUT,
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sizeof(tile->devs[idx].iob.pinw_out_DIFFO_OUT),
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"%s_DIFFO_OUT%i", prefix, type_idx);
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rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_out_DIFFO_OUT);
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if (rc) FAIL(rc);
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if (!x && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 1)
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strcpy(tile->devs[idx].iob.pinw_out_PCI_RDY, "LIOB_TOP_PCI_RDY0");
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else if (!x && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 0)
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strcpy(tile->devs[idx].iob.pinw_out_PCI_RDY, "LIOB_BOT_PCI_RDY0");
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else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 0)
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strcpy(tile->devs[idx].iob.pinw_out_PCI_RDY, "RIOB_BOT_PCI_RDY0");
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else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 1)
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strcpy(tile->devs[idx].iob.pinw_out_PCI_RDY, "RIOB_TOP_PCI_RDY1");
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else {
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snprintf(tile->devs[idx].iob.pinw_out_PCI_RDY,
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sizeof(tile->devs[idx].iob.pinw_out_PCI_RDY),
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"%s_PCI_RDY%i", prefix, type_idx);
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}
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rc = add_connpt_name(model, y, x, tile->devs[idx].iob.pinw_out_PCI_RDY);
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if (rc) FAIL(rc);
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return 0;
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fail:
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return rc;
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}
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#define DEV_INCREMENT 8
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static int add_dev(struct fpga_model* model,
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int y, int x, int type, int subtype)
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{
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struct fpga_tile* tile;
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int new_dev_i;
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int rc;
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tile = YX_TILE(model, y, x);
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if (!(tile->num_devs % DEV_INCREMENT)) {
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void* new_ptr = realloc(tile->devs,
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(tile->num_devs+DEV_INCREMENT)*sizeof(*tile->devs));
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EXIT(!new_ptr);
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memset(new_ptr + tile->num_devs * sizeof(*tile->devs),
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0, DEV_INCREMENT*sizeof(*tile->devs));
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tile->devs = new_ptr;
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}
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new_dev_i = tile->num_devs;
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tile->num_devs++;
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// init new device
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tile->devs[new_dev_i].type = type;
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if (type == DEV_IOB) {
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rc = init_iob(model, y, x, new_dev_i, subtype);
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if (rc) FAIL(rc);
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} else if (type == DEV_LOGIC)
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tile->devs[new_dev_i].logic.subtype = subtype;
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return 0;
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fail:
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return rc;
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}
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int init_devices(struct fpga_model* model)
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{
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int x, y, i, j, rc;
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// DCM, PLL
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for (i = 0; i < model->cfg_rows; i++) {
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y = TOP_IO_TILES + HALF_ROW-1 + i*ROW_SIZE;
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if (y > model->center_y) y++; // central regs
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x = model->center_x-CENTER_CMTPLL_O;
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if (i%2) {
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if ((rc = add_dev(model, y, x, DEV_DCM, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_DCM, 0))) goto fail;
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} else
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if ((rc = add_dev(model, y, x, DEV_PLL, 0))) goto fail;
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}
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// BSCAN
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y = TOP_IO_TILES;
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x = model->x_width-RIGHT_IO_DEVS_O;
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if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
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// BSCAN, OCT_CALIBRATE
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y = TOP_IO_TILES+1;
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x = model->x_width-RIGHT_IO_DEVS_O;
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if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_OCT_CALIBRATE, 0))) goto fail;
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// ICAP, SPI_ACCESS, OCT_CALIBRATE
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y = model->y_height-BOT_IO_TILES-1;
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x = model->x_width-RIGHT_IO_DEVS_O;
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if ((rc = add_dev(model, y, x, DEV_ICAP, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_SPI_ACCESS, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_OCT_CALIBRATE, 0))) goto fail;
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// STARTUP, POST_CRC_INTERNAL, SLAVE_SPI, SUSPEND_SYNC
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y = model->y_height-BOT_IO_TILES-2;
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x = model->x_width-RIGHT_IO_DEVS_O;
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if ((rc = add_dev(model, y, x, DEV_STARTUP, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_POST_CRC_INTERNAL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_SLAVE_SPI, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_SUSPEND_SYNC, 0))) goto fail;
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// BUFGMUX
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y = model->center_y;
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x = model->center_x;
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for (i = 0; i < 16; i++)
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if ((rc = add_dev(model, y, x, DEV_BUFGMUX, 0))) goto fail;
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// BUFIO, BUFIO_FB, BUFPLL, BUFPLL_MCB
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y = TOP_OUTER_ROW;
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x = model->center_x-CENTER_CMTPLL_O;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
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for (j = 0; j < 8; j++) {
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if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
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}
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y = model->center_y;
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x = LEFT_OUTER_COL;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
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for (j = 0; j < 8; j++) {
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if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
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}
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y = model->center_y;
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x = model->x_width - RIGHT_OUTER_O;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
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for (j = 0; j < 8; j++) {
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if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
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}
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y = model->y_height - BOT_OUTER_ROW;
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x = model->center_x-CENTER_CMTPLL_O;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
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for (j = 0; j < 8; j++) {
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if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
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}
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// BUFH
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for (i = 0; i < model->cfg_rows; i++) {
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y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
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if (y > model->center_y) y++; // central regs
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x = model->center_x;
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for (j = 0; j < 32; j++)
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if ((rc = add_dev(model, y, x, DEV_BUFH, 0))) goto fail;
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}
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// BRAM
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for (x = 0; x < model->x_width; x++) {
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if (!is_atx(X_FABRIC_BRAM_COL, model, x))
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continue;
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for (y = TOP_IO_TILES; y < model->y_height-BOT_IO_TILES; y++) {
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if (!(YX_TILE(model, y, x)->flags & TF_BRAM_DEV))
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continue;
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if ((rc = add_dev(model, y, x, DEV_BRAM16, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_BRAM8, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_BRAM8, 0)))
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goto fail;
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}
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}
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// MACC
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for (x = 0; x < model->x_width; x++) {
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if (!is_atx(X_FABRIC_MACC_COL, model, x))
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continue;
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for (y = TOP_IO_TILES; y < model->y_height-BOT_IO_TILES; y++) {
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if (!(YX_TILE(model, y, x)->flags & TF_MACC_DEV))
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continue;
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if ((rc = add_dev(model, y, x, DEV_MACC, 0))) goto fail;
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}
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}
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// ILOGIC/OLOGIC/IODELAY
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for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
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if (!is_atx(X_LOGIC_COL, model, x)
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|| is_atx(X_ROUTING_NO_IO, model, x-1))
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continue;
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for (i = 0; i <= 1; i++) {
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y = TOP_IO_TILES+i;
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for (j = 0; j <= 1; j++) {
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if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
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goto fail;
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}
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y = model->y_height-BOT_IO_TILES-i-1;
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for (j = 0; j <= 1; j++) {
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if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
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goto fail;
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}
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}
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}
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_LEFT_WIRED, model, y)) {
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x = LEFT_IO_DEVS;
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for (j = 0; j <= 1; j++) {
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if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
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goto fail;
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}
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}
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if (is_aty(Y_RIGHT_WIRED, model, y)) {
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x = model->x_width-RIGHT_IO_DEVS_O;
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for (j = 0; j <= 1; j++) {
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if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
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goto fail;
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}
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}
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}
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// IOB
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for (x = 0; x < model->x_width; x++) {
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// Note that the order of sub-types IOBM and IOBS must match
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// the order in the control.c sitename arrays.
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if (is_atx(X_OUTER_LEFT, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!is_aty(Y_LEFT_WIRED, model, y))
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continue;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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}
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}
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if (is_atx(X_OUTER_RIGHT, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!is_aty(Y_RIGHT_WIRED, model, y))
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continue;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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}
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}
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if (is_atx(X_FABRIC_LOGIC_ROUTING_COL|X_CENTER_ROUTING_COL, model, x)
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&& !is_atx(X_ROUTING_NO_IO, model, x)) {
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y = TOP_OUTER_ROW;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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y = model->y_height-BOT_OUTER_ROW;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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}
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}
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// TIEOFF
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y = model->center_y;
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x = LEFT_OUTER_COL;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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y = model->center_y;
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x = model->x_width-RIGHT_OUTER_O;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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y = TOP_OUTER_ROW;
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x = model->center_x-1;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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y = model->y_height-BOT_OUTER_ROW;
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x = model->center_x-CENTER_CMTPLL_O;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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for (x = 0; x < model->x_width; x++) {
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if (is_atx(X_LEFT_IO_DEVS_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!is_aty(Y_LEFT_WIRED, model, y))
|
|
continue;
|
|
if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
|
|
}
|
|
}
|
|
if (is_atx(X_RIGHT_IO_DEVS_COL, model, x)) {
|
|
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
|
|
if (!is_aty(Y_RIGHT_WIRED, model, y))
|
|
continue;
|
|
if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
|
|
}
|
|
}
|
|
if (is_atx(X_CENTER_CMTPLL_COL, model, x)) {
|
|
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
|
|
if (!(YX_TILE(model, y, x)->flags & TF_PLL_DEV))
|
|
continue;
|
|
if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
|
|
|
|
}
|
|
}
|
|
if (is_atx(X_ROUTING_COL, model, x)) {
|
|
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
|
|
if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
|
|
model, y))
|
|
continue;
|
|
if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
|
|
}
|
|
}
|
|
if (is_atx(X_LOGIC_COL, model, x)
|
|
&& !is_atx(X_ROUTING_NO_IO, model, x-1)) {
|
|
for (i = 0; i <= 1; i++) {
|
|
y = TOP_IO_TILES+i;
|
|
if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
|
|
y = model->y_height-BOT_IO_TILES-i-1;
|
|
if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
|
|
}
|
|
}
|
|
}
|
|
// LOGIC
|
|
for (x = 0; x < model->x_width; x++) {
|
|
if (!is_atx(X_LOGIC_COL, model, x))
|
|
continue;
|
|
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
|
|
// M and L are at index 0 (DEV_LOGM and DEV_LOGL), X is at index 1 (DEV_LOGX).
|
|
if (YX_TILE(model, y, x)->flags & TF_LOGIC_XM_DEV) {
|
|
if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_M))) goto fail;
|
|
if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_X))) goto fail;
|
|
}
|
|
if (YX_TILE(model, y, x)->flags & TF_LOGIC_XL_DEV) {
|
|
if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_L))) goto fail;
|
|
if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_X))) goto fail;
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|