274 lines
9.7 KiB
C
274 lines
9.7 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include <stdarg.h>
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#include "model.h"
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int init_devices(struct fpga_model* model)
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{
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int x, y, i, j;
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struct fpga_tile* tile;
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// DCM, PLL_ADV
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for (i = 0; i < model->cfg_rows; i++) {
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y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
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if (y > model->center_y) y++; // central regs
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tile = YX_TILE(model, y-1, model->center_x-CENTER_CMTPLL_O);
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if (i%2) {
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tile->devices[tile->num_devices++].type = DEV_DCM;
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tile->devices[tile->num_devices++].type = DEV_DCM;
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} else
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tile->devices[tile->num_devices++].type = DEV_PLL_ADV;
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}
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// BSCAN
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tile = YX_TILE(model, TOP_IO_TILES, model->x_width-RIGHT_IO_DEVS_O);
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tile->devices[tile->num_devices++].type = DEV_BSCAN;
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tile->devices[tile->num_devices++].type = DEV_BSCAN;
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// BSCAN, OCT_CALIBRATE
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tile = YX_TILE(model, TOP_IO_TILES+1, model->x_width-RIGHT_IO_DEVS_O);
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tile->devices[tile->num_devices++].type = DEV_BSCAN;
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tile->devices[tile->num_devices++].type = DEV_BSCAN;
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tile->devices[tile->num_devices++].type = DEV_OCT_CALIBRATE;
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// ICAP, SPI_ACCESS, OCT_CALIBRATE
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tile = YX_TILE(model, model->y_height-BOT_IO_TILES-1,
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model->x_width-RIGHT_IO_DEVS_O);
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tile->devices[tile->num_devices++].type = DEV_ICAP;
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tile->devices[tile->num_devices++].type = DEV_SPI_ACCESS;
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tile->devices[tile->num_devices++].type = DEV_OCT_CALIBRATE;
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// STARTUP, POST_CRC_INTERNAL, SLAVE_SPI, SUSPEND_SYNC
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tile = YX_TILE(model, model->y_height-BOT_IO_TILES-2,
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model->x_width-RIGHT_IO_DEVS_O);
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tile->devices[tile->num_devices++].type = DEV_STARTUP;
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tile->devices[tile->num_devices++].type = DEV_POST_CRC_INTERNAL;
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tile->devices[tile->num_devices++].type = DEV_SLAVE_SPI;
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tile->devices[tile->num_devices++].type = DEV_SUSPEND_SYNC;
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// BUFGMUX
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tile = YX_TILE(model, model->center_y, model->center_x);
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for (i = 0; i < 16; i++)
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tile->devices[tile->num_devices++].type = DEV_BUFGMUX;
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// BUFIO, BUFIO_FB, BUFPLL, BUFPLL_MCB
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tile = YX_TILE(model, TOP_OUTER_ROW, model->center_x-CENTER_CMTPLL_O);
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
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for (j = 0; j < 8; j++) {
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tile->devices[tile->num_devices++].type = DEV_BUFIO;
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tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
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}
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tile = YX_TILE(model, model->center_y, LEFT_OUTER_COL);
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
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for (j = 0; j < 8; j++) {
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tile->devices[tile->num_devices++].type = DEV_BUFIO;
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tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
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}
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tile = YX_TILE(model, model->center_y, model->x_width - RIGHT_OUTER_O);
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
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for (j = 0; j < 8; j++) {
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tile->devices[tile->num_devices++].type = DEV_BUFIO;
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tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
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}
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tile = YX_TILE(model, model->y_height - BOT_OUTER_ROW, model->center_x-CENTER_CMTPLL_O);
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
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for (j = 0; j < 8; j++) {
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tile->devices[tile->num_devices++].type = DEV_BUFIO;
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tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
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}
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// BUFH
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for (i = 0; i < model->cfg_rows; i++) {
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y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
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if (y > model->center_y) y++; // central regs
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tile = YX_TILE(model, y, model->center_x);
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for (j = 0; j < 32; j++)
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tile->devices[tile->num_devices++].type = DEV_BUFH;
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}
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// BRAM
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for (x = 0; x < model->x_width; x++) {
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if (is_atx(X_FABRIC_BRAM_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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tile = YX_TILE(model, y, x);
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if (tile->flags & TF_BRAM_DEV) {
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tile->devices[tile->num_devices++].type = DEV_BRAM16;
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tile->devices[tile->num_devices++].type = DEV_BRAM8;
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tile->devices[tile->num_devices++].type = DEV_BRAM8;
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}
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}
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}
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}
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// MACC
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for (x = 0; x < model->x_width; x++) {
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if (is_atx(X_FABRIC_MACC_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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tile = YX_TILE(model, y, x);
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if (tile->flags & TF_MACC_DEV)
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tile->devices[tile->num_devices++].type = DEV_MACC;
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}
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}
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}
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// ILOGIC/OLOGIC/IODELAY
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for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
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if (is_atx(X_LOGIC_COL, model, x)
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&& !is_atx(X_ROUTING_NO_IO, model, x-1)) {
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for (i = 0; i <= 1; i++) {
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tile = YX_TILE(model, TOP_IO_TILES+i, x);
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for (j = 0; j <= 1; j++) {
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tile->devices[tile->num_devices++].type = DEV_ILOGIC;
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tile->devices[tile->num_devices++].type = DEV_OLOGIC;
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tile->devices[tile->num_devices++].type = DEV_IODELAY;
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}
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tile = YX_TILE(model, model->y_height-BOT_IO_TILES-i-1, x);
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for (j = 0; j <= 1; j++) {
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tile->devices[tile->num_devices++].type = DEV_ILOGIC;
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tile->devices[tile->num_devices++].type = DEV_OLOGIC;
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tile->devices[tile->num_devices++].type = DEV_IODELAY;
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}
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}
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}
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}
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_LEFT_WIRED, model, y)) {
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tile = YX_TILE(model, y, LEFT_IO_DEVS);
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for (j = 0; j <= 1; j++) {
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tile->devices[tile->num_devices++].type = DEV_ILOGIC;
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tile->devices[tile->num_devices++].type = DEV_OLOGIC;
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tile->devices[tile->num_devices++].type = DEV_IODELAY;
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}
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}
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if (is_aty(Y_RIGHT_WIRED, model, y)) {
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tile = YX_TILE(model, y, model->x_width-RIGHT_IO_DEVS_O);
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for (j = 0; j <= 1; j++) {
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tile->devices[tile->num_devices++].type = DEV_ILOGIC;
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tile->devices[tile->num_devices++].type = DEV_OLOGIC;
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tile->devices[tile->num_devices++].type = DEV_IODELAY;
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}
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}
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}
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// IOB
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for (x = 0; x < model->x_width; x++) {
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if (is_atx(X_OUTER_LEFT, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_LEFT_WIRED, model, y)) {
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tile = YX_TILE(model, y, x);
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tile->devices[tile->num_devices++].type = DEV_IOBM;
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tile->devices[tile->num_devices++].type = DEV_IOBS;
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}
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}
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}
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if (is_atx(X_OUTER_RIGHT, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_RIGHT_WIRED, model, y)) {
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tile = YX_TILE(model, y, x);
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tile->devices[tile->num_devices++].type = DEV_IOBM;
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tile->devices[tile->num_devices++].type = DEV_IOBS;
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}
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}
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}
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if (is_atx(X_FABRIC_LOGIC_ROUTING_COL|X_CENTER_ROUTING_COL, model, x)
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&& !is_atx(X_ROUTING_NO_IO, model, x)) {
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tile = YX_TILE(model, TOP_OUTER_ROW, x);
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tile->devices[tile->num_devices++].type = DEV_IOBM;
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tile->devices[tile->num_devices++].type = DEV_IOBM;
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tile->devices[tile->num_devices++].type = DEV_IOBS;
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tile->devices[tile->num_devices++].type = DEV_IOBS;
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tile = YX_TILE(model, model->y_height-BOT_OUTER_ROW, x);
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tile->devices[tile->num_devices++].type = DEV_IOBM;
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tile->devices[tile->num_devices++].type = DEV_IOBM;
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tile->devices[tile->num_devices++].type = DEV_IOBS;
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tile->devices[tile->num_devices++].type = DEV_IOBS;
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}
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}
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// TIEOFF
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tile = YX_TILE(model, model->center_y, LEFT_OUTER_COL);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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tile = YX_TILE(model, model->center_y, model->x_width-RIGHT_OUTER_O);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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tile = YX_TILE(model, TOP_OUTER_ROW, model->center_x-1);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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tile = YX_TILE(model, model->y_height-BOT_OUTER_ROW, model->center_x-CENTER_CMTPLL_O);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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for (x = 0; x < model->x_width; x++) {
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if (is_atx(X_LEFT_IO_DEVS_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_LEFT_WIRED, model, y)) {
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tile = YX_TILE(model, y, x);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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}
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}
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}
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if (is_atx(X_RIGHT_IO_DEVS_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_RIGHT_WIRED, model, y)) {
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tile = YX_TILE(model, y, x);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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}
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}
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}
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if (is_atx(X_CENTER_CMTPLL_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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tile = YX_TILE(model, y, x);
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if (tile->flags & TF_PLL_DEV)
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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}
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}
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if (is_atx(X_ROUTING_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y))
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continue;
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tile = YX_TILE(model, y, x);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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}
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}
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if (is_atx(X_LOGIC_COL, model, x)
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&& !is_atx(X_ROUTING_NO_IO, model, x-1)) {
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for (i = 0; i <= 1; i++) {
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tile = YX_TILE(model, TOP_IO_TILES+i, x);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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tile = YX_TILE(model, model->y_height-BOT_IO_TILES-i-1, x);
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tile->devices[tile->num_devices++].type = DEV_TIEOFF;
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}
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}
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}
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// LOGIC
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for (x = 0; x < model->x_width; x++) {
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if (is_atx(X_LOGIC_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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tile = YX_TILE(model, y, x);
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if (tile->flags & TF_LOGIC_XM_DEV) {
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tile->devices[tile->num_devices++].type = DEV_LOGIC_X;
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tile->devices[tile->num_devices++].type = DEV_LOGIC_M;
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}
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if (tile->flags & TF_LOGIC_XL_DEV) {
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tile->devices[tile->num_devices++].type = DEV_LOGIC_X;
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tile->devices[tile->num_devices++].type = DEV_LOGIC_L;
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}
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}
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}
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}
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return 0;
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}
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