59 lines
2.0 KiB
Plaintext
59 lines
2.0 KiB
Plaintext
Design Principles
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- small independent command line utilities, no GUI
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- plain C, no C++
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- simple Makefiles
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- text-based file formats
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- no documentation - please read the sources
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- automatic test suite
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Libraries
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(most is to-be-done)
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- libfpga-model memory-only representation of an FPGA
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- libfpga-bit reads and writes .bit bitstream files
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- libfpga-floorplan reads and writes .fp floorplan files
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- libfpga-control programmatic access to libfpga-model
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- libfpga-design larger design elements on top of libfpga-control
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- libfpga-test test harness for model, control and design
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Design Utilities
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- new_fp creates empty .fp floorplan file
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- fp2bit converts .fp floorplan into .bit bitstream
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- bit2fp converts .bit bitstream into .fp floorplan
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- draw_svg_tiles draws a simple .svg showing tile types
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fpgatools Development Utilities
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- autotest executes test suite
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- sort_seq sorts line-based text file by sequence numbers in strings
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- merge_seq merges a pre-sorted text file into wire sequences
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- pair2net reads the first two words per line and builds nets
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- hstrrep high-speed hashed array based search and replace util
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TODO (as of 2012-08, expected time to delivery: months to years)
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* support chips other than xc6slx9, like slx45, slx150
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* support xc7a100
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* many more test cases for autotester
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* smarter autotester that can remember and verify groups of tests,
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automatically oversee test execution, etc.
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* Debian packages libfpga, libfpga-doc, fpgatools
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* many more cases in logic block configuration
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* configuration of bram and macc blocks, bram initialization data
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* routing switches
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* many more cases in model of switches and inter-tile connections
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* write standard design elements for libfpga-design library
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* support lm32 or openrisc core, either via libfpga or iverilog backend
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* iverilog fpga backend
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ChangeLog
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2012-08-20
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* Beginning of full fidelity circle with model, floorplan, conversion from
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and to bitstream format.
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2012-06-03
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* Project started.
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