117 lines
3.9 KiB
C
117 lines
3.9 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include "model.h"
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#include "floorplan.h"
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#include "control.h"
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/*
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This C design corresponds to the following Verilog:
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module blinking(input clk, output led);
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// synthesis attribute LOC clk "P55 | IOSTANDARD = LVCMOS33"
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// synthesis attribute LOC led "P48 | SLEW = QUIETIO | DRIVE = 8"
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reg [14:0] counter;
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always @(posedge clk) counter <= counter + 1;
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assign led = counter[14];
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endmodule
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*/
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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int iob_clk_y, iob_clk_x, iob_clk_type_idx;
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int iob_led_y, iob_led_x, iob_led_type_idx;
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int logic_y, logic_x, logic_type_idx;
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struct fpgadev_logic logic_cfg;
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net_idx_t inA_net, inB_net, out_net;
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fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
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XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING);
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fpga_find_iob(&model, "P55", &iob_clk_y, &iob_clk_x, &iob_clk_type_idx);
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fdev_iob_input(&model, iob_clk_y, iob_clk_x, iob_clk_type_idx,
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IO_LVCMOS33);
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fpga_find_iob(&model, "P48", &iob_led_y, &iob_led_x, &iob_led_type_idx);
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fdev_iob_output(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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IO_LVCMOS25);
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fdev_iob_slew(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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SLEW_QUIETIO);
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fdev_iob_drive(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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8);
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#if 0
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logic_y = 55-58
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logic_x = 13;
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logic_type_idx = DEV_LOG_X;
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if ((rc = fdev_logic_a2d_lut(&model, logic_y, logic_x, logic_type_idx,
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LUT_D, 6, "A3*A5", ZTERM))) FAIL(rc);
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memset(&logic_cfg, 0, sizeof(logic_cfg));
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logic_cfg.a2d[LUT_A].lut6 = "(A6+~A6)*(~A5)";
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logic_cfg.a2d[LUT_A].lut5 = "1";
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logic_cfg.a2d[LUT_A].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_A].ff = FF_FF;
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logic_cfg.a2d[LUT_A].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_A].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_B].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_B].lut5 = "1";
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logic_cfg.a2d[LUT_B].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_B].ff = FF_FF;
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logic_cfg.a2d[LUT_B].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_B].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_C].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_C].lut5 = "1";
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logic_cfg.a2d[LUT_C].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_C].ff = FF_FF;
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logic_cfg.a2d[LUT_C].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_C].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_D].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_D].lut5 = "1";
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logic_cfg.a2d[LUT_D].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_D].ff = FF_FF;
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logic_cfg.a2d[LUT_D].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_D].ff_srinit = FF_SRINIT0;
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logic_cfg.clk_inv = CLKINV_CLK;
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logic_cfg.sync_attr = SYNCATTR_ASYNC;
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logic_cfg.precyinit = PRECYINIT_0;
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logic_cfg.cout_used = 1;
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rc = fdev_logic_setconf(tstate->model, y, x, type_idx, logic_cfg);
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if (rc) FAIL(rc);
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if ((rc = fnet_new(&model, &inA_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inA_net, iob_inA_y, iob_inA_x,
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DEV_IOB, iob_inA_type_idx, IOB_OUT_I))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inA_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LI_D3))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, inA_net))) FAIL(rc);
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if ((rc = fnet_new(&model, &inB_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inB_net, iob_inB_y, iob_inB_x,
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DEV_IOB, iob_inB_type_idx, IOB_OUT_I))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inB_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LI_D5))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, inB_net))) FAIL(rc);
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if ((rc = fnet_new(&model, &out_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, out_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LO_D))) FAIL(rc);
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if ((rc = fnet_add_port(&model, out_net, iob_out_y, iob_out_x,
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DEV_IOB, iob_out_type_idx, IOB_IN_O))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, out_net))) FAIL(rc);
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#endif
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write_floorplan(stdout, &model, FP_DEFAULT);
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return fpga_free_model(&model);
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}
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