424 lines
14 KiB
C
424 lines
14 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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// The highest 4 bits are the binary revision and not
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// used when performing IDCODE verification.
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// ug380, Configuration Sequence, page 78
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#define IDCODE_MASK 0x0FFFFFFF
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#define XC6SLX4 0x04000093
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#define XC6SLX9 0x04001093
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#define XC6SLX16 0x04002093
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#define XC6SLX25 0x04004093
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#define XC6SLX25T 0x04024093
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#define XC6SLX45 0x04008093
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#define XC6SLX45T 0x04028093
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#define XC6SLX75 0x0400E093
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#define XC6SLX75T 0x0402E093
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#define XC6SLX100 0x04011093
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#define XC6SLX100T 0x04031093
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#define XC6SLX150 0x0401D093
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#define XC_MAX_MAJORS 400
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#define XC_MAX_TYPE2_ENTRIES 2000
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#define XC_MAX_MUI_POS 32
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#define XC_MAJ_ZERO 0x00000001
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#define XC_MAJ_LEFT 0x00000002
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#define XC_MAJ_CENTER 0x00000004
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#define XC_MAJ_RIGHT 0x00000008
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#define XC_MAJ_XM 0x00000010
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#define XC_MAJ_XL 0x00000020
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#define XC_MAJ_BRAM 0x00000040
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#define XC_MAJ_MACC 0x00000080
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#define XC_MAJ_TOP_BOT_IO 0x00000100
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#define XC_MAJ_GCLK_SEP 0x00000200
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struct xc_major_info
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{
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int flags;
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int minors;
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};
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#define XC_T2_IOB_PAD 0x00000001
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#define XC_T2_IOB_UNBONDED 0x00000002
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#define XC_T2_CENTER 0x00000004
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struct xc_type2_info
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{
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int flags;
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int val;
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};
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//
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// major_str
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// 'L' = X+L logic block
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// 'M' = X+M logic block
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// 'B' = block ram
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// 'D' = dsp (macc)
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// 'R' = registers and center IO/logic column
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//
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// 'n' = noio - can follow L or M to designate a logic
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// column without IO at top or bottom
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// 'g' = gclk - can follow LlMmBD to designate exactly one
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// place on the left and right side of the chip where
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// the global clock is separated into left and right
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// half (on each side of the chip, for a total of 4
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// vertical clock separations).
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// left_wiring and right_wiring are described with 16
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// characters for each row, order is top-down
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// 'W' = wired
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// 'U' = unwired
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//
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struct xc_die
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{
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int idcode;
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int num_rows;
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const char* left_wiring;
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const char* right_wiring;
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const char* major_str;
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int num_majors;
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struct xc_major_info majors[XC_MAX_MAJORS];
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int num_type2;
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struct xc_type2_info type2[XC_MAX_TYPE2_ENTRIES];
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int mcb_ypos;
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int num_mui;
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int mui_pos[XC_MAX_MUI_POS];
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int sel_logicin[16];
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};
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const struct xc_die* xc_die_info(int idcode);
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enum xc6_pkg { TQG144, FTG256, CSG324, FGG484 };
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#define XC6_NUM_GCLK_PINS 32
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struct xc6_pkg_info
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{
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enum xc6_pkg pkg;
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int num_gclk_pins;
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// negative side of differential pairs: even numbers
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// positive side of differential pairs: odd numbers
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const char* gclk_pin[XC6_NUM_GCLK_PINS];
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};
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const struct xc6_pkg_info *xc6_pkg_info(enum xc6_pkg pkg);
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#define FRAME_SIZE 130
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#define FRAMES_PER_ROW 505 // for slx4 and slx9
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#define PADDING_FRAMES_PER_ROW 2
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#define NUM_ROWS 4 // for slx9 and slx9
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#define FRAMES_DATA_START 0
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#define FRAMES_DATA_LEN (NUM_ROWS*FRAMES_PER_ROW*FRAME_SIZE)
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#define BRAM_DATA_START FRAMES_DATA_LEN
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#define BRAM_DATA_LEN (4*144*FRAME_SIZE)
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#define IOB_DATA_START (BRAM_DATA_START + BRAM_DATA_LEN)
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#define IOB_WORDS 896 // 16-bit words, for slx4 and slx9
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#define IOB_DATA_LEN (IOB_WORDS*2)
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#define IOB_ENTRY_LEN 8
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#define BITS_LEN (IOB_DATA_START+IOB_DATA_LEN)
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#define XC6_HCLK_BYTES 2
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#define XC6_HCLK_BITS (XC6_HCLK_BYTES*8)
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#define XC6_IOB_MASK_IO 0x00FF00FFFF000000
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#define XC6_IOB_MASK_IN_TYPE 0x000000000000F000
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#define XC6_IOB_MASK_SLEW 0x0000000000FF0000
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#define XC6_IOB_MASK_SUSPEND 0x000000000000001F
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#define XC6_IOB_INSTANTIATED 0x0000000000000080
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#define XC6_IOB_INPUT 0x00D0002400000000
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#define XC6_IOB_INPUT_LVCMOS33_25_LVTTL 0x000000000000E000
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#define XC6_IOB_INPUT_LVCMOS18_15_12 0x000000000000C000
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#define XC6_IOB_INPUT_LVCMOS18_15_12_JEDEC 0x0000000000002000
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#define XC6_IOB_INPUT_SSTL2_I 0x000000000000B000
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#define XC6_IOB_OUTPUT_LVCMOS33_25_DRIVE_2 0x001000B400000000
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#define XC6_IOB_OUTPUT_LVCMOS33_DRIVE_4 0x0070006C00000000
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#define XC6_IOB_OUTPUT_LVCMOS33_DRIVE_6 0x003000FC00000000
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#define XC6_IOB_OUTPUT_LVCMOS33_DRIVE_8 0x0040000000000000
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#define XC6_IOB_OUTPUT_LVCMOS33_DRIVE_12 0x0060008800000000
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#define XC6_IOB_OUTPUT_LVCMOS33_DRIVE_16 0x009800C600000000
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#define XC6_IOB_OUTPUT_LVCMOS33_DRIVE_24 0x0088007200000000
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#define XC6_IOB_OUTPUT_LVCMOS25_DRIVE_4 0x00B0006C00000000
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#define XC6_IOB_OUTPUT_LVCMOS25_DRIVE_6 0x004000FC00000000
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#define XC6_IOB_OUTPUT_LVCMOS25_DRIVE_8 0x0000000000000000
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#define XC6_IOB_OUTPUT_LVCMOS25_DRIVE_12 0x0058008800000000
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#define XC6_IOB_OUTPUT_LVCMOS25_DRIVE_16 0x00B800C600000000
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#define XC6_IOB_OUTPUT_LVCMOS25_DRIVE_24 0x0054007200000000
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#define XC6_IOB_OUTPUT_LVTTL_DRIVE_2 0x009000B400000000
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#define XC6_IOB_OUTPUT_LVTTL_DRIVE_4 0x00F0006C00000000
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#define XC6_IOB_OUTPUT_LVTTL_DRIVE_6 0x007000FC00000000
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#define XC6_IOB_OUTPUT_LVTTL_DRIVE_8 0x0030000000000000
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#define XC6_IOB_OUTPUT_LVTTL_DRIVE_12 0x0080008800000000
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#define XC6_IOB_OUTPUT_LVTTL_DRIVE_16 0x006000C600000000
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#define XC6_IOB_OUTPUT_LVTTL_DRIVE_24 0x0018007200000000
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#define XC6_IOB_OUTPUT_LVCMOS18_DRIVE_2 0x00F000B402000000
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#define XC6_IOB_OUTPUT_LVCMOS18_DRIVE_4 0x00C000AC02000000
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#define XC6_IOB_OUTPUT_LVCMOS18_DRIVE_6 0x00E000BC02000000
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#define XC6_IOB_OUTPUT_LVCMOS18_DRIVE_8 0x00D800A002000000
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#define XC6_IOB_OUTPUT_LVCMOS18_DRIVE_12 0x003800A802000000
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#define XC6_IOB_OUTPUT_LVCMOS18_DRIVE_16 0x002800A602000000
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#define XC6_IOB_OUTPUT_LVCMOS18_DRIVE_24 0x00A400A202000000
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#define XC6_IOB_OUTPUT_LVCMOS15_DRIVE_2 0x00B0007402000000
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#define XC6_IOB_OUTPUT_LVCMOS15_DRIVE_4 0x00E0000C02000000
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#define XC6_IOB_OUTPUT_LVCMOS15_DRIVE_6 0x0098005C02000000
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#define XC6_IOB_OUTPUT_LVCMOS15_DRIVE_8 0x00C8003002000000
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#define XC6_IOB_OUTPUT_LVCMOS15_DRIVE_12 0x00F4001802000000
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#define XC6_IOB_OUTPUT_LVCMOS15_DRIVE_16 0x002400D602000000
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#define XC6_IOB_OUTPUT_LVCMOS12_DRIVE_2 0x004000B402000000
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#define XC6_IOB_OUTPUT_LVCMOS12_DRIVE_4 0x0098006C02000000
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#define XC6_IOB_OUTPUT_LVCMOS12_DRIVE_6 0x008800FC02000000
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#define XC6_IOB_OUTPUT_LVCMOS12_DRIVE_8 0x0014000002000000
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#define XC6_IOB_OUTPUT_LVCMOS12_DRIVE_12 0x00FC008802000000
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#define XC6_IOB_OUTPUT_SSTL2_I 0x0040001C00000000
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#define XC6_IOB_IMUX_I_B 0x0000000000000400
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#define XC6_IOB_O_PINW 0x0000000000000100
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#define XC6_IOB_SLEW_SLOW 0x0000000000000000
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#define XC6_IOB_SLEW_FAST 0x0000000000330000
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#define XC6_IOB_SLEW_QUIETIO 0x0000000000660000
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#define XC6_IOB_SUSP_3STATE 0x0000000000000000
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#define XC6_IOB_SUSP_3STATE_OCT_ON 0x0000000000000001
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#define XC6_IOB_SUSP_3STATE_KEEPER 0x0000000000000002
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#define XC6_IOB_SUSP_3STATE_PULLUP 0x0000000000000004
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#define XC6_IOB_SUSP_3STATE_PULLDOWN 0x0000000000000008
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#define XC6_IOB_SUSP_LAST_VAL 0x0000000000000010
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int get_major_minors(int idcode, int major);
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enum major_type { MAJ_ZERO, MAJ_LEFT, MAJ_RIGHT, MAJ_CENTER,
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MAJ_LOGIC_XM, MAJ_LOGIC_XL, MAJ_BRAM, MAJ_MACC };
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enum major_type get_major_type(int idcode, int major);
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#define XC6_ZERO_MAJOR 0
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#define XC6_LEFTSIDE_MAJOR 1
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#define XC6_SLX9_RIGHTMOST_MAJOR 17
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int get_rightside_major(int idcode);
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int get_major_framestart(int idcode, int major);
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int get_frames_per_row(int idcode);
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int get_num_iobs(int idcode);
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const char* get_iob_sitename(int idcode, int idx);
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// returns -1 if sitename not found
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int find_iob_sitename(int idcode, const char* name);
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int xc_num_rows(int idcode);
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// The routing bitpos is relative to a tile, i.e. major (x)
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// and row/v64_i (y) are defined outside.
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struct xc6_routing_bitpos
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{
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// from and to are enum extra_wires values from model.h
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int from;
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int to;
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int bidir;
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// minors 0-19 are minor pairs, minor will be set
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// to the even beginning of the pair, two_bits_o and
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// one_bit_o are within 2*64 bits of the two minors.
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// Even bit offsets are from the first minor, odd bit
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// offsets from the second minor.
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// minor 20 is a regular single 64-bit minor.
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int minor; // 0,2,4,..18 for pairs, 20 for single-minor
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int two_bits_o; // 0-126 for pairs (even only), 0-62 for single-minor
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int two_bits_val; // 0-3
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int one_bit_o; // 1-6 positions up or down from two-bit pos
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};
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int get_xc6_routing_bitpos(struct xc6_routing_bitpos** bitpos, int* num_bitpos);
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void free_xc6_routing_bitpos(struct xc6_routing_bitpos* bitpos);
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#define XC6_LMAP_XM_M_A 0
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#define XC6_LMAP_XM_M_B 1
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#define XC6_LMAP_XM_M_C 0
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#define XC6_LMAP_XM_M_D 1
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#define XC6_LMAP_XM_X_A 2
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#define XC6_LMAP_XM_X_B 2
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#define XC6_LMAP_XM_X_C 3
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#define XC6_LMAP_XM_X_D 3
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#define XC6_LMAP_XL_L_A 3
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#define XC6_LMAP_XL_L_B 2
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#define XC6_LMAP_XL_L_C 3
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#define XC6_LMAP_XL_L_D 2
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#define XC6_LMAP_XL_X_A 2
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#define XC6_LMAP_XL_X_B 2
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#define XC6_LMAP_XL_X_C 3
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#define XC6_LMAP_XL_X_D 3
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// num_bits must be 32 or 64. If it is 32, the lower
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// 32 entries of map contain the bit positions for lut5,
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// the upper 32 entries of map the ones for lut6.
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// In either case 64 entries are written to map.
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void xc6_lut_bitmap(int lut_pos, int (*map)[64], int num_bits);
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//
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// logic configuration
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//
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//
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// Some things noteworthy for *not* having bits set:
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// cout_used, a_used-d_used, srinit=0, non-inverted clock,
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// async attribute, precyinit=0, ffmux=O6, cy0=X, enabling
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// 5Q-ff in X devices
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//
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// All offsets into vertical range of 64 bits per logic row.
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//
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// minor 20 (only bits 24-39 for logic config, 0-23 and 40-63
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// are for routing switches):
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#define XC6_MI20_LOGIC_MASK 0x000000FFFF000000ULL
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#define XC6_ML_D5_FFSRINIT_1 24
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#define XC6_X_D5_FFSRINIT_1 25
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#define XC6_ML_C5_FFSRINIT_1 29
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#define XC6_X_C_FFSRINIT_1 30
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#define XC6_X_C5_FFSRINIT_1 31
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#define XC6_ML_B5_FFSRINIT_1 32
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#define XC6_X_B5_FFSRINIT_1 34
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#define XC6_M_A_FFSRINIT_1 37 // M-device only
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#define XC6_X_A5_FFSRINIT_1 38
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#define XC6_ML_A5_FFSRINIT_1 39
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// minor 26 in XM, 25 in XL columns:
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// ML_D_CY0=DX -
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#define XC6_ML_D_CY0_O5 0 // implies lut5 on ML-D
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// X_D_OUTMUX=5Q - // implies lut5 on X-D
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#define XC6_X_D_OUTMUX_O5 1 // default-set, does not imply lut5
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// X_C_OUTMUX=5Q - // implies lut5 on X-C
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#define XC6_X_C_OUTMUX_O5 2 // default-set, does not imply lut5
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#define XC6_ML_D_FFSRINIT_1 3
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#define XC6_ML_C_FFSRINIT_1 4
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#define XC6_X_D_FFSRINIT_1 5
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// ML_C_CY0=CX -
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#define XC6_ML_C_CY0_O5 6 // implies lut5 on ML-C
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// X_B_OUTMUX=5Q - // implies lut5 on X-B
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#define XC6_X_B_OUTMUX_O5 7 // default-set, does not imply lut5
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#define XC6_ML_D_OUTMUX_MASK 0x0000000000000F00ULL
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#define XC6_ML_D_OUTMUX_O 8
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#define XC6_ML_D_OUTMUX_O6 1 // 0001
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#define XC6_ML_D_OUTMUX_XOR 2 // 0010
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#define XC6_ML_D_OUTMUX_O5 5 // 0101, implies lut5 on ML-D
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#define XC6_ML_D_OUTMUX_CY 6 // 0110
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#define XC6_ML_D_OUTMUX_5Q 8 // 1000, implies lut5 on ML-D
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#define XC6_ML_D_FFMUX_MASK 0x000000000000F000ULL
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#define XC6_ML_D_FFMUX_O 12
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#define XC6_ML_D_FFMUX_O6 0 // 0000
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#define XC6_ML_D_FFMUX_O5 1 // 0001, implies lut5 on ML-D
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#define XC6_ML_D_FFMUX_X 10 // 1010
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#define XC6_ML_D_FFMUX_XOR 12 // 1100
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#define XC6_ML_D_FFMUX_CY 13 // 1101
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#define XC6_X_CLK_B 16
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#define XC6_ML_ALL_LATCH 17
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#define XC6_ML_SR_USED 18
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#define XC6_ML_SYNC 19
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#define XC6_ML_CE_USED 20
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// X_D_FFMUX=O6 -
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#define XC6_X_D_FFMUX_X 21 // default-set, does not imply lut5
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// X_C_FFMUX=O6 -
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#define XC6_X_C_FFMUX_X 22 // default-set, does not imply lut5
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#define XC6_X_CE_USED 23
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#define XC6_ML_C_OUTMUX_MASK 0x000000000F000000ULL
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#define XC6_ML_C_OUTMUX_O 24
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#define XC6_ML_C_OUTMUX_XOR 1 // 0001
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#define XC6_ML_C_OUTMUX_O6 2 // 0010
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#define XC6_ML_C_OUTMUX_5Q 4 // 0100, implies lut5 on ML-C
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#define XC6_ML_C_OUTMUX_CY 9 // 1001
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#define XC6_ML_C_OUTMUX_O5 10 // 1010, implies lut5 on ML-C
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#define XC6_ML_C_OUTMUX_F7 12 // 1100
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#define XC6_ML_C_FFMUX_MASK 0x00000000F0000000ULL
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#define XC6_ML_C_FFMUX_O 28
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#define XC6_ML_C_FFMUX_O6 0 // 0000
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#define XC6_ML_C_FFMUX_O5 2 // 0010, implies lut5 on ML-C
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#define XC6_ML_C_FFMUX_X 5 // 0101
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#define XC6_ML_C_FFMUX_F7 7 // 0111
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#define XC6_ML_C_FFMUX_XOR 12 // 1100
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#define XC6_ML_C_FFMUX_CY 14 // 1110
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#define XC6_ML_B_OUTMUX_MASK 0x0000000F00000000ULL
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#define XC6_ML_B_OUTMUX_O 32
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#define XC6_ML_B_OUTMUX_5Q 2 // 0010, implies lut5 on ML-B
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#define XC6_ML_B_OUTMUX_F8 3 // 0011
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#define XC6_ML_B_OUTMUX_XOR 4 // 0100
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#define XC6_ML_B_OUTMUX_CY 5 // 0101
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#define XC6_ML_B_OUTMUX_O6 8 // 1000
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#define XC6_ML_B_OUTMUX_O5 9 // 1001, implies lut5 on ML-B
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// X_B_FFMUX=O6 -
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#define XC6_X_B_FFMUX_X 36 // default-set, does not imply lut5
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// X_A_FFMUX=O6 -
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#define XC6_X_A_FFMUX_X 37 // default-set, does not imply lut5
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#define XC6_X_B_FFSRINIT_1 38
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// X_A_OUTMUX=5Q - // implies lut5 on X-A
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#define XC6_X_A_OUTMUX_O5 39 // default-set, does not imply lut5
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#define XC6_X_SR_USED 40
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#define XC6_X_SYNC 41
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#define XC6_X_ALL_LATCH 42
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#define XC6_ML_CLK_B 43
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#define XC6_ML_B_FFMUX_MASK 0x0000F00000000000ULL
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#define XC6_ML_B_FFMUX_O 44
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#define XC6_ML_B_FFMUX_O6 0 // 0000
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#define XC6_ML_B_FFMUX_XOR 3 // 0011
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#define XC6_ML_B_FFMUX_O5 4 // 0100, implies lut5 on ML-B
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#define XC6_ML_B_FFMUX_CY 7 // 0111
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#define XC6_ML_B_FFMUX_X 10 // 1010
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#define XC6_ML_B_FFMUX_F8 14 // 1110
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#define XC6_ML_A_FFMUX_MASK 0x000F000000000000ULL
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#define XC6_ML_A_FFMUX_O 48
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#define XC6_ML_A_FFMUX_O6 0 // 0000
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#define XC6_ML_A_FFMUX_XOR 3 // 0011
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#define XC6_ML_A_FFMUX_X 5 // 0101
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#define XC6_ML_A_FFMUX_O5 8 // 1000, implies lut5 on ML-A
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#define XC6_ML_A_FFMUX_CY 11 // 1011
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#define XC6_ML_A_FFMUX_F7 13 // 1101
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#define XC6_ML_A_OUTMUX_MASK 0x00F0000000000000ULL
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#define XC6_ML_A_OUTMUX_O 52
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#define XC6_ML_A_OUTMUX_5Q 1 // 0001, implies lut5 on ML-A
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#define XC6_ML_A_OUTMUX_F7 3 // 0011
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#define XC6_ML_A_OUTMUX_XOR 4 // 0100
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#define XC6_ML_A_OUTMUX_CY 6 // 0110
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#define XC6_ML_A_OUTMUX_O6 8 // 1000
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#define XC6_ML_A_OUTMUX_O5 10 // 1010, implies lut5 on ML-A
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// ML_B_CY0=BX -
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#define XC6_ML_B_CY0_O5 56 // implies lut5 on ML-B
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#define XC6_ML_PRECYINIT_AX 57
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#define XC6_X_A_FFSRINIT_1 58
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// CIN_USED best corresponds to the cout->cout_n switch in the
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// next lower logic device (y+1).
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#define XC6_ML_CIN_USED 59
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// ML_PRECYINIT=0 -
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#define XC6_ML_PRECYINIT_1 60
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#define XC6_ML_B_FFSRINIT_1 61
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// ML_A_CY0=AX -
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#define XC6_ML_A_CY0_O5 62 // implies lut5 on ML-A
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#define XC6_L_A_FFSRINIT_1 63 // L-device only
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