86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include "model.h"
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#include "floorplan.h"
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#include "control.h"
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/*
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This C design corresponds to the following Verilog:
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module ver_and(input a, b, output y);
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// synthesis attribute LOC a "P45"
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// synthesis attribute LOC b "P46"
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// synthesis attribute LOC y "P48 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12"
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assign y = a & b;
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endmodule
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*/
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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int iob_inA_y, iob_inA_x, iob_inA_type_idx;
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int iob_inB_y, iob_inB_x, iob_inB_type_idx;
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int iob_out_y, iob_out_x, iob_out_type_idx;
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int logic_y, logic_x, logic_type_idx;
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net_idx_t inA_net, inB_net, out_net;
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int rc;
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if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
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XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING))) FAIL(rc);
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if ((rc = fpga_find_iob(&model, "P45", &iob_inA_y, &iob_inA_x,
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&iob_inA_type_idx))) FAIL(rc);
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if ((rc = fdev_iob_input(&model, iob_inA_y, iob_inA_x,
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iob_inA_type_idx, IO_LVCMOS33))) FAIL(rc);
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if ((rc = fpga_find_iob(&model, "P46", &iob_inB_y, &iob_inB_x,
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&iob_inB_type_idx))) FAIL(rc);
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if ((rc = fdev_iob_input(&model, iob_inB_y, iob_inB_x,
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iob_inB_type_idx, IO_LVCMOS33))) FAIL(rc);
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if ((rc = fpga_find_iob(&model, "P48", &iob_out_y, &iob_out_x,
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&iob_out_type_idx))) FAIL(rc);
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if ((rc = fdev_iob_output(&model, iob_out_y, iob_out_x,
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iob_out_type_idx, IO_LVCMOS33))) FAIL(rc);
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logic_y = 68;
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logic_x = 13;
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logic_type_idx = DEV_LOG_X;
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if ((rc = fdev_logic_a2d_lut(&model, logic_y, logic_x, logic_type_idx,
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LUT_D, 6, "A3*A5", ZTERM))) FAIL(rc);
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if ((rc = fnet_new(&model, &inA_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inA_net, iob_inA_y, iob_inA_x,
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DEV_IOB, iob_inA_type_idx, IOB_OUT_I))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inA_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LI_D3))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, inA_net))) FAIL(rc);
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if ((rc = fnet_new(&model, &inB_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inB_net, iob_inB_y, iob_inB_x,
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DEV_IOB, iob_inB_type_idx, IOB_OUT_I))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inB_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LI_D5))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, inB_net))) FAIL(rc);
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if ((rc = fnet_new(&model, &out_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, out_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LO_D))) FAIL(rc);
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if ((rc = fnet_add_port(&model, out_net, iob_out_y, iob_out_x,
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DEV_IOB, iob_out_type_idx, IOB_IN_O))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, out_net))) FAIL(rc);
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if ((rc = write_floorplan(stdout, &model, FP_DEFAULT))) FAIL(rc);
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return EXIT_SUCCESS;
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fail:
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return rc;
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}
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