207 lines
7.0 KiB
C
207 lines
7.0 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include "model.h"
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#include "floorplan.h"
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#include "control.h"
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/*
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This C design corresponds to the following Verilog:
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module blinking(input clk, output led);
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// synthesis attribute LOC clk "P55 | IOSTANDARD = LVCMOS33"
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// synthesis attribute LOC led "P48 | SLEW = QUIETIO | DRIVE = 8"
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reg [14:0] counter;
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always @(posedge clk) counter <= counter + 1;
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assign led = counter[14];
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endmodule
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*/
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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int param_bits;
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const char *param_clock_pin, *param_led_pin;
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int iob_clk_y, iob_clk_x, iob_clk_type_idx;
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int iob_led_y, iob_led_x, iob_led_type_idx;
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int logic_y, logic_x, logic_type_idx;
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struct fpgadev_logic logic_cfg;
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net_idx_t net;
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if (cmdline_help(argc, argv)) {
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printf( " %*s [-Dbits=14|23]\n"
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" %*s [-Dclock_pin=IO_L30N_GCLK0_USERCCLK_2|...]\n"
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" %*s [-Dled_pin=IO_L48P_D7_2|...]\n"
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"\n", (int) strlen(*argv), "",
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(int) strlen(*argv), "", (int) strlen(*argv), "");
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return 0;
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}
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if (!(param_bits = cmdline_intvar(argc, argv, "bits")))
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param_bits = 14;
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if (!(param_clock_pin = cmdline_strvar(argc, argv, "clock_pin")))
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param_clock_pin = "IO_L30N_GCLK0_USERCCLK_2";
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if (!(param_led_pin = cmdline_strvar(argc, argv, "led_pin")))
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param_led_pin = "IO_L48P_D7_2";
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fpga_build_model(&model, cmdline_part(argc, argv),
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cmdline_package(argc, argv));
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fpga_find_iob(&model, xc6_find_pkg_pin(model.pkg, param_clock_pin),
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&iob_clk_y, &iob_clk_x, &iob_clk_type_idx);
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fdev_iob_input(&model, iob_clk_y, iob_clk_x, iob_clk_type_idx,
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IO_LVCMOS33);
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fpga_find_iob(&model, xc6_find_pkg_pin(model.pkg, param_led_pin),
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&iob_led_y, &iob_led_x, &iob_led_type_idx);
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fdev_iob_output(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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IO_LVCMOS25);
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fdev_iob_slew(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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SLEW_QUIETIO);
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fdev_iob_drive(&model, iob_led_y, iob_led_x, iob_led_type_idx,
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8);
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logic_y = 58;
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logic_x = 13;
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logic_type_idx = DEV_LOG_M_OR_L;
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CLEAR(logic_cfg);
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logic_cfg.a2d[LUT_A].lut6 = "(A6+~A6)*(~A5)";
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logic_cfg.a2d[LUT_A].lut5 = "1";
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logic_cfg.a2d[LUT_A].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_A].ff = FF_FF;
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logic_cfg.a2d[LUT_A].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_A].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_B].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_B].lut5 = "0";
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logic_cfg.a2d[LUT_B].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_B].ff = FF_FF;
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logic_cfg.a2d[LUT_B].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_B].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_C].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_C].lut5 = "0";
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logic_cfg.a2d[LUT_C].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_C].ff = FF_FF;
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logic_cfg.a2d[LUT_C].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_C].ff_srinit = FF_SRINIT0;
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logic_cfg.a2d[LUT_D].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_D].lut5 = "0";
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logic_cfg.a2d[LUT_D].cy0 = CY0_O5;
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logic_cfg.a2d[LUT_D].ff = FF_FF;
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logic_cfg.a2d[LUT_D].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_D].ff_srinit = FF_SRINIT0;
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logic_cfg.clk_inv = CLKINV_CLK;
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logic_cfg.sync_attr = SYNCATTR_ASYNC;
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logic_cfg.precyinit = PRECYINIT_0;
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logic_cfg.cout_used = 1;
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fdev_logic_setconf(&model, logic_y, logic_x, logic_type_idx, &logic_cfg);
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logic_y = 57;
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logic_cfg.precyinit = 0;
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logic_cfg.a2d[LUT_A].lut6 = "(A6+~A6)*(A5)";
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logic_cfg.a2d[LUT_A].lut5 = "0";
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fdev_logic_setconf(&model, logic_y, logic_x, logic_type_idx, &logic_cfg);
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logic_y = 56;
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fdev_logic_setconf(&model, logic_y, logic_x, logic_type_idx, &logic_cfg);
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logic_y = 55;
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logic_cfg.cout_used = 0;
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logic_cfg.a2d[LUT_C].lut6 = "A5";
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logic_cfg.a2d[LUT_C].lut5 = 0;
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logic_cfg.a2d[LUT_C].cy0 = 0;
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logic_cfg.a2d[LUT_C].ff = FF_FF;
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logic_cfg.a2d[LUT_C].ff_mux = MUX_XOR;
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logic_cfg.a2d[LUT_C].ff_srinit = FF_SRINIT0;
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CLEAR(logic_cfg.a2d[LUT_D]);
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fdev_logic_setconf(&model, logic_y, logic_x, logic_type_idx, &logic_cfg);
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// clock to logic devs
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fnet_new(&model, &net);
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fnet_add_port(&model, net, iob_clk_y, iob_clk_x, DEV_IOB,
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iob_clk_type_idx, IOB_OUT_I);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CLK);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CLK);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CLK);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CLK);
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fnet_route(&model, net);
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// vcc to logic devs
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_A6);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_B6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_A6);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_B6);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C6);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_D6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_A6);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_B6);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C6);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_D6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_A6);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_B6);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C6);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_D6);
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fnet_vcc_gnd(&model, net, /*is_vcc*/ 1);
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// carry chain
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CIN);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_COUT);
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fnet_route(&model, net);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 56, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CIN);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_COUT);
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fnet_route(&model, net);
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 57, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_CIN);
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fnet_add_port(&model, net, 58, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_COUT);
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fnet_route(&model, net);
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// bit chain
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{
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int out_pin[] = {LO_AQ, LO_BQ, LO_CQ, LO_DQ};
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int in_pin[] = {LI_A5, LI_B5, LI_C5, LI_D5};
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int cur_y, i;
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for (cur_y = 58; cur_y >= 55; cur_y--) {
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for (i = 0; i < 4; i++) {
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if (cur_y == 55 && i >= 2)
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break;
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fnet_new(&model, &net);
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fnet_add_port(&model, net, cur_y, 13, DEV_LOGIC, DEV_LOG_M_OR_L, out_pin[i]);
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fnet_add_port(&model, net, cur_y, 13, DEV_LOGIC, DEV_LOG_M_OR_L, in_pin[i]);
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fnet_route(&model, net);
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}
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}
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}
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fnet_new(&model, &net);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LO_CQ);
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fnet_add_port(&model, net, 55, 13, DEV_LOGIC, DEV_LOG_M_OR_L, LI_C5);
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fnet_add_port(&model, net, iob_led_y, iob_led_x, DEV_IOB,
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iob_led_type_idx, IOB_IN_O);
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fnet_route(&model, net);
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write_floorplan(stdout, &model, FP_DEFAULT);
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return fpga_free_model(&model);
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}
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