108 lines
3.5 KiB
Plaintext
108 lines
3.5 KiB
Plaintext
Introduction
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fpgatools converts the configuration of an FPGA between
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JSON and bitstream representation.
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The only supported chip at this time is the xc6slx9, a 45nm-generation
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FPGA with 5720 6-input LUTs, block ram and multiply-accumulate
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resources.
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Also not included are place and route tools or other higher-level
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logic optimization, synthesis, Verilog, HLS, etc.
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Future work on integrating with graywolf or yosys might be an option.
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If you have ideas in that direction, please email the author at
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wspraul@q-ag.de
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*) educational resource
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*) have fun and experiment with every feature of the chip
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*) command-line tools, text-based file formats
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*) supported platform: Linux
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*) free software, released into the public domain (see
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UNLICENSE for details)
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FAQ
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todo
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Libraries
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- libfpga-control programmatic access to libfpga-model
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- libfpga-model in-memory representation of the FPGA
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- libfpga-floorplan reads and writes .fp floorplan files
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- libfpga-bit reads and writes .bit bitstream files
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Design Utilities
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- hello_world outputs an AND gate floorplan to stdout
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- blinking_led outputs blinking led design to stdout
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- fpinfo outputs information about tiles, devices, ports,
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connections and switches in a floorplan
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- fp2bit converts .fp floorplan into .bit bitstream
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- bit2fp converts .bit bitstream into .fp floorplan
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- draw_svg_tiles draws a simple .svg showing tile types
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fpgatools Development Utilities
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- autotest test suite
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- sort_seq sorts line-based text file by sequence numbers in strings
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- merge_seq merges a pre-sorted text file into wire sequences
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- pair2net reads the first two words per line and builds nets
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- hstrrep high-speed hashed array based search and replace util
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Profiling
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~# time ./hello_world
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~# perf record ./hello_world
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~# perf annotate
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~# perf report
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TODO (as of 2015-03)
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short-term (3 months):
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* support block memory
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-> write block_mem autotest
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* support macc
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* support pll_adv
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* support dcm
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* support ilogic2/ologic2
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mid-term (12 months):
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* example: counter (including clock, jtag)
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* more cases in logic block configuration
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* autotest: fix bugs in lut_encoding, logic_cfg, routing_sw, io_sw tests
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* autotest: protect stderr of diff executable in autotest log
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* several places might benefit from a bison parser:
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- switchbox description into bit parser/generator (bit_frames.c)
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- inter-tile wire connections (model_conns.c)
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- configure devices and route wires
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cleanup (whenever convenient):
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* use tile flags instead of tile names
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* model connections and switches together rather than separately
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* describe more wire names/meanings with integers instead of strings
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* move all part-specific static data into xc_info()
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long-term (>12 months):
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* auto-crc calculation in .bit file
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* MCB switches and connections
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* maybe fp2bit should natively write ieee1532 and separate tools convert
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from ieee1532 to .bit and other formats
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* design fpga core that uses high-speed icap/reconfig to process data
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* example: j1 soc
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* support chips other than xc6slx9, maybe xc7a35 or xc7a100
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ChangeLog
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2012-12-20
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* Second design verified: blinking_led is a clocked design where the clock
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increments a counter and the highest bit of the counter drives a LED.
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2012-09-24
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* First design verified: hello_world is an unclocked AND gate design
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which was verified in a xc6slx9.
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2012-08-20
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* Beginning of full fidelity circle with model, floorplan, conversion
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between floorplan and binary configuration formats.
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2012-06-03
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* Project started.
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