101 lines
3.5 KiB
Plaintext
101 lines
3.5 KiB
Plaintext
Introduction
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fpgatools is a toolchain to program field-programmable gate arrays
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(FPGAs). The only supported chip at this time is the xc6slx9, a cheap
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(ca. 7 USD) but powerful 45nm-generation chip with 5720 6-input LUTs,
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block ram and multiply-accumulate devices.
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The long-term goals of fpgatools are:
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*) reach the maximum physical performance of the chip
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*) fast development cycles
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*) independent toolchain that only depends on other free software
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*) bootstrap on chip, i.e. program the fpga from a softcore running
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on the same fpga
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*) complete package including all tools to get started such as jtag,
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debugging, parts data and designs for prototyping hardware
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*) work towards a design flow that includes later manufacturing
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in different ASIC processes, include information about ASIC
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processes, libraries, GDS generation, etc.
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*) lightweight C implementation without GUI
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*) supported platform: Linux
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*) license: public domain
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FAQ
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todo
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Libraries
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- libfpga-cores reusable cores
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- libfpga-stdlib standard design elements on top of libfpga-control
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- libfpga-control programmatic access to libfpga-model
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- libfpga-model memory-only representation of an FPGA
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- libfpga-floorplan reads and writes .fp floorplan files
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- libfpga-bit reads and writes .bit bitstream files
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Design Utilities
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- hello_world outputs an AND gate floorplan to stdout
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- new_fp creates empty .fp floorplan file
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- fp2bit converts .fp floorplan into .bit bitstream
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- bit2fp converts .bit bitstream into .fp floorplan
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- draw_svg_tiles draws a simple .svg showing tile types
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fpgatools Development Utilities
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- autotest executes test suite
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- sort_seq sorts line-based text file by sequence numbers in strings
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- merge_seq merges a pre-sorted text file into wire sequences
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- pair2net reads the first two words per line and builds nets
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- hstrrep high-speed hashed array based search and replace util
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Design Principles
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- small independent command line utilities, no GUI
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- plain C, no C++
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- simple Makefiles
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- text-based file formats
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- automatic test suite
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- public domain software
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TODO
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short-term (1 month):
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* add lut_encoding autotest for lut6 and lut5 in a-d position
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of x(m), x(l), l and m devs
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* example: blinking_led
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* example: counter (including clock, jtag)
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* support reading iologic switches
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* autotest: fix roundtrip issues in routing_sw test
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* autotest: protect stderr of diff executable in autotest log
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* 3 Debian packages: libfpga, libfpga-doc, fpgatools
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mid-term (6 months):
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* support chips other than xc6slx9, maybe an ftg256 or fgg484-packaged
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xc6 or the xc7a100
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* more cases in switches (98% done) and inter-tile connections (15% done)
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* more cases in logic block configuration
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* configuration of bram and macc blocks, bram initialization data
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* write standard design elements for libfpga-stdlib library
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* several places might benefit from a bison parser:
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- switchbox description into bit parser/generator (bit_frames.c)
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- inter-tile wire connections (model_conns.c)
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- configure devices and route wires
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long-term (>6 months):
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* auto-crc calculation in .bit file
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* support lm32 or openrisc core, either via libfpga or iverilog backend
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* ipv6 or vnc in hardware?
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* iverilog fpga backend
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ChangeLog
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2012-09-24
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* First design verified: hello_world is an unclocked AND gate design
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which was verified in a xc6slx9.
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2012-08-20
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* Beginning of full fidelity circle with model, floorplan, conversion
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between floorplan and binary configuration formats.
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2012-06-03
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* Project started.
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