From 32c5af0442d3dedbd1207ae7b283a5e5ffbc77cf Mon Sep 17 00:00:00 2001 From: Matthew Flatt Date: Thu, 9 Jul 2020 22:18:56 +0000 Subject: [PATCH] arm64: fix unsafe bitwise shift by 0 and unsafe $fxu< on 0 original commit: 742fe456e3b20caf02156f0c2e0f906cb6fa579f --- s/arm64.ss | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/s/arm64.ss b/s/arm64.ss index e52987f91c..bcf4341c40 100644 --- a/s/arm64.ss +++ b/s/arm64.ss @@ -747,12 +747,12 @@ [(op (y neg-unsigned12) (x ur)) (let ([info (if (eq? op 'eq?) info-cc-eq (make-info-condition-code op #t #t))]) (values '() `(asm ,info ,(asm-relop info #t) ,x ,y)))] - [(op (x ur) (y neg-unsigned12)) - (let ([info (if (eq? op 'eq?) info-cc-eq (make-info-condition-code op #f #t))]) - (values '() `(asm ,info ,(asm-relop info #t) ,x ,y)))] [(op (x ur) (y ur unsigned12)) (let ([info (if (eq? op 'eq?) info-cc-eq (make-info-condition-code op #f #t))]) - (values '() `(asm ,info ,(asm-relop info #f) ,x ,y)))]) + (values '() `(asm ,info ,(asm-relop info #f) ,x ,y)))] + [(op (x ur) (y neg-unsigned12)) + (let ([info (if (eq? op 'eq?) info-cc-eq (make-info-condition-code op #f #t))]) + (values '() `(asm ,info ,(asm-relop info #t) ,x ,y)))]) (define-instruction pred (condition-code) [(op) (values '() `(asm ,info ,(asm-condition-code info)))]) @@ -2499,11 +2499,16 @@ ;; When `n` fits in a fixnum, the compiler may generate ;; a bad shift that is under a guard, so force it to 63 bits (let ([n (fxand n 63)]) - (case op - [(sll) (emit lsli dest src0 n code*)] - [(srl) (emit lsri dest src0 n code*)] - [(sra) (emit asri dest src0 n code*)] - [else (sorry! 'shiftop "unrecognized ~s" op)]))] + (cond + [(fx= n 0) + ;; shift by 0 is just a move + (emit mov dest src0 code*)] + [else + (case op + [(sll) (emit lsli dest src0 n code*)] + [(srl) (emit lsri dest src0 n code*)] + [(sra) (emit asri dest src0 n code*)] + [else (sorry! 'shiftop "unrecognized ~s" op)])]))] [else (case op [(sll) (emit lsl dest src0 src1 code*)]